drivers/mmc/sdhci.c

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Back ported to the 8xx platform (from the 8260 platform) by
   8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <sdhci.h>
  16
  17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  19 #else
  20 void *aligned_buffer;
  21 #endif
  22
  23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  24 {
  25         unsigned long timeout;
  26
  27         /* Wait max 100 ms */
  28         timeout = 100;
  29         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  30         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  31                 if (timeout == 0) {
  32                         printf("%s: Reset 0x%x never completed.\n",
  33                                __func__, (int)mask);
  34                         return;
  35                 }
  36                 timeout--;
  37                 udelay(1000);
  38         }
  39 }
  40
  41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  42 {
  43         int i;
  44         if (cmd->resp_type & MMC_RSP_136) {
  45                 /* CRC is stripped so we need to do some shifting. */
  46                 for (i = 0; i < 4; i++) {
  47                         cmd->response[i] = sdhci_readl(host,
  48                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  49                         if (i != 3)
  50                                 cmd->response[i] |= sdhci_readb(host,
  51                                                 SDHCI_RESPONSE + (3-i)*4-1);
  52                 }
  53         } else {
  54                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  55         }
  56 }
  57
  58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  59 {
  60         int i;
  61         char *offs;
  62         for (i = 0; i < data->blocksize; i += 4) {
  63                 offs = data->dest + i;
  64                 if (data->flags == MMC_DATA_READ)
  65                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  66                 else
  67                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  68         }
  69 }
  70
  71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  72                                 unsigned int start_addr)
  73 {
  74         unsigned int stat, rdy, mask, timeout, block = 0;
  75 #ifdef CONFIG_MMC_SDMA
  76         unsigned char ctrl;
  77         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  78         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  79         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  80 #endif
  81
  82         timeout = 1000000;
  83         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  84         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  85         do {
  86                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  87                 if (stat & SDHCI_INT_ERROR) {
  88                         printf("%s: Error detected in status(0x%X)!\n",
  89                                __func__, stat);
  90                         return -1;
  91                 }
  92                 if (stat & rdy) {
  93                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  94                                 continue;
  95                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  96                         sdhci_transfer_pio(host, data);
  97                         data->dest += data->blocksize;
  98                         if (++block >= data->blocks)
  99                                 break;
 100                 }
 101 #ifdef CONFIG_MMC_SDMA
 102                 if (stat & SDHCI_INT_DMA_END) {
 103                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 104                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 105                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 106                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 107                 }
 108 #endif
 109                 if (timeout-- > 0)
 110                         udelay(10);
 111                 else {
 112                         printf("%s: Transfer data timeout\n", __func__);
 113                         return -1;
 114                 }
 115         } while (!(stat & SDHCI_INT_DATA_END));
 116         return 0;
 117 }
 118
 119 /*
 120  * No command will be sent by driver if card is busy, so driver must wait
 121  * for card ready state.
 122  * Every time when card is busy after timeout then (last) timeout value will be
 123  * increased twice but only if it doesn't exceed global defined maximum.
 124  * Each function call will use last timeout value. Max timeout can be redefined
 125  * in board config file.
 126  */
 127 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
 128 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT            3200
 129 #endif
 130 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT        100
 131 #define SDHCI_READ_STATUS_TIMEOUT               1000
 132
 133 #ifdef CONFIG_DM_MMC_OPS
 134 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 135                               struct mmc_data *data)
 136 {
 137         struct mmc *mmc = mmc_get_mmc_dev(dev);
 138
 139 #else
 140 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 141                               struct mmc_data *data)
 142 {
 143 #endif
 144         struct sdhci_host *host = mmc->priv;
 145         unsigned int stat = 0;
 146         int ret = 0;
 147         int trans_bytes = 0, is_aligned = 1;
 148         u32 mask, flags, mode;
 149         unsigned int time = 0, start_addr = 0;
 150         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 151         unsigned start = get_timer(0);
 152
 153         /* Timeout unit - ms */
 154         static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
 155
 156         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 157         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 158
 159         /* We shouldn't wait for data inihibit for stop commands, even
 160            though they might use busy signaling */
 161         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 162                 mask &= ~SDHCI_DATA_INHIBIT;
 163
 164         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 165                 if (time >= cmd_timeout) {
 166                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 167                         if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
 168                                 cmd_timeout += cmd_timeout;
 169                                 printf("timeout increasing to: %u ms.\n",
 170                                        cmd_timeout);
 171                         } else {
 172                                 puts("timeout.\n");
 173                                 return COMM_ERR;
 174                         }
 175                 }
 176                 time++;
 177                 udelay(1000);
 178         }
 179
 180         mask = SDHCI_INT_RESPONSE;
 181         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 182                 flags = SDHCI_CMD_RESP_NONE;
 183         else if (cmd->resp_type & MMC_RSP_136)
 184                 flags = SDHCI_CMD_RESP_LONG;
 185         else if (cmd->resp_type & MMC_RSP_BUSY) {
 186                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 187                 if (data)
 188                         mask |= SDHCI_INT_DATA_END;
 189         } else
 190                 flags = SDHCI_CMD_RESP_SHORT;
 191
 192         if (cmd->resp_type & MMC_RSP_CRC)
 193                 flags |= SDHCI_CMD_CRC;
 194         if (cmd->resp_type & MMC_RSP_OPCODE)
 195                 flags |= SDHCI_CMD_INDEX;
 196         if (data)
 197                 flags |= SDHCI_CMD_DATA;
 198
 199         /* Set Transfer mode regarding to data flag */
 200         if (data != 0) {
 201                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 202                 mode = SDHCI_TRNS_BLK_CNT_EN;
 203                 trans_bytes = data->blocks * data->blocksize;
 204                 if (data->blocks > 1)
 205                         mode |= SDHCI_TRNS_MULTI;
 206
 207                 if (data->flags == MMC_DATA_READ)
 208                         mode |= SDHCI_TRNS_READ;
 209
 210 #ifdef CONFIG_MMC_SDMA
 211                 if (data->flags == MMC_DATA_READ)
 212                         start_addr = (unsigned long)data->dest;
 213                 else
 214                         start_addr = (unsigned long)data->src;
 215                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 216                                 (start_addr & 0x7) != 0x0) {
 217                         is_aligned = 0;
 218                         start_addr = (unsigned long)aligned_buffer;
 219                         if (data->flags != MMC_DATA_READ)
 220                                 memcpy(aligned_buffer, data->src, trans_bytes);
 221                 }
 222
 223 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 224                 /*
 225                  * Always use this bounce-buffer when
 226                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 227                  */
 228                 is_aligned = 0;
 229                 start_addr = (unsigned long)aligned_buffer;
 230                 if (data->flags != MMC_DATA_READ)
 231                         memcpy(aligned_buffer, data->src, trans_bytes);
 232 #endif
 233
 234                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 235                 mode |= SDHCI_TRNS_DMA;
 236 #endif
 237                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 238                                 data->blocksize),
 239                                 SDHCI_BLOCK_SIZE);
 240                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 241                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 242         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 243                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 244         }
 245
 246         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 247 #ifdef CONFIG_MMC_SDMA
 248         flush_cache(start_addr, trans_bytes);
 249 #endif
 250         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 251         start = get_timer(0);
 252         do {
 253                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 254                 if (stat & SDHCI_INT_ERROR)
 255                         break;
 256
 257                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 258                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 259                                 return 0;
 260                         } else {
 261                                 printf("%s: Timeout for status update!\n",
 262                                        __func__);
 263                                 return TIMEOUT;
 264                         }
 265                 }
 266         } while ((stat & mask) != mask);
 267
 268         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 269                 sdhci_cmd_done(host, cmd);
 270                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 271         } else
 272                 ret = -1;
 273
 274         if (!ret && data)
 275                 ret = sdhci_transfer_data(host, data, start_addr);
 276
 277         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 278                 udelay(1000);
 279
 280         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 281         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 282         if (!ret) {
 283                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 284                                 !is_aligned && (data->flags == MMC_DATA_READ))
 285                         memcpy(data->dest, aligned_buffer, trans_bytes);
 286                 return 0;
 287         }
 288
 289         sdhci_reset(host, SDHCI_RESET_CMD);
 290         sdhci_reset(host, SDHCI_RESET_DATA);
 291         if (stat & SDHCI_INT_TIMEOUT)
 292                 return TIMEOUT;
 293         else
 294                 return COMM_ERR;
 295 }
 296
 297 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 298 {
 299         struct sdhci_host *host = mmc->priv;
 300         unsigned int div, clk, timeout, reg;
 301
 302         /* Wait max 20 ms */
 303         timeout = 200;
 304         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 305                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 306                 if (timeout == 0) {
 307                         printf("%s: Timeout to wait cmd & data inhibit\n",
 308                                __func__);
 309                         return -1;
 310                 }
 311
 312                 timeout--;
 313                 udelay(100);
 314         }
 315
 316         reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 317         reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
 318         sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
 319
 320         if (clock == 0)
 321                 return 0;
 322
 323         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 324                 /* Version 3.00 divisors must be a multiple of 2. */
 325                 if (mmc->cfg->f_max <= clock)
 326                         div = 1;
 327                 else {
 328                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
 329                                 if ((mmc->cfg->f_max / div) <= clock)
 330                                         break;
 331                         }
 332                 }
 333         } else {
 334                 /* Version 2.00 divisors must be a power of 2. */
 335                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 336                         if ((mmc->cfg->f_max / div) <= clock)
 337                                 break;
 338                 }
 339         }
 340         div >>= 1;
 341
 342         if (host->set_clock)
 343                 host->set_clock(host->index, div);
 344
 345         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 346         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 347                 << SDHCI_DIVIDER_HI_SHIFT;
 348         clk |= SDHCI_CLOCK_INT_EN;
 349         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 350
 351         /* Wait max 20 ms */
 352         timeout = 20;
 353         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 354                 & SDHCI_CLOCK_INT_STABLE)) {
 355                 if (timeout == 0) {
 356                         printf("%s: Internal clock never stabilised.\n",
 357                                __func__);
 358                         return -1;
 359                 }
 360                 timeout--;
 361                 udelay(1000);
 362         }
 363
 364         clk |= SDHCI_CLOCK_CARD_EN;
 365         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 366         return 0;
 367 }
 368
 369 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 370 {
 371         u8 pwr = 0;
 372
 373         if (power != (unsigned short)-1) {
 374                 switch (1 << power) {
 375                 case MMC_VDD_165_195:
 376                         pwr = SDHCI_POWER_180;
 377                         break;
 378                 case MMC_VDD_29_30:
 379                 case MMC_VDD_30_31:
 380                         pwr = SDHCI_POWER_300;
 381                         break;
 382                 case MMC_VDD_32_33:
 383                 case MMC_VDD_33_34:
 384                         pwr = SDHCI_POWER_330;
 385                         break;
 386                 }
 387         }
 388
 389         if (pwr == 0) {
 390                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 391                 return;
 392         }
 393
 394         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
 395                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 396
 397         pwr |= SDHCI_POWER_ON;
 398
 399         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 400 }
 401
 402 #ifdef CONFIG_DM_MMC_OPS
 403 static int sdhci_set_ios(struct udevice *dev)
 404 {
 405         struct mmc *mmc = mmc_get_mmc_dev(dev);
 406 #else
 407 static void sdhci_set_ios(struct mmc *mmc)
 408 {
 409 #endif
 410         u32 ctrl;
 411         struct sdhci_host *host = mmc->priv;
 412
 413         if (host->set_control_reg)
 414                 host->set_control_reg(host);
 415
 416         if (mmc->clock != host->clock)
 417                 sdhci_set_clock(mmc, mmc->clock);
 418
 419         /* Set bus width */
 420         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 421         if (mmc->bus_width == 8) {
 422                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 423                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 424                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 425                         ctrl |= SDHCI_CTRL_8BITBUS;
 426         } else {
 427                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 428                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 429                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 430                 if (mmc->bus_width == 4)
 431                         ctrl |= SDHCI_CTRL_4BITBUS;
 432                 else
 433                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 434         }
 435
 436         if (mmc->clock > 26000000)
 437                 ctrl |= SDHCI_CTRL_HISPD;
 438         else
 439                 ctrl &= ~SDHCI_CTRL_HISPD;
 440
 441         if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 442                 ctrl &= ~SDHCI_CTRL_HISPD;
 443
 444         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 445 #ifdef CONFIG_DM_MMC_OPS
 446         return 0;
 447 #endif
 448 }
 449
 450 static int sdhci_init(struct mmc *mmc)
 451 {
 452         struct sdhci_host *host = mmc->priv;
 453
 454         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 455                 aligned_buffer = memalign(8, 512*1024);
 456                 if (!aligned_buffer) {
 457                         printf("%s: Aligned buffer alloc failed!!!\n",
 458                                __func__);
 459                         return -1;
 460                 }
 461         }
 462
 463         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 464
 465         if (host->quirks & SDHCI_QUIRK_NO_CD) {
 466 #if defined(CONFIG_PIC32_SDHCI)
 467                 /* PIC32 SDHCI CD errata:
 468                  * - set CD_TEST and clear CD_TEST_INS bit
 469                  */
 470                 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
 471 #else
 472                 unsigned int status;
 473
 474                 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
 475                         SDHCI_HOST_CONTROL);
 476
 477                 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 478                 while ((!(status & SDHCI_CARD_PRESENT)) ||
 479                     (!(status & SDHCI_CARD_STATE_STABLE)) ||
 480                     (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
 481                         status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 482 #endif
 483         }
 484
 485         /* Enable only interrupts served by the SD controller */
 486         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 487                      SDHCI_INT_ENABLE);
 488         /* Mask all sdhci interrupt sources */
 489         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 490
 491         return 0;
 492 }
 493
 494 #ifdef CONFIG_DM_MMC_OPS
 495 int sdhci_probe(struct udevice *dev)
 496 {
 497         struct mmc *mmc = mmc_get_mmc_dev(dev);
 498
 499         return sdhci_init(mmc);
 500 }
 501
 502 const struct dm_mmc_ops sdhci_ops = {
 503         .send_cmd       = sdhci_send_command,
 504         .set_ios        = sdhci_set_ios,
 505 };
 506 #else
 507 static const struct mmc_ops sdhci_ops = {
 508         .send_cmd       = sdhci_send_command,
 509         .set_ios        = sdhci_set_ios,
 510         .init           = sdhci_init,
 511 };
 512 #endif
 513
 514 int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 515                     uint caps, u32 max_clk, u32 min_clk, uint version,
 516                     uint quirks, uint host_caps)
 517 {
 518         cfg->name = name;
 519 #ifndef CONFIG_DM_MMC_OPS
 520         cfg->ops = &sdhci_ops;
 521 #endif
 522         if (max_clk)
 523                 cfg->f_max = max_clk;
 524         else {
 525                 if (version >= SDHCI_SPEC_300)
 526                         cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 527                                 SDHCI_CLOCK_BASE_SHIFT;
 528                 else
 529                         cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
 530                                 SDHCI_CLOCK_BASE_SHIFT;
 531                 cfg->f_max *= 1000000;
 532         }
 533         if (cfg->f_max == 0)
 534                 return -EINVAL;
 535         if (min_clk)
 536                 cfg->f_min = min_clk;
 537         else {
 538                 if (version >= SDHCI_SPEC_300)
 539                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 540                 else
 541                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 542         }
 543         cfg->voltages = 0;
 544         if (caps & SDHCI_CAN_VDD_330)
 545                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 546         if (caps & SDHCI_CAN_VDD_300)
 547                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 548         if (caps & SDHCI_CAN_VDD_180)
 549                 cfg->voltages |= MMC_VDD_165_195;
 550
 551         cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 552         if (version >= SDHCI_SPEC_300) {
 553                 if (caps & SDHCI_CAN_DO_8BIT)
 554                         cfg->host_caps |= MMC_MODE_8BIT;
 555         }
 556
 557         if (quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 558                 cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
 559
 560         if (host_caps)
 561                 cfg->host_caps |= host_caps;
 562
 563
 564         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 565
 566         return 0;
 567 }
 568
 569 #ifdef CONFIG_BLK
 570 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 571 {
 572         return mmc_bind(dev, mmc, cfg);
 573 }
 574 #else
 575 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 576 {
 577         unsigned int caps;
 578
 579         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 580 #ifdef CONFIG_MMC_SDMA
 581         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 582                 printf("%s: Your controller doesn't support SDMA!!\n",
 583                        __func__);
 584                 return -1;
 585         }
 586 #endif
 587
 588         if (sdhci_setup_cfg(&host->cfg, host->name, host->bus_width, caps,
 589                             max_clk, min_clk, SDHCI_GET_VERSION(host),
 590                             host->quirks, host->host_caps)) {
 591                 printf("%s: Hardware doesn't specify base clock frequency\n",
 592                        __func__);
 593                 return -EINVAL;
 594         }
 595
 596         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 597                 host->cfg.voltages |= host->voltages;
 598
 599         sdhci_reset(host, SDHCI_RESET_ALL);
 600
 601         host->mmc = mmc_create(&host->cfg, host);
 602         if (host->mmc == NULL) {
 603                 printf("%s: mmc create fail!\n", __func__);
 604                 return -1;
 605         }
 606
 607         return 0;
 608 }
 609 #endif