2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 void *aligned_buffer
= (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
;
23 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
25 unsigned long timeout
;
29 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
30 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
32 printf("%s: Reset 0x%x never completed.\n",
41 static void sdhci_cmd_done(struct sdhci_host
*host
, struct mmc_cmd
*cmd
)
44 if (cmd
->resp_type
& MMC_RSP_136
) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i
= 0; i
< 4; i
++) {
47 cmd
->response
[i
] = sdhci_readl(host
,
48 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
50 cmd
->response
[i
] |= sdhci_readb(host
,
51 SDHCI_RESPONSE
+ (3-i
)*4-1);
54 cmd
->response
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
58 static void sdhci_transfer_pio(struct sdhci_host
*host
, struct mmc_data
*data
)
62 for (i
= 0; i
< data
->blocksize
; i
+= 4) {
63 offs
= data
->dest
+ i
;
64 if (data
->flags
== MMC_DATA_READ
)
65 *(u32
*)offs
= sdhci_readl(host
, SDHCI_BUFFER
);
67 sdhci_writel(host
, *(u32
*)offs
, SDHCI_BUFFER
);
71 static int sdhci_transfer_data(struct sdhci_host
*host
, struct mmc_data
*data
,
72 unsigned int start_addr
)
74 unsigned int stat
, rdy
, mask
, timeout
, block
= 0;
75 bool transfer_done
= false;
76 #ifdef CONFIG_MMC_SDHCI_SDMA
78 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
79 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
80 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
84 rdy
= SDHCI_INT_SPACE_AVAIL
| SDHCI_INT_DATA_AVAIL
;
85 mask
= SDHCI_DATA_AVAILABLE
| SDHCI_SPACE_AVAILABLE
;
87 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
88 if (stat
& SDHCI_INT_ERROR
) {
89 printf("%s: Error detected in status(0x%X)!\n",
93 if (!transfer_done
&& (stat
& rdy
)) {
94 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
))
96 sdhci_writel(host
, rdy
, SDHCI_INT_STATUS
);
97 sdhci_transfer_pio(host
, data
);
98 data
->dest
+= data
->blocksize
;
99 if (++block
>= data
->blocks
) {
100 /* Keep looping until the SDHCI_INT_DATA_END is
101 * cleared, even if we finished sending all the
104 transfer_done
= true;
108 #ifdef CONFIG_MMC_SDHCI_SDMA
109 if (!transfer_done
&& (stat
& SDHCI_INT_DMA_END
)) {
110 sdhci_writel(host
, SDHCI_INT_DMA_END
, SDHCI_INT_STATUS
);
111 start_addr
&= ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1);
112 start_addr
+= SDHCI_DEFAULT_BOUNDARY_SIZE
;
113 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
119 printf("%s: Transfer data timeout\n", __func__
);
122 } while (!(stat
& SDHCI_INT_DATA_END
));
127 * No command will be sent by driver if card is busy, so driver must wait
128 * for card ready state.
129 * Every time when card is busy after timeout then (last) timeout value will be
130 * increased twice but only if it doesn't exceed global defined maximum.
131 * Each function call will use last timeout value.
133 #define SDHCI_CMD_MAX_TIMEOUT 3200
134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
135 #define SDHCI_READ_STATUS_TIMEOUT 1000
138 static int sdhci_send_command(struct udevice
*dev
, struct mmc_cmd
*cmd
,
139 struct mmc_data
*data
)
141 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
144 static int sdhci_send_command(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
145 struct mmc_data
*data
)
148 struct sdhci_host
*host
= mmc
->priv
;
149 unsigned int stat
= 0;
151 int trans_bytes
= 0, is_aligned
= 1;
152 u32 mask
, flags
, mode
;
153 unsigned int time
= 0, start_addr
= 0;
154 int mmc_dev
= mmc_get_blk_desc(mmc
)->devnum
;
155 unsigned start
= get_timer(0);
157 /* Timeout unit - ms */
158 static unsigned int cmd_timeout
= SDHCI_CMD_DEFAULT_TIMEOUT
;
160 mask
= SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
;
162 /* We shouldn't wait for data inihibit for stop commands, even
163 though they might use busy signaling */
164 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
165 mask
&= ~SDHCI_DATA_INHIBIT
;
167 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
168 if (time
>= cmd_timeout
) {
169 printf("%s: MMC: %d busy ", __func__
, mmc_dev
);
170 if (2 * cmd_timeout
<= SDHCI_CMD_MAX_TIMEOUT
) {
171 cmd_timeout
+= cmd_timeout
;
172 printf("timeout increasing to: %u ms.\n",
183 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
185 mask
= SDHCI_INT_RESPONSE
;
186 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
187 flags
= SDHCI_CMD_RESP_NONE
;
188 else if (cmd
->resp_type
& MMC_RSP_136
)
189 flags
= SDHCI_CMD_RESP_LONG
;
190 else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
191 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
193 mask
|= SDHCI_INT_DATA_END
;
195 flags
= SDHCI_CMD_RESP_SHORT
;
197 if (cmd
->resp_type
& MMC_RSP_CRC
)
198 flags
|= SDHCI_CMD_CRC
;
199 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
200 flags
|= SDHCI_CMD_INDEX
;
202 flags
|= SDHCI_CMD_DATA
;
204 /* Set Transfer mode regarding to data flag */
206 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
207 mode
= SDHCI_TRNS_BLK_CNT_EN
;
208 trans_bytes
= data
->blocks
* data
->blocksize
;
209 if (data
->blocks
> 1)
210 mode
|= SDHCI_TRNS_MULTI
;
212 if (data
->flags
== MMC_DATA_READ
)
213 mode
|= SDHCI_TRNS_READ
;
215 #ifdef CONFIG_MMC_SDHCI_SDMA
216 if (data
->flags
== MMC_DATA_READ
)
217 start_addr
= (unsigned long)data
->dest
;
219 start_addr
= (unsigned long)data
->src
;
220 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
221 (start_addr
& 0x7) != 0x0) {
223 start_addr
= (unsigned long)aligned_buffer
;
224 if (data
->flags
!= MMC_DATA_READ
)
225 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
228 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
230 * Always use this bounce-buffer when
231 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
234 start_addr
= (unsigned long)aligned_buffer
;
235 if (data
->flags
!= MMC_DATA_READ
)
236 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
239 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
240 mode
|= SDHCI_TRNS_DMA
;
242 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
245 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
246 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
247 } else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
248 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
251 sdhci_writel(host
, cmd
->cmdarg
, SDHCI_ARGUMENT
);
252 #ifdef CONFIG_MMC_SDHCI_SDMA
254 trans_bytes
= ALIGN(trans_bytes
, CONFIG_SYS_CACHELINE_SIZE
);
255 flush_cache(start_addr
, trans_bytes
);
258 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->cmdidx
, flags
), SDHCI_COMMAND
);
259 start
= get_timer(0);
261 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
262 if (stat
& SDHCI_INT_ERROR
)
265 if (get_timer(start
) >= SDHCI_READ_STATUS_TIMEOUT
) {
266 if (host
->quirks
& SDHCI_QUIRK_BROKEN_R1B
) {
269 printf("%s: Timeout for status update!\n",
274 } while ((stat
& mask
) != mask
);
276 if ((stat
& (SDHCI_INT_ERROR
| mask
)) == mask
) {
277 sdhci_cmd_done(host
, cmd
);
278 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
283 ret
= sdhci_transfer_data(host
, data
, start_addr
);
285 if (host
->quirks
& SDHCI_QUIRK_WAIT_SEND_CMD
)
288 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
289 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
291 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
292 !is_aligned
&& (data
->flags
== MMC_DATA_READ
))
293 memcpy(data
->dest
, aligned_buffer
, trans_bytes
);
297 sdhci_reset(host
, SDHCI_RESET_CMD
);
298 sdhci_reset(host
, SDHCI_RESET_DATA
);
299 if (stat
& SDHCI_INT_TIMEOUT
)
305 static int sdhci_set_clock(struct mmc
*mmc
, unsigned int clock
)
307 struct sdhci_host
*host
= mmc
->priv
;
308 unsigned int div
, clk
= 0, timeout
;
312 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
313 (SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
)) {
315 printf("%s: Timeout to wait cmd & data inhibit\n",
324 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
329 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
331 * Check if the Host Controller supports Programmable Clock
335 for (div
= 1; div
<= 1024; div
++) {
336 if ((host
->max_clk
/ div
) <= clock
)
341 * Set Programmable Clock Mode in the Clock
344 clk
= SDHCI_PROG_CLOCK_MODE
;
347 /* Version 3.00 divisors must be a multiple of 2. */
348 if (host
->max_clk
<= clock
) {
352 div
< SDHCI_MAX_DIV_SPEC_300
;
354 if ((host
->max_clk
/ div
) <= clock
)
361 /* Version 2.00 divisors must be a power of 2. */
362 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
363 if ((host
->max_clk
/ div
) <= clock
)
369 if (host
->ops
&& host
->ops
->set_clock
)
370 host
->ops
->set_clock(host
, div
);
372 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
373 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
374 << SDHCI_DIVIDER_HI_SHIFT
;
375 clk
|= SDHCI_CLOCK_INT_EN
;
376 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
380 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
381 & SDHCI_CLOCK_INT_STABLE
)) {
383 printf("%s: Internal clock never stabilised.\n",
391 clk
|= SDHCI_CLOCK_CARD_EN
;
392 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
396 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
400 if (power
!= (unsigned short)-1) {
401 switch (1 << power
) {
402 case MMC_VDD_165_195
:
403 pwr
= SDHCI_POWER_180
;
407 pwr
= SDHCI_POWER_300
;
411 pwr
= SDHCI_POWER_330
;
417 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
421 pwr
|= SDHCI_POWER_ON
;
423 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
427 static int sdhci_set_ios(struct udevice
*dev
)
429 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
431 static int sdhci_set_ios(struct mmc
*mmc
)
435 struct sdhci_host
*host
= mmc
->priv
;
437 if (host
->ops
&& host
->ops
->set_control_reg
)
438 host
->ops
->set_control_reg(host
);
440 if (mmc
->clock
!= host
->clock
)
441 sdhci_set_clock(mmc
, mmc
->clock
);
444 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
445 if (mmc
->bus_width
== 8) {
446 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
447 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
448 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
449 ctrl
|= SDHCI_CTRL_8BITBUS
;
451 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
452 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
453 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
454 if (mmc
->bus_width
== 4)
455 ctrl
|= SDHCI_CTRL_4BITBUS
;
457 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
460 if (mmc
->clock
> 26000000)
461 ctrl
|= SDHCI_CTRL_HISPD
;
463 ctrl
&= ~SDHCI_CTRL_HISPD
;
465 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
466 ctrl
&= ~SDHCI_CTRL_HISPD
;
468 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
470 /* If available, call the driver specific "post" set_ios() function */
471 if (host
->ops
&& host
->ops
->set_ios_post
)
472 host
->ops
->set_ios_post(host
);
477 static int sdhci_init(struct mmc
*mmc
)
479 struct sdhci_host
*host
= mmc
->priv
;
481 sdhci_reset(host
, SDHCI_RESET_ALL
);
483 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) && !aligned_buffer
) {
484 aligned_buffer
= memalign(8, 512*1024);
485 if (!aligned_buffer
) {
486 printf("%s: Aligned buffer alloc failed!!!\n",
492 sdhci_set_power(host
, fls(mmc
->cfg
->voltages
) - 1);
494 if (host
->ops
&& host
->ops
->get_cd
)
495 host
->ops
->get_cd(host
);
497 /* Enable only interrupts served by the SD controller */
498 sdhci_writel(host
, SDHCI_INT_DATA_MASK
| SDHCI_INT_CMD_MASK
,
500 /* Mask all sdhci interrupt sources */
501 sdhci_writel(host
, 0x0, SDHCI_SIGNAL_ENABLE
);
507 int sdhci_probe(struct udevice
*dev
)
509 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
511 return sdhci_init(mmc
);
514 const struct dm_mmc_ops sdhci_ops
= {
515 .send_cmd
= sdhci_send_command
,
516 .set_ios
= sdhci_set_ios
,
519 static const struct mmc_ops sdhci_ops
= {
520 .send_cmd
= sdhci_send_command
,
521 .set_ios
= sdhci_set_ios
,
526 int sdhci_setup_cfg(struct mmc_config
*cfg
, struct sdhci_host
*host
,
527 u32 f_max
, u32 f_min
)
531 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
533 #ifdef CONFIG_MMC_SDHCI_SDMA
534 if (!(caps
& SDHCI_CAN_DO_SDMA
)) {
535 printf("%s: Your controller doesn't support SDMA!!\n",
540 if (host
->quirks
& SDHCI_QUIRK_REG32_RW
)
542 sdhci_readl(host
, SDHCI_HOST_VERSION
- 2) >> 16;
544 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
546 cfg
->name
= host
->name
;
547 #ifndef CONFIG_DM_MMC
548 cfg
->ops
= &sdhci_ops
;
551 /* Check whether the clock multiplier is supported or not */
552 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
553 caps_1
= sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
554 host
->clk_mul
= (caps_1
& SDHCI_CLOCK_MUL_MASK
) >>
555 SDHCI_CLOCK_MUL_SHIFT
;
558 if (host
->max_clk
== 0) {
559 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
560 host
->max_clk
= (caps
& SDHCI_CLOCK_V3_BASE_MASK
) >>
561 SDHCI_CLOCK_BASE_SHIFT
;
563 host
->max_clk
= (caps
& SDHCI_CLOCK_BASE_MASK
) >>
564 SDHCI_CLOCK_BASE_SHIFT
;
565 host
->max_clk
*= 1000000;
567 host
->max_clk
*= host
->clk_mul
;
569 if (host
->max_clk
== 0) {
570 printf("%s: Hardware doesn't specify base clock frequency\n",
574 if (f_max
&& (f_max
< host
->max_clk
))
577 cfg
->f_max
= host
->max_clk
;
581 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
582 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_300
;
584 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_200
;
587 if (caps
& SDHCI_CAN_VDD_330
)
588 cfg
->voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
589 if (caps
& SDHCI_CAN_VDD_300
)
590 cfg
->voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
591 if (caps
& SDHCI_CAN_VDD_180
)
592 cfg
->voltages
|= MMC_VDD_165_195
;
594 if (host
->quirks
& SDHCI_QUIRK_BROKEN_VOLTAGE
)
595 cfg
->voltages
|= host
->voltages
;
597 cfg
->host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
;
599 /* Since Host Controller Version3.0 */
600 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
601 if (!(caps
& SDHCI_CAN_DO_8BIT
))
602 cfg
->host_caps
&= ~MMC_MODE_8BIT
;
606 cfg
->host_caps
|= host
->host_caps
;
608 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
614 int sdhci_bind(struct udevice
*dev
, struct mmc
*mmc
, struct mmc_config
*cfg
)
616 return mmc_bind(dev
, mmc
, cfg
);
619 int add_sdhci(struct sdhci_host
*host
, u32 f_max
, u32 f_min
)
623 ret
= sdhci_setup_cfg(&host
->cfg
, host
, f_max
, f_min
);
627 host
->mmc
= mmc_create(&host
->cfg
, host
);
628 if (host
->mmc
== NULL
) {
629 printf("%s: mmc create fail!\n", __func__
);