2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
17 void *aligned_buffer
= (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
;
22 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
24 unsigned long timeout
;
28 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
29 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
31 printf("%s: Reset 0x%x never completed.\n",
40 static void sdhci_cmd_done(struct sdhci_host
*host
, struct mmc_cmd
*cmd
)
43 if (cmd
->resp_type
& MMC_RSP_136
) {
44 /* CRC is stripped so we need to do some shifting. */
45 for (i
= 0; i
< 4; i
++) {
46 cmd
->response
[i
] = sdhci_readl(host
,
47 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
49 cmd
->response
[i
] |= sdhci_readb(host
,
50 SDHCI_RESPONSE
+ (3-i
)*4-1);
53 cmd
->response
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
57 static void sdhci_transfer_pio(struct sdhci_host
*host
, struct mmc_data
*data
)
61 for (i
= 0; i
< data
->blocksize
; i
+= 4) {
62 offs
= data
->dest
+ i
;
63 if (data
->flags
== MMC_DATA_READ
)
64 *(u32
*)offs
= sdhci_readl(host
, SDHCI_BUFFER
);
66 sdhci_writel(host
, *(u32
*)offs
, SDHCI_BUFFER
);
70 static int sdhci_transfer_data(struct sdhci_host
*host
, struct mmc_data
*data
,
71 unsigned int start_addr
)
73 unsigned int stat
, rdy
, mask
, timeout
, block
= 0;
74 #ifdef CONFIG_MMC_SDMA
76 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
77 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
78 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
82 rdy
= SDHCI_INT_SPACE_AVAIL
| SDHCI_INT_DATA_AVAIL
;
83 mask
= SDHCI_DATA_AVAILABLE
| SDHCI_SPACE_AVAILABLE
;
85 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
86 if (stat
& SDHCI_INT_ERROR
) {
87 printf("%s: Error detected in status(0x%X)!\n",
92 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
))
94 sdhci_writel(host
, rdy
, SDHCI_INT_STATUS
);
95 sdhci_transfer_pio(host
, data
);
96 data
->dest
+= data
->blocksize
;
97 if (++block
>= data
->blocks
)
100 #ifdef CONFIG_MMC_SDMA
101 if (stat
& SDHCI_INT_DMA_END
) {
102 sdhci_writel(host
, SDHCI_INT_DMA_END
, SDHCI_INT_STATUS
);
103 start_addr
&= ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1);
104 start_addr
+= SDHCI_DEFAULT_BOUNDARY_SIZE
;
105 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
111 printf("%s: Transfer data timeout\n", __func__
);
114 } while (!(stat
& SDHCI_INT_DATA_END
));
119 * No command will be sent by driver if card is busy, so driver must wait
120 * for card ready state.
121 * Every time when card is busy after timeout then (last) timeout value will be
122 * increased twice but only if it doesn't exceed global defined maximum.
123 * Each function call will use last timeout value. Max timeout can be redefined
124 * in board config file.
126 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
127 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
129 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
130 #define SDHCI_READ_STATUS_TIMEOUT 1000
132 static int sdhci_send_command(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
133 struct mmc_data
*data
)
135 struct sdhci_host
*host
= mmc
->priv
;
136 unsigned int stat
= 0;
138 int trans_bytes
= 0, is_aligned
= 1;
139 u32 mask
, flags
, mode
;
140 unsigned int time
= 0, start_addr
= 0;
141 int mmc_dev
= mmc_get_blk_desc(mmc
)->devnum
;
142 unsigned start
= get_timer(0);
144 /* Timeout unit - ms */
145 static unsigned int cmd_timeout
= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
;
147 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
148 mask
= SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
;
150 /* We shouldn't wait for data inihibit for stop commands, even
151 though they might use busy signaling */
152 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
153 mask
&= ~SDHCI_DATA_INHIBIT
;
155 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
156 if (time
>= cmd_timeout
) {
157 printf("%s: MMC: %d busy ", __func__
, mmc_dev
);
158 if (2 * cmd_timeout
<= CONFIG_SDHCI_CMD_MAX_TIMEOUT
) {
159 cmd_timeout
+= cmd_timeout
;
160 printf("timeout increasing to: %u ms.\n",
171 mask
= SDHCI_INT_RESPONSE
;
172 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
173 flags
= SDHCI_CMD_RESP_NONE
;
174 else if (cmd
->resp_type
& MMC_RSP_136
)
175 flags
= SDHCI_CMD_RESP_LONG
;
176 else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
177 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
178 mask
|= SDHCI_INT_DATA_END
;
180 flags
= SDHCI_CMD_RESP_SHORT
;
182 if (cmd
->resp_type
& MMC_RSP_CRC
)
183 flags
|= SDHCI_CMD_CRC
;
184 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
185 flags
|= SDHCI_CMD_INDEX
;
187 flags
|= SDHCI_CMD_DATA
;
189 /* Set Transfer mode regarding to data flag */
191 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
192 mode
= SDHCI_TRNS_BLK_CNT_EN
;
193 trans_bytes
= data
->blocks
* data
->blocksize
;
194 if (data
->blocks
> 1)
195 mode
|= SDHCI_TRNS_MULTI
;
197 if (data
->flags
== MMC_DATA_READ
)
198 mode
|= SDHCI_TRNS_READ
;
200 #ifdef CONFIG_MMC_SDMA
201 if (data
->flags
== MMC_DATA_READ
)
202 start_addr
= (unsigned long)data
->dest
;
204 start_addr
= (unsigned long)data
->src
;
205 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
206 (start_addr
& 0x7) != 0x0) {
208 start_addr
= (unsigned long)aligned_buffer
;
209 if (data
->flags
!= MMC_DATA_READ
)
210 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
213 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
215 * Always use this bounce-buffer when
216 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
219 start_addr
= (unsigned long)aligned_buffer
;
220 if (data
->flags
!= MMC_DATA_READ
)
221 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
224 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
225 mode
|= SDHCI_TRNS_DMA
;
227 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
230 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
231 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
232 } else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
233 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
236 sdhci_writel(host
, cmd
->cmdarg
, SDHCI_ARGUMENT
);
237 #ifdef CONFIG_MMC_SDMA
238 flush_cache(start_addr
, trans_bytes
);
240 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->cmdidx
, flags
), SDHCI_COMMAND
);
241 start
= get_timer(0);
243 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
244 if (stat
& SDHCI_INT_ERROR
)
246 } while (((stat
& mask
) != mask
) &&
247 (get_timer(start
) < SDHCI_READ_STATUS_TIMEOUT
));
249 if (get_timer(start
) >= SDHCI_READ_STATUS_TIMEOUT
) {
250 if (host
->quirks
& SDHCI_QUIRK_BROKEN_R1B
)
253 printf("%s: Timeout for status update!\n", __func__
);
258 if ((stat
& (SDHCI_INT_ERROR
| mask
)) == mask
) {
259 sdhci_cmd_done(host
, cmd
);
260 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
265 ret
= sdhci_transfer_data(host
, data
, start_addr
);
267 if (host
->quirks
& SDHCI_QUIRK_WAIT_SEND_CMD
)
270 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
271 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
273 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
274 !is_aligned
&& (data
->flags
== MMC_DATA_READ
))
275 memcpy(data
->dest
, aligned_buffer
, trans_bytes
);
279 sdhci_reset(host
, SDHCI_RESET_CMD
);
280 sdhci_reset(host
, SDHCI_RESET_DATA
);
281 if (stat
& SDHCI_INT_TIMEOUT
)
287 static int sdhci_set_clock(struct mmc
*mmc
, unsigned int clock
)
289 struct sdhci_host
*host
= mmc
->priv
;
290 unsigned int div
, clk
, timeout
, reg
;
294 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
295 (SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
)) {
297 printf("%s: Timeout to wait cmd & data inhibit\n",
306 reg
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
307 reg
&= ~SDHCI_CLOCK_CARD_EN
;
308 sdhci_writew(host
, reg
, SDHCI_CLOCK_CONTROL
);
313 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
314 /* Version 3.00 divisors must be a multiple of 2. */
315 if (mmc
->cfg
->f_max
<= clock
)
318 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
; div
+= 2) {
319 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
324 /* Version 2.00 divisors must be a power of 2. */
325 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
326 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
333 host
->set_clock(host
->index
, div
);
335 clk
= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
336 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
337 << SDHCI_DIVIDER_HI_SHIFT
;
338 clk
|= SDHCI_CLOCK_INT_EN
;
339 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
343 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
344 & SDHCI_CLOCK_INT_STABLE
)) {
346 printf("%s: Internal clock never stabilised.\n",
354 clk
|= SDHCI_CLOCK_CARD_EN
;
355 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
359 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
363 if (power
!= (unsigned short)-1) {
364 switch (1 << power
) {
365 case MMC_VDD_165_195
:
366 pwr
= SDHCI_POWER_180
;
370 pwr
= SDHCI_POWER_300
;
374 pwr
= SDHCI_POWER_330
;
380 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
384 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
385 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
387 pwr
|= SDHCI_POWER_ON
;
389 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
392 static void sdhci_set_ios(struct mmc
*mmc
)
395 struct sdhci_host
*host
= mmc
->priv
;
397 if (host
->set_control_reg
)
398 host
->set_control_reg(host
);
400 if (mmc
->clock
!= host
->clock
)
401 sdhci_set_clock(mmc
, mmc
->clock
);
404 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
405 if (mmc
->bus_width
== 8) {
406 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
407 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
408 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
409 ctrl
|= SDHCI_CTRL_8BITBUS
;
411 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
412 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
413 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
414 if (mmc
->bus_width
== 4)
415 ctrl
|= SDHCI_CTRL_4BITBUS
;
417 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
420 if (mmc
->clock
> 26000000)
421 ctrl
|= SDHCI_CTRL_HISPD
;
423 ctrl
&= ~SDHCI_CTRL_HISPD
;
425 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
426 ctrl
&= ~SDHCI_CTRL_HISPD
;
428 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
431 static int sdhci_init(struct mmc
*mmc
)
433 struct sdhci_host
*host
= mmc
->priv
;
435 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) && !aligned_buffer
) {
436 aligned_buffer
= memalign(8, 512*1024);
437 if (!aligned_buffer
) {
438 printf("%s: Aligned buffer alloc failed!!!\n",
444 sdhci_set_power(host
, fls(mmc
->cfg
->voltages
) - 1);
446 if (host
->quirks
& SDHCI_QUIRK_NO_CD
) {
447 #if defined(CONFIG_PIC32_SDHCI)
448 /* PIC32 SDHCI CD errata:
449 * - set CD_TEST and clear CD_TEST_INS bit
451 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST
, SDHCI_HOST_CONTROL
);
455 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST_INS
| SDHCI_CTRL_CD_TEST
,
458 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
459 while ((!(status
& SDHCI_CARD_PRESENT
)) ||
460 (!(status
& SDHCI_CARD_STATE_STABLE
)) ||
461 (!(status
& SDHCI_CARD_DETECT_PIN_LEVEL
)))
462 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
466 /* Enable only interrupts served by the SD controller */
467 sdhci_writel(host
, SDHCI_INT_DATA_MASK
| SDHCI_INT_CMD_MASK
,
469 /* Mask all sdhci interrupt sources */
470 sdhci_writel(host
, 0x0, SDHCI_SIGNAL_ENABLE
);
476 static const struct mmc_ops sdhci_ops
= {
477 .send_cmd
= sdhci_send_command
,
478 .set_ios
= sdhci_set_ios
,
482 int add_sdhci(struct sdhci_host
*host
, u32 max_clk
, u32 min_clk
)
486 host
->cfg
.name
= host
->name
;
487 host
->cfg
.ops
= &sdhci_ops
;
489 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
490 #ifdef CONFIG_MMC_SDMA
491 if (!(caps
& SDHCI_CAN_DO_SDMA
)) {
492 printf("%s: Your controller doesn't support SDMA!!\n",
499 host
->cfg
.f_max
= max_clk
;
501 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
502 host
->cfg
.f_max
= (caps
& SDHCI_CLOCK_V3_BASE_MASK
)
503 >> SDHCI_CLOCK_BASE_SHIFT
;
505 host
->cfg
.f_max
= (caps
& SDHCI_CLOCK_BASE_MASK
)
506 >> SDHCI_CLOCK_BASE_SHIFT
;
507 host
->cfg
.f_max
*= 1000000;
509 if (host
->cfg
.f_max
== 0) {
510 printf("%s: Hardware doesn't specify base clock frequency\n",
515 host
->cfg
.f_min
= min_clk
;
517 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
518 host
->cfg
.f_min
= host
->cfg
.f_max
/
519 SDHCI_MAX_DIV_SPEC_300
;
521 host
->cfg
.f_min
= host
->cfg
.f_max
/
522 SDHCI_MAX_DIV_SPEC_200
;
525 host
->cfg
.voltages
= 0;
526 if (caps
& SDHCI_CAN_VDD_330
)
527 host
->cfg
.voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
528 if (caps
& SDHCI_CAN_VDD_300
)
529 host
->cfg
.voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
530 if (caps
& SDHCI_CAN_VDD_180
)
531 host
->cfg
.voltages
|= MMC_VDD_165_195
;
533 if (host
->quirks
& SDHCI_QUIRK_BROKEN_VOLTAGE
)
534 host
->cfg
.voltages
|= host
->voltages
;
536 host
->cfg
.host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
;
537 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
538 if (caps
& SDHCI_CAN_DO_8BIT
)
539 host
->cfg
.host_caps
|= MMC_MODE_8BIT
;
542 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
543 host
->cfg
.host_caps
&= ~(MMC_MODE_HS
| MMC_MODE_HS_52MHz
);
546 host
->cfg
.host_caps
|= host
->host_caps
;
548 host
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
550 sdhci_reset(host
, SDHCI_RESET_ALL
);
552 host
->mmc
= mmc_create(&host
->cfg
, host
);
553 if (host
->mmc
== NULL
) {
554 printf("%s: mmc create fail!\n", __func__
);