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[people/ms/u-boot.git] / drivers / mmc / sdhci.c
1 /*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10
11 #include <common.h>
12 #include <malloc.h>
13 #include <mmc.h>
14 #include <sdhci.h>
15
16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
18 #else
19 void *aligned_buffer;
20 #endif
21
22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
23 {
24 unsigned long timeout;
25
26 /* Wait max 100 ms */
27 timeout = 100;
28 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
29 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
30 if (timeout == 0) {
31 printf("%s: Reset 0x%x never completed.\n",
32 __func__, (int)mask);
33 return;
34 }
35 timeout--;
36 udelay(1000);
37 }
38 }
39
40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
41 {
42 int i;
43 if (cmd->resp_type & MMC_RSP_136) {
44 /* CRC is stripped so we need to do some shifting. */
45 for (i = 0; i < 4; i++) {
46 cmd->response[i] = sdhci_readl(host,
47 SDHCI_RESPONSE + (3-i)*4) << 8;
48 if (i != 3)
49 cmd->response[i] |= sdhci_readb(host,
50 SDHCI_RESPONSE + (3-i)*4-1);
51 }
52 } else {
53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
54 }
55 }
56
57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
58 {
59 int i;
60 char *offs;
61 for (i = 0; i < data->blocksize; i += 4) {
62 offs = data->dest + i;
63 if (data->flags == MMC_DATA_READ)
64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
65 else
66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
67 }
68 }
69
70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
71 unsigned int start_addr)
72 {
73 unsigned int stat, rdy, mask, timeout, block = 0;
74 #ifdef CONFIG_MMC_SDMA
75 unsigned char ctrl;
76 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
77 ctrl &= ~SDHCI_CTRL_DMA_MASK;
78 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
79 #endif
80
81 timeout = 1000000;
82 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
83 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
84 do {
85 stat = sdhci_readl(host, SDHCI_INT_STATUS);
86 if (stat & SDHCI_INT_ERROR) {
87 printf("%s: Error detected in status(0x%X)!\n",
88 __func__, stat);
89 return -1;
90 }
91 if (stat & rdy) {
92 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
93 continue;
94 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
95 sdhci_transfer_pio(host, data);
96 data->dest += data->blocksize;
97 if (++block >= data->blocks)
98 break;
99 }
100 #ifdef CONFIG_MMC_SDMA
101 if (stat & SDHCI_INT_DMA_END) {
102 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
103 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
104 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
105 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
106 }
107 #endif
108 if (timeout-- > 0)
109 udelay(10);
110 else {
111 printf("%s: Transfer data timeout\n", __func__);
112 return -1;
113 }
114 } while (!(stat & SDHCI_INT_DATA_END));
115 return 0;
116 }
117
118 /*
119 * No command will be sent by driver if card is busy, so driver must wait
120 * for card ready state.
121 * Every time when card is busy after timeout then (last) timeout value will be
122 * increased twice but only if it doesn't exceed global defined maximum.
123 * Each function call will use last timeout value. Max timeout can be redefined
124 * in board config file.
125 */
126 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
127 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
128 #endif
129 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
130 #define SDHCI_READ_STATUS_TIMEOUT 1000
131
132 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
133 struct mmc_data *data)
134 {
135 struct sdhci_host *host = mmc->priv;
136 unsigned int stat = 0;
137 int ret = 0;
138 int trans_bytes = 0, is_aligned = 1;
139 u32 mask, flags, mode;
140 unsigned int time = 0, start_addr = 0;
141 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
142 unsigned start = get_timer(0);
143
144 /* Timeout unit - ms */
145 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
146
147 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
148 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
149
150 /* We shouldn't wait for data inihibit for stop commands, even
151 though they might use busy signaling */
152 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
153 mask &= ~SDHCI_DATA_INHIBIT;
154
155 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
156 if (time >= cmd_timeout) {
157 printf("%s: MMC: %d busy ", __func__, mmc_dev);
158 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
159 cmd_timeout += cmd_timeout;
160 printf("timeout increasing to: %u ms.\n",
161 cmd_timeout);
162 } else {
163 puts("timeout.\n");
164 return COMM_ERR;
165 }
166 }
167 time++;
168 udelay(1000);
169 }
170
171 mask = SDHCI_INT_RESPONSE;
172 if (!(cmd->resp_type & MMC_RSP_PRESENT))
173 flags = SDHCI_CMD_RESP_NONE;
174 else if (cmd->resp_type & MMC_RSP_136)
175 flags = SDHCI_CMD_RESP_LONG;
176 else if (cmd->resp_type & MMC_RSP_BUSY) {
177 flags = SDHCI_CMD_RESP_SHORT_BUSY;
178 mask |= SDHCI_INT_DATA_END;
179 } else
180 flags = SDHCI_CMD_RESP_SHORT;
181
182 if (cmd->resp_type & MMC_RSP_CRC)
183 flags |= SDHCI_CMD_CRC;
184 if (cmd->resp_type & MMC_RSP_OPCODE)
185 flags |= SDHCI_CMD_INDEX;
186 if (data)
187 flags |= SDHCI_CMD_DATA;
188
189 /* Set Transfer mode regarding to data flag */
190 if (data != 0) {
191 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
192 mode = SDHCI_TRNS_BLK_CNT_EN;
193 trans_bytes = data->blocks * data->blocksize;
194 if (data->blocks > 1)
195 mode |= SDHCI_TRNS_MULTI;
196
197 if (data->flags == MMC_DATA_READ)
198 mode |= SDHCI_TRNS_READ;
199
200 #ifdef CONFIG_MMC_SDMA
201 if (data->flags == MMC_DATA_READ)
202 start_addr = (unsigned long)data->dest;
203 else
204 start_addr = (unsigned long)data->src;
205 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
206 (start_addr & 0x7) != 0x0) {
207 is_aligned = 0;
208 start_addr = (unsigned long)aligned_buffer;
209 if (data->flags != MMC_DATA_READ)
210 memcpy(aligned_buffer, data->src, trans_bytes);
211 }
212
213 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
214 /*
215 * Always use this bounce-buffer when
216 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
217 */
218 is_aligned = 0;
219 start_addr = (unsigned long)aligned_buffer;
220 if (data->flags != MMC_DATA_READ)
221 memcpy(aligned_buffer, data->src, trans_bytes);
222 #endif
223
224 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
225 mode |= SDHCI_TRNS_DMA;
226 #endif
227 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
228 data->blocksize),
229 SDHCI_BLOCK_SIZE);
230 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
231 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
232 } else if (cmd->resp_type & MMC_RSP_BUSY) {
233 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
234 }
235
236 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
237 #ifdef CONFIG_MMC_SDMA
238 flush_cache(start_addr, trans_bytes);
239 #endif
240 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
241 start = get_timer(0);
242 do {
243 stat = sdhci_readl(host, SDHCI_INT_STATUS);
244 if (stat & SDHCI_INT_ERROR)
245 break;
246 } while (((stat & mask) != mask) &&
247 (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));
248
249 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
250 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
251 return 0;
252 else {
253 printf("%s: Timeout for status update!\n", __func__);
254 return TIMEOUT;
255 }
256 }
257
258 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
259 sdhci_cmd_done(host, cmd);
260 sdhci_writel(host, mask, SDHCI_INT_STATUS);
261 } else
262 ret = -1;
263
264 if (!ret && data)
265 ret = sdhci_transfer_data(host, data, start_addr);
266
267 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
268 udelay(1000);
269
270 stat = sdhci_readl(host, SDHCI_INT_STATUS);
271 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
272 if (!ret) {
273 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
274 !is_aligned && (data->flags == MMC_DATA_READ))
275 memcpy(data->dest, aligned_buffer, trans_bytes);
276 return 0;
277 }
278
279 sdhci_reset(host, SDHCI_RESET_CMD);
280 sdhci_reset(host, SDHCI_RESET_DATA);
281 if (stat & SDHCI_INT_TIMEOUT)
282 return TIMEOUT;
283 else
284 return COMM_ERR;
285 }
286
287 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
288 {
289 struct sdhci_host *host = mmc->priv;
290 unsigned int div, clk, timeout, reg;
291
292 /* Wait max 20 ms */
293 timeout = 200;
294 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
295 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
296 if (timeout == 0) {
297 printf("%s: Timeout to wait cmd & data inhibit\n",
298 __func__);
299 return -1;
300 }
301
302 timeout--;
303 udelay(100);
304 }
305
306 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
307 reg &= ~SDHCI_CLOCK_CARD_EN;
308 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
309
310 if (clock == 0)
311 return 0;
312
313 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
314 /* Version 3.00 divisors must be a multiple of 2. */
315 if (mmc->cfg->f_max <= clock)
316 div = 1;
317 else {
318 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
319 if ((mmc->cfg->f_max / div) <= clock)
320 break;
321 }
322 }
323 } else {
324 /* Version 2.00 divisors must be a power of 2. */
325 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
326 if ((mmc->cfg->f_max / div) <= clock)
327 break;
328 }
329 }
330 div >>= 1;
331
332 if (host->set_clock)
333 host->set_clock(host->index, div);
334
335 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
336 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
337 << SDHCI_DIVIDER_HI_SHIFT;
338 clk |= SDHCI_CLOCK_INT_EN;
339 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
340
341 /* Wait max 20 ms */
342 timeout = 20;
343 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
344 & SDHCI_CLOCK_INT_STABLE)) {
345 if (timeout == 0) {
346 printf("%s: Internal clock never stabilised.\n",
347 __func__);
348 return -1;
349 }
350 timeout--;
351 udelay(1000);
352 }
353
354 clk |= SDHCI_CLOCK_CARD_EN;
355 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
356 return 0;
357 }
358
359 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
360 {
361 u8 pwr = 0;
362
363 if (power != (unsigned short)-1) {
364 switch (1 << power) {
365 case MMC_VDD_165_195:
366 pwr = SDHCI_POWER_180;
367 break;
368 case MMC_VDD_29_30:
369 case MMC_VDD_30_31:
370 pwr = SDHCI_POWER_300;
371 break;
372 case MMC_VDD_32_33:
373 case MMC_VDD_33_34:
374 pwr = SDHCI_POWER_330;
375 break;
376 }
377 }
378
379 if (pwr == 0) {
380 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
381 return;
382 }
383
384 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
385 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
386
387 pwr |= SDHCI_POWER_ON;
388
389 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
390 }
391
392 static void sdhci_set_ios(struct mmc *mmc)
393 {
394 u32 ctrl;
395 struct sdhci_host *host = mmc->priv;
396
397 if (host->set_control_reg)
398 host->set_control_reg(host);
399
400 if (mmc->clock != host->clock)
401 sdhci_set_clock(mmc, mmc->clock);
402
403 /* Set bus width */
404 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
405 if (mmc->bus_width == 8) {
406 ctrl &= ~SDHCI_CTRL_4BITBUS;
407 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
408 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
409 ctrl |= SDHCI_CTRL_8BITBUS;
410 } else {
411 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
412 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
413 ctrl &= ~SDHCI_CTRL_8BITBUS;
414 if (mmc->bus_width == 4)
415 ctrl |= SDHCI_CTRL_4BITBUS;
416 else
417 ctrl &= ~SDHCI_CTRL_4BITBUS;
418 }
419
420 if (mmc->clock > 26000000)
421 ctrl |= SDHCI_CTRL_HISPD;
422 else
423 ctrl &= ~SDHCI_CTRL_HISPD;
424
425 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
426 ctrl &= ~SDHCI_CTRL_HISPD;
427
428 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
429 }
430
431 static int sdhci_init(struct mmc *mmc)
432 {
433 struct sdhci_host *host = mmc->priv;
434
435 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
436 aligned_buffer = memalign(8, 512*1024);
437 if (!aligned_buffer) {
438 printf("%s: Aligned buffer alloc failed!!!\n",
439 __func__);
440 return -1;
441 }
442 }
443
444 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
445
446 if (host->quirks & SDHCI_QUIRK_NO_CD) {
447 #if defined(CONFIG_PIC32_SDHCI)
448 /* PIC32 SDHCI CD errata:
449 * - set CD_TEST and clear CD_TEST_INS bit
450 */
451 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
452 #else
453 unsigned int status;
454
455 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
456 SDHCI_HOST_CONTROL);
457
458 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
459 while ((!(status & SDHCI_CARD_PRESENT)) ||
460 (!(status & SDHCI_CARD_STATE_STABLE)) ||
461 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
462 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
463 #endif
464 }
465
466 /* Enable only interrupts served by the SD controller */
467 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
468 SDHCI_INT_ENABLE);
469 /* Mask all sdhci interrupt sources */
470 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
471
472 return 0;
473 }
474
475
476 static const struct mmc_ops sdhci_ops = {
477 .send_cmd = sdhci_send_command,
478 .set_ios = sdhci_set_ios,
479 .init = sdhci_init,
480 };
481
482 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
483 {
484 unsigned int caps;
485
486 host->cfg.name = host->name;
487 host->cfg.ops = &sdhci_ops;
488
489 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
490 #ifdef CONFIG_MMC_SDMA
491 if (!(caps & SDHCI_CAN_DO_SDMA)) {
492 printf("%s: Your controller doesn't support SDMA!!\n",
493 __func__);
494 return -1;
495 }
496 #endif
497
498 if (max_clk)
499 host->cfg.f_max = max_clk;
500 else {
501 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
502 host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
503 >> SDHCI_CLOCK_BASE_SHIFT;
504 else
505 host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
506 >> SDHCI_CLOCK_BASE_SHIFT;
507 host->cfg.f_max *= 1000000;
508 }
509 if (host->cfg.f_max == 0) {
510 printf("%s: Hardware doesn't specify base clock frequency\n",
511 __func__);
512 return -1;
513 }
514 if (min_clk)
515 host->cfg.f_min = min_clk;
516 else {
517 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
518 host->cfg.f_min = host->cfg.f_max /
519 SDHCI_MAX_DIV_SPEC_300;
520 else
521 host->cfg.f_min = host->cfg.f_max /
522 SDHCI_MAX_DIV_SPEC_200;
523 }
524
525 host->cfg.voltages = 0;
526 if (caps & SDHCI_CAN_VDD_330)
527 host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
528 if (caps & SDHCI_CAN_VDD_300)
529 host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
530 if (caps & SDHCI_CAN_VDD_180)
531 host->cfg.voltages |= MMC_VDD_165_195;
532
533 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
534 host->cfg.voltages |= host->voltages;
535
536 host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
537 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
538 if (caps & SDHCI_CAN_DO_8BIT)
539 host->cfg.host_caps |= MMC_MODE_8BIT;
540 }
541
542 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
543 host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
544
545 if (host->host_caps)
546 host->cfg.host_caps |= host->host_caps;
547
548 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
549
550 sdhci_reset(host, SDHCI_RESET_ALL);
551
552 host->mmc = mmc_create(&host->cfg, host);
553 if (host->mmc == NULL) {
554 printf("%s: mmc create fail!\n", __func__);
555 return -1;
556 }
557
558 return 0;
559 }