2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
34 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
36 unsigned long timeout
;
40 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
41 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
43 printf("Reset 0x%x never completed.\n", (int)mask
);
51 static void sdhci_cmd_done(struct sdhci_host
*host
, struct mmc_cmd
*cmd
)
54 if (cmd
->resp_type
& MMC_RSP_136
) {
55 /* CRC is stripped so we need to do some shifting. */
56 for (i
= 0; i
< 4; i
++) {
57 cmd
->response
[i
] = sdhci_readl(host
,
58 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
60 cmd
->response
[i
] |= sdhci_readb(host
,
61 SDHCI_RESPONSE
+ (3-i
)*4-1);
64 cmd
->response
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
68 static void sdhci_transfer_pio(struct sdhci_host
*host
, struct mmc_data
*data
)
72 for (i
= 0; i
< data
->blocksize
; i
+= 4) {
73 offs
= data
->dest
+ i
;
74 if (data
->flags
== MMC_DATA_READ
)
75 *(u32
*)offs
= sdhci_readl(host
, SDHCI_BUFFER
);
77 sdhci_writel(host
, *(u32
*)offs
, SDHCI_BUFFER
);
81 static int sdhci_transfer_data(struct sdhci_host
*host
, struct mmc_data
*data
,
82 unsigned int start_addr
)
84 unsigned int stat
, rdy
, mask
, timeout
, block
= 0;
87 rdy
= SDHCI_INT_SPACE_AVAIL
| SDHCI_INT_DATA_AVAIL
;
88 mask
= SDHCI_DATA_AVAILABLE
| SDHCI_SPACE_AVAILABLE
;
90 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
91 if (stat
& SDHCI_INT_ERROR
) {
92 printf("Error detected in status(0x%X)!\n", stat
);
96 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
))
98 sdhci_writel(host
, rdy
, SDHCI_INT_STATUS
);
99 sdhci_transfer_pio(host
, data
);
100 data
->dest
+= data
->blocksize
;
101 if (++block
>= data
->blocks
)
104 #ifdef CONFIG_MMC_SDMA
105 if (stat
& SDHCI_INT_DMA_END
) {
106 sdhci_writel(host
, SDHCI_INT_DMA_END
, SDHCI_INT_STATUS
);
107 start_addr
&= ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1);
108 start_addr
+= SDHCI_DEFAULT_BOUNDARY_SIZE
;
109 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
115 printf("Transfer data timeout\n");
118 } while (!(stat
& SDHCI_INT_DATA_END
));
122 int sdhci_send_command(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
123 struct mmc_data
*data
)
125 struct sdhci_host
*host
= (struct sdhci_host
*)mmc
->priv
;
126 unsigned int stat
= 0;
128 int trans_bytes
= 0, is_aligned
= 1;
129 u32 mask
, flags
, mode
;
130 unsigned int timeout
, start_addr
= 0;
131 unsigned int retry
= 10000;
136 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
137 mask
= SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
;
139 /* We shouldn't wait for data inihibit for stop commands, even
140 though they might use busy signaling */
141 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
142 mask
&= ~SDHCI_DATA_INHIBIT
;
144 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
146 printf("Controller never released inhibit bit(s).\n");
153 mask
= SDHCI_INT_RESPONSE
;
154 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
155 flags
= SDHCI_CMD_RESP_NONE
;
156 else if (cmd
->resp_type
& MMC_RSP_136
)
157 flags
= SDHCI_CMD_RESP_LONG
;
158 else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
159 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
160 mask
|= SDHCI_INT_DATA_END
;
162 flags
= SDHCI_CMD_RESP_SHORT
;
164 if (cmd
->resp_type
& MMC_RSP_CRC
)
165 flags
|= SDHCI_CMD_CRC
;
166 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
167 flags
|= SDHCI_CMD_INDEX
;
169 flags
|= SDHCI_CMD_DATA
;
171 /*Set Transfer mode regarding to data flag*/
173 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
174 mode
= SDHCI_TRNS_BLK_CNT_EN
;
175 trans_bytes
= data
->blocks
* data
->blocksize
;
176 if (data
->blocks
> 1)
177 mode
|= SDHCI_TRNS_MULTI
;
179 if (data
->flags
== MMC_DATA_READ
)
180 mode
|= SDHCI_TRNS_READ
;
182 #ifdef CONFIG_MMC_SDMA
183 if (data
->flags
== MMC_DATA_READ
)
184 start_addr
= (unsigned int)data
->dest
;
186 start_addr
= (unsigned int)data
->src
;
187 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
188 (start_addr
& 0x7) != 0x0) {
190 start_addr
= (unsigned int)aligned_buffer
;
191 if (data
->flags
!= MMC_DATA_READ
)
192 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
195 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
196 mode
|= SDHCI_TRNS_DMA
;
198 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
201 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
202 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
205 sdhci_writel(host
, cmd
->cmdarg
, SDHCI_ARGUMENT
);
206 #ifdef CONFIG_MMC_SDMA
207 flush_cache(start_addr
, trans_bytes
);
209 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->cmdidx
, flags
), SDHCI_COMMAND
);
211 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
212 if (stat
& SDHCI_INT_ERROR
)
216 } while ((stat
& mask
) != mask
);
219 if (host
->quirks
& SDHCI_QUIRK_BROKEN_R1B
)
222 printf("Timeout for status update!\n");
227 if ((stat
& (SDHCI_INT_ERROR
| mask
)) == mask
) {
228 sdhci_cmd_done(host
, cmd
);
229 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
234 ret
= sdhci_transfer_data(host
, data
, start_addr
);
236 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
237 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
239 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
240 !is_aligned
&& (data
->flags
== MMC_DATA_READ
))
241 memcpy(data
->dest
, aligned_buffer
, trans_bytes
);
245 sdhci_reset(host
, SDHCI_RESET_CMD
);
246 sdhci_reset(host
, SDHCI_RESET_DATA
);
247 if (stat
& SDHCI_INT_TIMEOUT
)
253 static int sdhci_set_clock(struct mmc
*mmc
, unsigned int clock
)
255 struct sdhci_host
*host
= (struct sdhci_host
*)mmc
->priv
;
256 unsigned int div
, clk
, timeout
;
258 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
263 if ((host
->version
& SDHCI_SPEC_VER_MASK
) >= SDHCI_SPEC_300
) {
264 /* Version 3.00 divisors must be a multiple of 2. */
265 if (mmc
->f_max
<= clock
)
268 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
; div
+= 2) {
269 if ((mmc
->f_max
/ div
) <= clock
)
274 /* Version 2.00 divisors must be a power of 2. */
275 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
276 if ((mmc
->f_max
/ div
) <= clock
)
283 host
->set_clock(host
->index
, div
);
285 clk
= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
286 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
287 << SDHCI_DIVIDER_HI_SHIFT
;
288 clk
|= SDHCI_CLOCK_INT_EN
;
289 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
293 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
294 & SDHCI_CLOCK_INT_STABLE
)) {
296 printf("Internal clock never stabilised.\n");
303 clk
|= SDHCI_CLOCK_CARD_EN
;
304 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
308 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
312 if (power
!= (unsigned short)-1) {
313 switch (1 << power
) {
314 case MMC_VDD_165_195
:
315 pwr
= SDHCI_POWER_180
;
319 pwr
= SDHCI_POWER_300
;
323 pwr
= SDHCI_POWER_330
;
329 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
333 pwr
|= SDHCI_POWER_ON
;
335 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
338 void sdhci_set_ios(struct mmc
*mmc
)
341 struct sdhci_host
*host
= (struct sdhci_host
*)mmc
->priv
;
343 if (host
->set_control_reg
)
344 host
->set_control_reg(host
);
346 if (mmc
->clock
!= host
->clock
)
347 sdhci_set_clock(mmc
, mmc
->clock
);
350 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
351 if (mmc
->bus_width
== 8) {
352 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
353 if ((host
->version
& SDHCI_SPEC_VER_MASK
) >= SDHCI_SPEC_300
)
354 ctrl
|= SDHCI_CTRL_8BITBUS
;
356 if ((host
->version
& SDHCI_SPEC_VER_MASK
) >= SDHCI_SPEC_300
)
357 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
358 if (mmc
->bus_width
== 4)
359 ctrl
|= SDHCI_CTRL_4BITBUS
;
361 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
364 if (mmc
->clock
> 26000000)
365 ctrl
|= SDHCI_CTRL_HISPD
;
367 ctrl
&= ~SDHCI_CTRL_HISPD
;
369 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
370 ctrl
&= ~SDHCI_CTRL_HISPD
;
372 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
375 int sdhci_init(struct mmc
*mmc
)
377 struct sdhci_host
*host
= (struct sdhci_host
*)mmc
->priv
;
379 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) && !aligned_buffer
) {
380 aligned_buffer
= memalign(8, 512*1024);
381 if (!aligned_buffer
) {
382 printf("Aligned buffer alloc failed!!!");
387 sdhci_set_power(host
, fls(mmc
->voltages
) - 1);
389 if (host
->quirks
& SDHCI_QUIRK_NO_CD
) {
392 sdhci_writel(host
, SDHCI_CTRL_CD_TEST_INS
| SDHCI_CTRL_CD_TEST
,
395 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
396 while ((!(status
& SDHCI_CARD_PRESENT
)) ||
397 (!(status
& SDHCI_CARD_STATE_STABLE
)) ||
398 (!(status
& SDHCI_CARD_DETECT_PIN_LEVEL
)))
399 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
402 /* Eable all state */
403 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_ENABLE
);
404 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_SIGNAL_ENABLE
);
409 int add_sdhci(struct sdhci_host
*host
, u32 max_clk
, u32 min_clk
)
414 mmc
= malloc(sizeof(struct mmc
));
416 printf("mmc malloc fail!\n");
423 sprintf(mmc
->name
, "%s", host
->name
);
424 mmc
->send_cmd
= sdhci_send_command
;
425 mmc
->set_ios
= sdhci_set_ios
;
426 mmc
->init
= sdhci_init
;
429 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
430 #ifdef CONFIG_MMC_SDMA
431 if (!(caps
& SDHCI_CAN_DO_SDMA
)) {
432 printf("Your controller don't support sdma!!\n");
438 mmc
->f_max
= max_clk
;
440 if ((host
->version
& SDHCI_SPEC_VER_MASK
) >= SDHCI_SPEC_300
)
441 mmc
->f_max
= (caps
& SDHCI_CLOCK_V3_BASE_MASK
)
442 >> SDHCI_CLOCK_BASE_SHIFT
;
444 mmc
->f_max
= (caps
& SDHCI_CLOCK_BASE_MASK
)
445 >> SDHCI_CLOCK_BASE_SHIFT
;
446 mmc
->f_max
*= 1000000;
448 if (mmc
->f_max
== 0) {
449 printf("Hardware doesn't specify base clock frequency\n");
453 mmc
->f_min
= min_clk
;
455 if ((host
->version
& SDHCI_SPEC_VER_MASK
) >= SDHCI_SPEC_300
)
456 mmc
->f_min
= mmc
->f_max
/ SDHCI_MAX_DIV_SPEC_300
;
458 mmc
->f_min
= mmc
->f_max
/ SDHCI_MAX_DIV_SPEC_200
;
462 if (caps
& SDHCI_CAN_VDD_330
)
463 mmc
->voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
464 if (caps
& SDHCI_CAN_VDD_300
)
465 mmc
->voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
466 if (caps
& SDHCI_CAN_VDD_180
)
467 mmc
->voltages
|= MMC_VDD_165_195
;
469 if (host
->quirks
& SDHCI_QUIRK_BROKEN_VOLTAGE
)
470 mmc
->voltages
|= host
->voltages
;
472 mmc
->host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
;
473 if (caps
& SDHCI_CAN_DO_8BIT
)
474 mmc
->host_caps
|= MMC_MODE_8BIT
;
476 mmc
->host_caps
|= host
->host_caps
;
478 sdhci_reset(host
, SDHCI_RESET_ALL
);