2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 void *aligned_buffer
= (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
;
23 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
25 unsigned long timeout
;
29 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
30 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
32 printf("%s: Reset 0x%x never completed.\n",
41 static void sdhci_cmd_done(struct sdhci_host
*host
, struct mmc_cmd
*cmd
)
44 if (cmd
->resp_type
& MMC_RSP_136
) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i
= 0; i
< 4; i
++) {
47 cmd
->response
[i
] = sdhci_readl(host
,
48 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
50 cmd
->response
[i
] |= sdhci_readb(host
,
51 SDHCI_RESPONSE
+ (3-i
)*4-1);
54 cmd
->response
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
58 static void sdhci_transfer_pio(struct sdhci_host
*host
, struct mmc_data
*data
)
62 for (i
= 0; i
< data
->blocksize
; i
+= 4) {
63 offs
= data
->dest
+ i
;
64 if (data
->flags
== MMC_DATA_READ
)
65 *(u32
*)offs
= sdhci_readl(host
, SDHCI_BUFFER
);
67 sdhci_writel(host
, *(u32
*)offs
, SDHCI_BUFFER
);
71 static int sdhci_transfer_data(struct sdhci_host
*host
, struct mmc_data
*data
,
72 unsigned int start_addr
)
74 unsigned int stat
, rdy
, mask
, timeout
, block
= 0;
75 #ifdef CONFIG_MMC_SDMA
77 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
78 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
79 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
83 rdy
= SDHCI_INT_SPACE_AVAIL
| SDHCI_INT_DATA_AVAIL
;
84 mask
= SDHCI_DATA_AVAILABLE
| SDHCI_SPACE_AVAILABLE
;
86 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
87 if (stat
& SDHCI_INT_ERROR
) {
88 printf("%s: Error detected in status(0x%X)!\n",
93 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
))
95 sdhci_writel(host
, rdy
, SDHCI_INT_STATUS
);
96 sdhci_transfer_pio(host
, data
);
97 data
->dest
+= data
->blocksize
;
98 if (++block
>= data
->blocks
)
101 #ifdef CONFIG_MMC_SDMA
102 if (stat
& SDHCI_INT_DMA_END
) {
103 sdhci_writel(host
, SDHCI_INT_DMA_END
, SDHCI_INT_STATUS
);
104 start_addr
&= ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1);
105 start_addr
+= SDHCI_DEFAULT_BOUNDARY_SIZE
;
106 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
112 printf("%s: Transfer data timeout\n", __func__
);
115 } while (!(stat
& SDHCI_INT_DATA_END
));
120 * No command will be sent by driver if card is busy, so driver must wait
121 * for card ready state.
122 * Every time when card is busy after timeout then (last) timeout value will be
123 * increased twice but only if it doesn't exceed global defined maximum.
124 * Each function call will use last timeout value.
126 #define SDHCI_CMD_MAX_TIMEOUT 3200
127 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
128 #define SDHCI_READ_STATUS_TIMEOUT 1000
130 #ifdef CONFIG_DM_MMC_OPS
131 static int sdhci_send_command(struct udevice
*dev
, struct mmc_cmd
*cmd
,
132 struct mmc_data
*data
)
134 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
137 static int sdhci_send_command(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
138 struct mmc_data
*data
)
141 struct sdhci_host
*host
= mmc
->priv
;
142 unsigned int stat
= 0;
144 int trans_bytes
= 0, is_aligned
= 1;
145 u32 mask
, flags
, mode
;
146 unsigned int time
= 0, start_addr
= 0;
147 int mmc_dev
= mmc_get_blk_desc(mmc
)->devnum
;
148 unsigned start
= get_timer(0);
150 /* Timeout unit - ms */
151 static unsigned int cmd_timeout
= SDHCI_CMD_DEFAULT_TIMEOUT
;
153 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
154 mask
= SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
;
156 /* We shouldn't wait for data inihibit for stop commands, even
157 though they might use busy signaling */
158 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
159 mask
&= ~SDHCI_DATA_INHIBIT
;
161 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
162 if (time
>= cmd_timeout
) {
163 printf("%s: MMC: %d busy ", __func__
, mmc_dev
);
164 if (2 * cmd_timeout
<= SDHCI_CMD_MAX_TIMEOUT
) {
165 cmd_timeout
+= cmd_timeout
;
166 printf("timeout increasing to: %u ms.\n",
177 mask
= SDHCI_INT_RESPONSE
;
178 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
179 flags
= SDHCI_CMD_RESP_NONE
;
180 else if (cmd
->resp_type
& MMC_RSP_136
)
181 flags
= SDHCI_CMD_RESP_LONG
;
182 else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
183 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
185 mask
|= SDHCI_INT_DATA_END
;
187 flags
= SDHCI_CMD_RESP_SHORT
;
189 if (cmd
->resp_type
& MMC_RSP_CRC
)
190 flags
|= SDHCI_CMD_CRC
;
191 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
192 flags
|= SDHCI_CMD_INDEX
;
194 flags
|= SDHCI_CMD_DATA
;
196 /* Set Transfer mode regarding to data flag */
198 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
199 mode
= SDHCI_TRNS_BLK_CNT_EN
;
200 trans_bytes
= data
->blocks
* data
->blocksize
;
201 if (data
->blocks
> 1)
202 mode
|= SDHCI_TRNS_MULTI
;
204 if (data
->flags
== MMC_DATA_READ
)
205 mode
|= SDHCI_TRNS_READ
;
207 #ifdef CONFIG_MMC_SDMA
208 if (data
->flags
== MMC_DATA_READ
)
209 start_addr
= (unsigned long)data
->dest
;
211 start_addr
= (unsigned long)data
->src
;
212 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
213 (start_addr
& 0x7) != 0x0) {
215 start_addr
= (unsigned long)aligned_buffer
;
216 if (data
->flags
!= MMC_DATA_READ
)
217 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
220 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
222 * Always use this bounce-buffer when
223 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
226 start_addr
= (unsigned long)aligned_buffer
;
227 if (data
->flags
!= MMC_DATA_READ
)
228 memcpy(aligned_buffer
, data
->src
, trans_bytes
);
231 sdhci_writel(host
, start_addr
, SDHCI_DMA_ADDRESS
);
232 mode
|= SDHCI_TRNS_DMA
;
234 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
237 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
238 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
239 } else if (cmd
->resp_type
& MMC_RSP_BUSY
) {
240 sdhci_writeb(host
, 0xe, SDHCI_TIMEOUT_CONTROL
);
243 sdhci_writel(host
, cmd
->cmdarg
, SDHCI_ARGUMENT
);
244 #ifdef CONFIG_MMC_SDMA
245 flush_cache(start_addr
, trans_bytes
);
247 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->cmdidx
, flags
), SDHCI_COMMAND
);
248 start
= get_timer(0);
250 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
251 if (stat
& SDHCI_INT_ERROR
)
254 if (get_timer(start
) >= SDHCI_READ_STATUS_TIMEOUT
) {
255 if (host
->quirks
& SDHCI_QUIRK_BROKEN_R1B
) {
258 printf("%s: Timeout for status update!\n",
263 } while ((stat
& mask
) != mask
);
265 if ((stat
& (SDHCI_INT_ERROR
| mask
)) == mask
) {
266 sdhci_cmd_done(host
, cmd
);
267 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
272 ret
= sdhci_transfer_data(host
, data
, start_addr
);
274 if (host
->quirks
& SDHCI_QUIRK_WAIT_SEND_CMD
)
277 stat
= sdhci_readl(host
, SDHCI_INT_STATUS
);
278 sdhci_writel(host
, SDHCI_INT_ALL_MASK
, SDHCI_INT_STATUS
);
280 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) &&
281 !is_aligned
&& (data
->flags
== MMC_DATA_READ
))
282 memcpy(data
->dest
, aligned_buffer
, trans_bytes
);
286 sdhci_reset(host
, SDHCI_RESET_CMD
);
287 sdhci_reset(host
, SDHCI_RESET_DATA
);
288 if (stat
& SDHCI_INT_TIMEOUT
)
294 static int sdhci_set_clock(struct mmc
*mmc
, unsigned int clock
)
296 struct sdhci_host
*host
= mmc
->priv
;
297 unsigned int div
, clk
= 0, timeout
, reg
;
301 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
302 (SDHCI_CMD_INHIBIT
| SDHCI_DATA_INHIBIT
)) {
304 printf("%s: Timeout to wait cmd & data inhibit\n",
313 reg
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
314 reg
&= ~(SDHCI_CLOCK_CARD_EN
| SDHCI_CLOCK_INT_EN
);
315 sdhci_writew(host
, reg
, SDHCI_CLOCK_CONTROL
);
320 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
322 * Check if the Host Controller supports Programmable Clock
326 for (div
= 1; div
<= 1024; div
++) {
327 if ((mmc
->cfg
->f_max
* host
->clk_mul
/ div
)
333 * Set Programmable Clock Mode in the Clock
336 clk
= SDHCI_PROG_CLOCK_MODE
;
339 /* Version 3.00 divisors must be a multiple of 2. */
340 if (mmc
->cfg
->f_max
<= clock
) {
344 div
< SDHCI_MAX_DIV_SPEC_300
;
346 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
353 /* Version 2.00 divisors must be a power of 2. */
354 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
355 if ((mmc
->cfg
->f_max
/ div
) <= clock
)
362 host
->set_clock(host
->index
, div
);
364 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
365 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
366 << SDHCI_DIVIDER_HI_SHIFT
;
367 clk
|= SDHCI_CLOCK_INT_EN
;
368 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
372 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
373 & SDHCI_CLOCK_INT_STABLE
)) {
375 printf("%s: Internal clock never stabilised.\n",
383 clk
|= SDHCI_CLOCK_CARD_EN
;
384 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
388 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
392 if (power
!= (unsigned short)-1) {
393 switch (1 << power
) {
394 case MMC_VDD_165_195
:
395 pwr
= SDHCI_POWER_180
;
399 pwr
= SDHCI_POWER_300
;
403 pwr
= SDHCI_POWER_330
;
409 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
413 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
414 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
416 pwr
|= SDHCI_POWER_ON
;
418 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
421 #ifdef CONFIG_DM_MMC_OPS
422 static int sdhci_set_ios(struct udevice
*dev
)
424 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
426 static void sdhci_set_ios(struct mmc
*mmc
)
430 struct sdhci_host
*host
= mmc
->priv
;
432 if (host
->set_control_reg
)
433 host
->set_control_reg(host
);
435 if (mmc
->clock
!= host
->clock
)
436 sdhci_set_clock(mmc
, mmc
->clock
);
439 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
440 if (mmc
->bus_width
== 8) {
441 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
442 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
443 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
444 ctrl
|= SDHCI_CTRL_8BITBUS
;
446 if ((SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) ||
447 (host
->quirks
& SDHCI_QUIRK_USE_WIDE8
))
448 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
449 if (mmc
->bus_width
== 4)
450 ctrl
|= SDHCI_CTRL_4BITBUS
;
452 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
455 if (mmc
->clock
> 26000000)
456 ctrl
|= SDHCI_CTRL_HISPD
;
458 ctrl
&= ~SDHCI_CTRL_HISPD
;
460 if (host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
)
461 ctrl
&= ~SDHCI_CTRL_HISPD
;
463 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
464 #ifdef CONFIG_DM_MMC_OPS
469 static int sdhci_init(struct mmc
*mmc
)
471 struct sdhci_host
*host
= mmc
->priv
;
473 sdhci_reset(host
, SDHCI_RESET_ALL
);
475 if ((host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
) && !aligned_buffer
) {
476 aligned_buffer
= memalign(8, 512*1024);
477 if (!aligned_buffer
) {
478 printf("%s: Aligned buffer alloc failed!!!\n",
484 sdhci_set_power(host
, fls(mmc
->cfg
->voltages
) - 1);
486 if (host
->quirks
& SDHCI_QUIRK_NO_CD
) {
487 #if defined(CONFIG_PIC32_SDHCI)
488 /* PIC32 SDHCI CD errata:
489 * - set CD_TEST and clear CD_TEST_INS bit
491 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST
, SDHCI_HOST_CONTROL
);
495 sdhci_writeb(host
, SDHCI_CTRL_CD_TEST_INS
| SDHCI_CTRL_CD_TEST
,
498 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
499 while ((!(status
& SDHCI_CARD_PRESENT
)) ||
500 (!(status
& SDHCI_CARD_STATE_STABLE
)) ||
501 (!(status
& SDHCI_CARD_DETECT_PIN_LEVEL
)))
502 status
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
506 /* Enable only interrupts served by the SD controller */
507 sdhci_writel(host
, SDHCI_INT_DATA_MASK
| SDHCI_INT_CMD_MASK
,
509 /* Mask all sdhci interrupt sources */
510 sdhci_writel(host
, 0x0, SDHCI_SIGNAL_ENABLE
);
515 #ifdef CONFIG_DM_MMC_OPS
516 int sdhci_probe(struct udevice
*dev
)
518 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
520 return sdhci_init(mmc
);
523 const struct dm_mmc_ops sdhci_ops
= {
524 .send_cmd
= sdhci_send_command
,
525 .set_ios
= sdhci_set_ios
,
528 static const struct mmc_ops sdhci_ops
= {
529 .send_cmd
= sdhci_send_command
,
530 .set_ios
= sdhci_set_ios
,
535 int sdhci_setup_cfg(struct mmc_config
*cfg
, struct sdhci_host
*host
,
536 u32 max_clk
, u32 min_clk
)
540 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
542 #ifdef CONFIG_MMC_SDMA
543 if (!(caps
& SDHCI_CAN_DO_SDMA
)) {
544 printf("%s: Your controller doesn't support SDMA!!\n",
549 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
551 cfg
->name
= host
->name
;
552 #ifndef CONFIG_DM_MMC_OPS
553 cfg
->ops
= &sdhci_ops
;
556 cfg
->f_max
= max_clk
;
558 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
559 cfg
->f_max
= (caps
& SDHCI_CLOCK_V3_BASE_MASK
) >>
560 SDHCI_CLOCK_BASE_SHIFT
;
562 cfg
->f_max
= (caps
& SDHCI_CLOCK_BASE_MASK
) >>
563 SDHCI_CLOCK_BASE_SHIFT
;
564 cfg
->f_max
*= 1000000;
566 if (cfg
->f_max
== 0) {
567 printf("%s: Hardware doesn't specify base clock frequency\n",
572 cfg
->f_min
= min_clk
;
574 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
)
575 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_300
;
577 cfg
->f_min
= cfg
->f_max
/ SDHCI_MAX_DIV_SPEC_200
;
580 if (caps
& SDHCI_CAN_VDD_330
)
581 cfg
->voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
582 if (caps
& SDHCI_CAN_VDD_300
)
583 cfg
->voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
584 if (caps
& SDHCI_CAN_VDD_180
)
585 cfg
->voltages
|= MMC_VDD_165_195
;
587 if (host
->quirks
& SDHCI_QUIRK_BROKEN_VOLTAGE
)
588 cfg
->voltages
|= host
->voltages
;
590 cfg
->host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
;
591 if (SDHCI_GET_VERSION(host
) >= SDHCI_SPEC_300
) {
592 if (caps
& SDHCI_CAN_DO_8BIT
)
593 cfg
->host_caps
|= MMC_MODE_8BIT
;
597 cfg
->host_caps
|= host
->host_caps
;
600 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
603 * In case of Host Controller v3.00, find out whether clock
604 * multiplier is supported.
606 caps_1
= sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
607 host
->clk_mul
= (caps_1
& SDHCI_CLOCK_MUL_MASK
) >>
608 SDHCI_CLOCK_MUL_SHIFT
;
614 int sdhci_bind(struct udevice
*dev
, struct mmc
*mmc
, struct mmc_config
*cfg
)
616 return mmc_bind(dev
, mmc
, cfg
);
619 int add_sdhci(struct sdhci_host
*host
, u32 max_clk
, u32 min_clk
)
623 ret
= sdhci_setup_cfg(&host
->cfg
, host
, max_clk
, min_clk
);
627 host
->mmc
= mmc_create(&host
->cfg
, host
);
628 if (host
->mmc
== NULL
) {
629 printf("%s: mmc create fail!\n", __func__
);