4 * Copyright (C) 2011 Renesas Solutions Corp.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
17 #include <asm/errno.h>
21 #define DRIVER_NAME "sh_mmcif"
23 static int sh_mmcif_intr(void *dev_id
)
25 struct sh_mmcif_host
*host
= dev_id
;
28 state
= sh_mmcif_read(&host
->regs
->ce_int
);
29 state
&= sh_mmcif_read(&host
->regs
->ce_int_mask
);
31 if (state
& INT_RBSYE
) {
32 sh_mmcif_write(~(INT_RBSYE
| INT_CRSPE
), &host
->regs
->ce_int
);
33 sh_mmcif_bitclr(MASK_MRBSYE
, &host
->regs
->ce_int_mask
);
35 } else if (state
& INT_CRSPE
) {
36 sh_mmcif_write(~INT_CRSPE
, &host
->regs
->ce_int
);
37 sh_mmcif_bitclr(MASK_MCRSPE
, &host
->regs
->ce_int_mask
);
38 /* one more interrupt (INT_RBSYE) */
39 if (sh_mmcif_read(&host
->regs
->ce_cmd_set
) & CMD_SET_RBSY
)
42 } else if (state
& INT_BUFREN
) {
43 sh_mmcif_write(~INT_BUFREN
, &host
->regs
->ce_int
);
44 sh_mmcif_bitclr(MASK_MBUFREN
, &host
->regs
->ce_int_mask
);
46 } else if (state
& INT_BUFWEN
) {
47 sh_mmcif_write(~INT_BUFWEN
, &host
->regs
->ce_int
);
48 sh_mmcif_bitclr(MASK_MBUFWEN
, &host
->regs
->ce_int_mask
);
50 } else if (state
& INT_CMD12DRE
) {
51 sh_mmcif_write(~(INT_CMD12DRE
| INT_CMD12RBE
| INT_CMD12CRE
|
52 INT_BUFRE
), &host
->regs
->ce_int
);
53 sh_mmcif_bitclr(MASK_MCMD12DRE
, &host
->regs
->ce_int_mask
);
55 } else if (state
& INT_BUFRE
) {
56 sh_mmcif_write(~INT_BUFRE
, &host
->regs
->ce_int
);
57 sh_mmcif_bitclr(MASK_MBUFRE
, &host
->regs
->ce_int_mask
);
59 } else if (state
& INT_DTRANE
) {
60 sh_mmcif_write(~INT_DTRANE
, &host
->regs
->ce_int
);
61 sh_mmcif_bitclr(MASK_MDTRANE
, &host
->regs
->ce_int_mask
);
63 } else if (state
& INT_CMD12RBE
) {
64 sh_mmcif_write(~(INT_CMD12RBE
| INT_CMD12CRE
),
66 sh_mmcif_bitclr(MASK_MCMD12RBE
, &host
->regs
->ce_int_mask
);
68 } else if (state
& INT_ERR_STS
) {
70 sh_mmcif_write(~state
, &host
->regs
->ce_int
);
71 sh_mmcif_bitclr(state
, &host
->regs
->ce_int_mask
);
78 debug("%s: int err state = %08x\n", DRIVER_NAME
, state
);
84 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host
*host
)
86 int timeout
= 10000000;
95 if (!sh_mmcif_intr(host
))
98 udelay(1); /* 1 usec */
101 return 1; /* Return value: NOT 0 = complete waiting */
104 static void sh_mmcif_clock_control(struct sh_mmcif_host
*host
, unsigned int clk
)
108 sh_mmcif_bitclr(CLK_ENABLE
, &host
->regs
->ce_clk_ctrl
);
109 sh_mmcif_bitclr(CLK_CLEAR
, &host
->regs
->ce_clk_ctrl
);
113 if (clk
== CLKDEV_EMMC_DATA
) {
114 sh_mmcif_bitset(CLK_PCLK
, &host
->regs
->ce_clk_ctrl
);
116 for (i
= 1; (unsigned int)host
->clk
/ (1 << i
) >= clk
; i
++)
118 sh_mmcif_bitset((i
- 1) << 16, &host
->regs
->ce_clk_ctrl
);
120 sh_mmcif_bitset(CLK_ENABLE
, &host
->regs
->ce_clk_ctrl
);
123 static void sh_mmcif_sync_reset(struct sh_mmcif_host
*host
)
127 tmp
= sh_mmcif_read(&host
->regs
->ce_clk_ctrl
) & (CLK_ENABLE
|
130 sh_mmcif_write(SOFT_RST_ON
, &host
->regs
->ce_version
);
131 sh_mmcif_write(SOFT_RST_OFF
, &host
->regs
->ce_version
);
132 sh_mmcif_bitset(tmp
| SRSPTO_256
| SRBSYTO_29
| SRWDTO_29
| SCCSTO_29
,
133 &host
->regs
->ce_clk_ctrl
);
135 sh_mmcif_bitset(BUF_ACC_ATYP
, &host
->regs
->ce_buf_acc
);
138 static int sh_mmcif_error_manage(struct sh_mmcif_host
*host
)
141 int ret
, timeout
= 10000000;
146 state1
= sh_mmcif_read(&host
->regs
->ce_host_sts1
);
147 state2
= sh_mmcif_read(&host
->regs
->ce_host_sts2
);
148 debug("%s: ERR HOST_STS1 = %08x\n", \
149 DRIVER_NAME
, sh_mmcif_read(&host
->regs
->ce_host_sts1
));
150 debug("%s: ERR HOST_STS2 = %08x\n", \
151 DRIVER_NAME
, sh_mmcif_read(&host
->regs
->ce_host_sts2
));
153 if (state1
& STS1_CMDSEQ
) {
154 debug("%s: Forced end of command sequence\n", DRIVER_NAME
);
155 sh_mmcif_bitset(CMD_CTRL_BREAK
, &host
->regs
->ce_cmd_ctrl
);
156 sh_mmcif_bitset(~CMD_CTRL_BREAK
, &host
->regs
->ce_cmd_ctrl
);
160 printf(DRIVER_NAME
": Forceed end of " \
161 "command sequence timeout err\n");
164 if (!(sh_mmcif_read(&host
->regs
->ce_host_sts1
)
168 sh_mmcif_sync_reset(host
);
172 if (state2
& STS2_CRC_ERR
)
174 else if (state2
& STS2_TIMEOUT_ERR
)
181 static int sh_mmcif_single_read(struct sh_mmcif_host
*host
,
182 struct mmc_data
*data
)
186 unsigned long *p
= (unsigned long *)data
->dest
;
188 if ((unsigned long)p
& 0x00000001) {
189 printf("%s: The data pointer is unaligned.", __func__
);
195 /* buf read enable */
196 sh_mmcif_bitset(MASK_MBUFREN
, &host
->regs
->ce_int_mask
);
197 time
= mmcif_wait_interrupt_flag(host
);
198 if (time
== 0 || host
->sd_error
!= 0)
199 return sh_mmcif_error_manage(host
);
202 blocksize
= (BLOCK_SIZE_MASK
&
203 sh_mmcif_read(&host
->regs
->ce_block_set
)) + 3;
204 for (i
= 0; i
< blocksize
/ 4; i
++)
205 *p
++ = sh_mmcif_read(&host
->regs
->ce_data
);
207 /* buffer read end */
208 sh_mmcif_bitset(MASK_MBUFRE
, &host
->regs
->ce_int_mask
);
209 time
= mmcif_wait_interrupt_flag(host
);
210 if (time
== 0 || host
->sd_error
!= 0)
211 return sh_mmcif_error_manage(host
);
217 static int sh_mmcif_multi_read(struct sh_mmcif_host
*host
,
218 struct mmc_data
*data
)
222 unsigned long *p
= (unsigned long *)data
->dest
;
224 if ((unsigned long)p
& 0x00000001) {
225 printf("%s: The data pointer is unaligned.", __func__
);
230 blocksize
= BLOCK_SIZE_MASK
& sh_mmcif_read(&host
->regs
->ce_block_set
);
231 for (j
= 0; j
< data
->blocks
; j
++) {
232 sh_mmcif_bitset(MASK_MBUFREN
, &host
->regs
->ce_int_mask
);
233 time
= mmcif_wait_interrupt_flag(host
);
234 if (time
== 0 || host
->sd_error
!= 0)
235 return sh_mmcif_error_manage(host
);
238 for (i
= 0; i
< blocksize
/ 4; i
++)
239 *p
++ = sh_mmcif_read(&host
->regs
->ce_data
);
246 static int sh_mmcif_single_write(struct sh_mmcif_host
*host
,
247 struct mmc_data
*data
)
251 const unsigned long *p
= (unsigned long *)data
->dest
;
253 if ((unsigned long)p
& 0x00000001) {
254 printf("%s: The data pointer is unaligned.", __func__
);
259 sh_mmcif_bitset(MASK_MBUFWEN
, &host
->regs
->ce_int_mask
);
261 time
= mmcif_wait_interrupt_flag(host
);
262 if (time
== 0 || host
->sd_error
!= 0)
263 return sh_mmcif_error_manage(host
);
266 blocksize
= (BLOCK_SIZE_MASK
&
267 sh_mmcif_read(&host
->regs
->ce_block_set
)) + 3;
268 for (i
= 0; i
< blocksize
/ 4; i
++)
269 sh_mmcif_write(*p
++, &host
->regs
->ce_data
);
271 /* buffer write end */
272 sh_mmcif_bitset(MASK_MDTRANE
, &host
->regs
->ce_int_mask
);
274 time
= mmcif_wait_interrupt_flag(host
);
275 if (time
== 0 || host
->sd_error
!= 0)
276 return sh_mmcif_error_manage(host
);
282 static int sh_mmcif_multi_write(struct sh_mmcif_host
*host
,
283 struct mmc_data
*data
)
287 const unsigned long *p
= (unsigned long *)data
->dest
;
289 if ((unsigned long)p
& 0x00000001) {
290 printf("%s: The data pointer is unaligned.", __func__
);
295 blocksize
= BLOCK_SIZE_MASK
& sh_mmcif_read(&host
->regs
->ce_block_set
);
296 for (j
= 0; j
< data
->blocks
; j
++) {
297 sh_mmcif_bitset(MASK_MBUFWEN
, &host
->regs
->ce_int_mask
);
299 time
= mmcif_wait_interrupt_flag(host
);
301 if (time
== 0 || host
->sd_error
!= 0)
302 return sh_mmcif_error_manage(host
);
305 for (i
= 0; i
< blocksize
/ 4; i
++)
306 sh_mmcif_write(*p
++, &host
->regs
->ce_data
);
313 static void sh_mmcif_get_response(struct sh_mmcif_host
*host
,
316 if (cmd
->resp_type
& MMC_RSP_136
) {
317 cmd
->response
[0] = sh_mmcif_read(&host
->regs
->ce_resp3
);
318 cmd
->response
[1] = sh_mmcif_read(&host
->regs
->ce_resp2
);
319 cmd
->response
[2] = sh_mmcif_read(&host
->regs
->ce_resp1
);
320 cmd
->response
[3] = sh_mmcif_read(&host
->regs
->ce_resp0
);
321 debug(" RESP %08x, %08x, %08x, %08x\n", cmd
->response
[0],
322 cmd
->response
[1], cmd
->response
[2], cmd
->response
[3]);
324 cmd
->response
[0] = sh_mmcif_read(&host
->regs
->ce_resp0
);
328 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host
*host
,
331 cmd
->response
[0] = sh_mmcif_read(&host
->regs
->ce_resp_cmd12
);
334 static u32
sh_mmcif_set_cmd(struct sh_mmcif_host
*host
,
335 struct mmc_data
*data
, struct mmc_cmd
*cmd
)
338 u32 opc
= cmd
->cmdidx
;
340 /* Response Type check */
341 switch (cmd
->resp_type
) {
343 tmp
|= CMD_SET_RTYP_NO
;
348 tmp
|= CMD_SET_RTYP_6B
;
351 tmp
|= CMD_SET_RTYP_17B
;
354 printf(DRIVER_NAME
": Not support type response.\n");
359 if (opc
== MMC_CMD_SWITCH
)
365 switch (host
->bus_width
) {
366 case MMC_BUS_WIDTH_1
:
367 tmp
|= CMD_SET_DATW_1
;
369 case MMC_BUS_WIDTH_4
:
370 tmp
|= CMD_SET_DATW_4
;
372 case MMC_BUS_WIDTH_8
:
373 tmp
|= CMD_SET_DATW_8
;
376 printf(DRIVER_NAME
": Not support bus width.\n");
381 if (opc
== MMC_CMD_WRITE_SINGLE_BLOCK
||
382 opc
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)
385 if (opc
== MMC_CMD_READ_MULTIPLE_BLOCK
||
386 opc
== MMC_CMD_WRITE_MULTIPLE_BLOCK
) {
387 tmp
|= CMD_SET_CMLTE
| CMD_SET_CMD12EN
;
388 sh_mmcif_bitset(data
->blocks
<< 16, &host
->regs
->ce_block_set
);
390 /* RIDXC[1:0] check bits */
391 if (opc
== MMC_CMD_SEND_OP_COND
|| opc
== MMC_CMD_ALL_SEND_CID
||
392 opc
== MMC_CMD_SEND_CSD
|| opc
== MMC_CMD_SEND_CID
)
393 tmp
|= CMD_SET_RIDXC_BITS
;
394 /* RCRC7C[1:0] check bits */
395 if (opc
== MMC_CMD_SEND_OP_COND
)
396 tmp
|= CMD_SET_CRC7C_BITS
;
397 /* RCRC7C[1:0] internal CRC7 */
398 if (opc
== MMC_CMD_ALL_SEND_CID
||
399 opc
== MMC_CMD_SEND_CSD
|| opc
== MMC_CMD_SEND_CID
)
400 tmp
|= CMD_SET_CRC7C_INTERNAL
;
402 return opc
= ((opc
<< 24) | tmp
);
405 static u32
sh_mmcif_data_trans(struct sh_mmcif_host
*host
,
406 struct mmc_data
*data
, u16 opc
)
411 case MMC_CMD_READ_MULTIPLE_BLOCK
:
412 ret
= sh_mmcif_multi_read(host
, data
);
414 case MMC_CMD_WRITE_MULTIPLE_BLOCK
:
415 ret
= sh_mmcif_multi_write(host
, data
);
417 case MMC_CMD_WRITE_SINGLE_BLOCK
:
418 ret
= sh_mmcif_single_write(host
, data
);
420 case MMC_CMD_READ_SINGLE_BLOCK
:
421 case MMC_CMD_SEND_EXT_CSD
:
422 ret
= sh_mmcif_single_read(host
, data
);
425 printf(DRIVER_NAME
": NOT SUPPORT CMD = d'%08d\n", opc
);
432 static int sh_mmcif_start_cmd(struct sh_mmcif_host
*host
,
433 struct mmc_data
*data
, struct mmc_cmd
*cmd
)
436 int ret
= 0, mask
= 0;
437 u32 opc
= cmd
->cmdidx
;
439 if (opc
== MMC_CMD_STOP_TRANSMISSION
) {
440 /* MMCIF sends the STOP command automatically */
441 if (host
->last_cmd
== MMC_CMD_READ_MULTIPLE_BLOCK
)
442 sh_mmcif_bitset(MASK_MCMD12DRE
,
443 &host
->regs
->ce_int_mask
);
445 sh_mmcif_bitset(MASK_MCMD12RBE
,
446 &host
->regs
->ce_int_mask
);
448 time
= mmcif_wait_interrupt_flag(host
);
449 if (time
== 0 || host
->sd_error
!= 0)
450 return sh_mmcif_error_manage(host
);
452 sh_mmcif_get_cmd12response(host
, cmd
);
455 if (opc
== MMC_CMD_SWITCH
)
460 mask
|= MASK_MCMDVIO
| MASK_MBUFVIO
| MASK_MWDATERR
|
461 MASK_MRDATERR
| MASK_MRIDXERR
| MASK_MRSPERR
|
462 MASK_MCCSTO
| MASK_MCRCSTO
| MASK_MWDATTO
|
463 MASK_MRDATTO
| MASK_MRBSYTO
| MASK_MRSPTO
;
466 sh_mmcif_write(0, &host
->regs
->ce_block_set
);
467 sh_mmcif_write(data
->blocksize
, &host
->regs
->ce_block_set
);
469 opc
= sh_mmcif_set_cmd(host
, data
, cmd
);
471 sh_mmcif_write(INT_START_MAGIC
, &host
->regs
->ce_int
);
472 sh_mmcif_write(mask
, &host
->regs
->ce_int_mask
);
474 debug("CMD%d ARG:%08x\n", cmd
->cmdidx
, cmd
->cmdarg
);
476 sh_mmcif_write(cmd
->cmdarg
, &host
->regs
->ce_arg
);
479 sh_mmcif_write(opc
, &host
->regs
->ce_cmd_set
);
481 time
= mmcif_wait_interrupt_flag(host
);
483 return sh_mmcif_error_manage(host
);
485 if (host
->sd_error
) {
486 switch (cmd
->cmdidx
) {
487 case MMC_CMD_ALL_SEND_CID
:
488 case MMC_CMD_SELECT_CARD
:
489 case MMC_CMD_APP_CMD
:
493 printf(DRIVER_NAME
": Cmd(d'%d) err\n", cmd
->cmdidx
);
494 ret
= sh_mmcif_error_manage(host
);
503 if (!(opc
& 0x00C00000))
506 if (host
->wait_int
== 1) {
507 sh_mmcif_get_response(host
, cmd
);
511 ret
= sh_mmcif_data_trans(host
, data
, cmd
->cmdidx
);
512 host
->last_cmd
= cmd
->cmdidx
;
517 static int sh_mmcif_request(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
518 struct mmc_data
*data
)
520 struct sh_mmcif_host
*host
= mmc
->priv
;
525 switch (cmd
->cmdidx
) {
526 case MMC_CMD_APP_CMD
:
528 case MMC_CMD_SEND_EXT_CSD
: /* = SD_SEND_IF_COND (8) */
533 /* send_if_cond cmd (not support) */
540 ret
= sh_mmcif_start_cmd(host
, data
, cmd
);
546 static void sh_mmcif_set_ios(struct mmc
*mmc
)
548 struct sh_mmcif_host
*host
= mmc
->priv
;
551 sh_mmcif_clock_control(host
, mmc
->clock
);
553 if (mmc
->bus_width
== 8)
554 host
->bus_width
= MMC_BUS_WIDTH_8
;
555 else if (mmc
->bus_width
== 4)
556 host
->bus_width
= MMC_BUS_WIDTH_4
;
558 host
->bus_width
= MMC_BUS_WIDTH_1
;
560 debug("clock = %d, buswidth = %d\n", mmc
->clock
, mmc
->bus_width
);
563 static int sh_mmcif_init(struct mmc
*mmc
)
565 struct sh_mmcif_host
*host
= mmc
->priv
;
567 sh_mmcif_sync_reset(host
);
568 sh_mmcif_write(MASK_ALL
, &host
->regs
->ce_int_mask
);
572 static const struct mmc_ops sh_mmcif_ops
= {
573 .send_cmd
= sh_mmcif_request
,
574 .set_ios
= sh_mmcif_set_ios
,
575 .init
= sh_mmcif_init
,
578 static struct mmc_config sh_mmcif_cfg
= {
580 .ops
= &sh_mmcif_ops
,
581 .host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
| MMC_MODE_4BIT
|
582 MMC_MODE_8BIT
| MMC_MODE_HC
,
583 .voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
584 .f_min
= CLKDEV_MMC_INIT
,
585 .f_max
= CLKDEV_EMMC_DATA
,
586 .b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
589 int mmcif_mmc_init(void)
593 struct sh_mmcif_host
*host
= NULL
;
595 host
= malloc(sizeof(struct sh_mmcif_host
));
598 memset(host
, 0, sizeof(*host
));
600 host
->regs
= (struct sh_mmcif_regs
*)CONFIG_SH_MMCIF_ADDR
;
601 host
->clk
= CONFIG_SH_MMCIF_CLK
;
603 mmc
= mmc_create(&sh_mmcif_cfg
, host
);