drivers/mmc/sh_mmcif.h

   1 /*
   2  * MMCIF driver.
   3  *
   4  * Copyright (C)  2011 Renesas Solutions Corp.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 #ifndef _SH_MMCIF_H_
  10 #define _SH_MMCIF_H_
  11
  12 struct sh_mmcif_regs {
  13         unsigned long ce_cmd_set;
  14         unsigned long reserved;
  15         unsigned long ce_arg;
  16         unsigned long ce_arg_cmd12;
  17         unsigned long ce_cmd_ctrl;
  18         unsigned long ce_block_set;
  19         unsigned long ce_clk_ctrl;
  20         unsigned long ce_buf_acc;
  21         unsigned long ce_resp3;
  22         unsigned long ce_resp2;
  23         unsigned long ce_resp1;
  24         unsigned long ce_resp0;
  25         unsigned long ce_resp_cmd12;
  26         unsigned long ce_data;
  27         unsigned long reserved2[2];
  28         unsigned long ce_int;
  29         unsigned long ce_int_mask;
  30         unsigned long ce_host_sts1;
  31         unsigned long ce_host_sts2;
  32         unsigned long reserved3[11];
  33         unsigned long ce_version;
  34 };
  35
  36 /* CE_CMD_SET */
  37 #define CMD_MASK                0x3f000000
  38 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  39 /* R1/R1b/R3/R4/R5 */
  40 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22))
  41 /* R2 */
  42 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22))
  43 /* R1b */
  44 #define CMD_SET_RBSY            (1 << 21)
  45 #define CMD_SET_CCSEN           (1 << 20)
  46 /* 1: on data, 0: no data */
  47 #define CMD_SET_WDAT            (1 << 19)
  48 /* 1: write to card, 0: read from card */
  49 #define CMD_SET_DWEN            (1 << 18)
  50 /* 1: multi block trans, 0: single */
  51 #define CMD_SET_CMLTE           (1 << 17)
  52 /* 1: CMD12 auto issue */
  53 #define CMD_SET_CMD12EN         (1 << 16)
  54 /* index check */
  55 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14))
  56 /* check bits check */
  57 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14))
  58 /* no check */
  59 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14))
  60 /* 1: CRC7 check*/
  61 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12))
  62 /* 1: check bits check*/
  63 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12))
  64 /* 1: internal CRC7 check*/
  65 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12))
  66 /* 1: CRC16 check*/
  67 #define CMD_SET_CRC16C          (1 << 10)
  68 /* 1: not receive CRC status */
  69 #define CMD_SET_CRCSTE          (1 << 8)
  70 /* 1: tran mission bit "Low" */
  71 #define CMD_SET_TBIT            (1 << 7)
  72 /* 1: open/drain */
  73 #define CMD_SET_OPDM            (1 << 6)
  74 #define CMD_SET_CCSH            (1 << 5)
  75 /* 1bit */
  76 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0))
  77 /* 4bit */
  78 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0))
  79 /* 8bit */
  80 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0))
  81
  82 /* CE_CMD_CTRL */
  83 #define CMD_CTRL_BREAK          (1 << 0)
  84
  85 /* CE_BLOCK_SET */
  86 #define BLOCK_SIZE_MASK         0x0000ffff
  87
  88 /* CE_CLK_CTRL */
  89 #define CLK_ENABLE              (1 << 24)
  90 #define CLK_CLEAR               ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  91 #define CLK_PCLK                ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  92 /* respons timeout */
  93 #define SRSPTO_256              ((1 << 13) | (0 << 12))
  94 /* respons busy timeout */
  95 #define SRBSYTO_29              ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
  96 /* read/write timeout */
  97 #define SRWDTO_29               ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
  98 /* ccs timeout */
  99 #define SCCSTO_29               ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
 100
 101 /* CE_BUF_ACC */
 102 #define BUF_ACC_DMAWEN          (1 << 25)
 103 #define BUF_ACC_DMAREN          (1 << 24)
 104 #define BUF_ACC_BUSW_32         (0 << 17)
 105 #define BUF_ACC_BUSW_16         (1 << 17)
 106 #define BUF_ACC_ATYP            (1 << 16)
 107
 108 /* CE_INT */
 109 #define INT_CCSDE               (1 << 29)
 110 #define INT_CMD12DRE            (1 << 26)
 111 #define INT_CMD12RBE            (1 << 25)
 112 #define INT_CMD12CRE            (1 << 24)
 113 #define INT_DTRANE              (1 << 23)
 114 #define INT_BUFRE               (1 << 22)
 115 #define INT_BUFWEN              (1 << 21)
 116 #define INT_BUFREN              (1 << 20)
 117 #define INT_CCSRCV              (1 << 19)
 118 #define INT_RBSYE               (1 << 17)
 119 #define INT_CRSPE               (1 << 16)
 120 #define INT_CMDVIO              (1 << 15)
 121 #define INT_BUFVIO              (1 << 14)
 122 #define INT_WDATERR             (1 << 11)
 123 #define INT_RDATERR             (1 << 10)
 124 #define INT_RIDXERR             (1 << 9)
 125 #define INT_RSPERR              (1 << 8)
 126 #define INT_CCSTO               (1 << 5)
 127 #define INT_CRCSTO              (1 << 4)
 128 #define INT_WDATTO              (1 << 3)
 129 #define INT_RDATTO              (1 << 2)
 130 #define INT_RBSYTO              (1 << 1)
 131 #define INT_RSPTO               (1 << 0)
 132 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 133                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 134                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 135                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 136 #define INT_START_MAGIC         0xD80430C0
 137
 138 /* CE_INT_MASK */
 139 #define MASK_ALL                0x00000000
 140 #define MASK_MCCSDE             (1 << 29)
 141 #define MASK_MCMD12DRE          (1 << 26)
 142 #define MASK_MCMD12RBE          (1 << 25)
 143 #define MASK_MCMD12CRE          (1 << 24)
 144 #define MASK_MDTRANE            (1 << 23)
 145 #define MASK_MBUFRE             (1 << 22)
 146 #define MASK_MBUFWEN            (1 << 21)
 147 #define MASK_MBUFREN            (1 << 20)
 148 #define MASK_MCCSRCV            (1 << 19)
 149 #define MASK_MRBSYE             (1 << 17)
 150 #define MASK_MCRSPE             (1 << 16)
 151 #define MASK_MCMDVIO            (1 << 15)
 152 #define MASK_MBUFVIO            (1 << 14)
 153 #define MASK_MWDATERR           (1 << 11)
 154 #define MASK_MRDATERR           (1 << 10)
 155 #define MASK_MRIDXERR           (1 << 9)
 156 #define MASK_MRSPERR            (1 << 8)
 157 #define MASK_MCCSTO             (1 << 5)
 158 #define MASK_MCRCSTO            (1 << 4)
 159 #define MASK_MWDATTO            (1 << 3)
 160 #define MASK_MRDATTO            (1 << 2)
 161 #define MASK_MRBSYTO            (1 << 1)
 162 #define MASK_MRSPTO             (1 << 0)
 163
 164 /* CE_HOST_STS1 */
 165 #define STS1_CMDSEQ             (1 << 31)
 166
 167 /* CE_HOST_STS2 */
 168 #define STS2_CRCSTE             (1 << 31)
 169 #define STS2_CRC16E             (1 << 30)
 170 #define STS2_AC12CRCE           (1 << 29)
 171 #define STS2_RSPCRC7E           (1 << 28)
 172 #define STS2_CRCSTEBE           (1 << 27)
 173 #define STS2_RDATEBE            (1 << 26)
 174 #define STS2_AC12REBE           (1 << 25)
 175 #define STS2_RSPEBE             (1 << 24)
 176 #define STS2_AC12IDXE           (1 << 23)
 177 #define STS2_RSPIDXE            (1 << 22)
 178 #define STS2_CCSTO              (1 << 15)
 179 #define STS2_RDATTO             (1 << 14)
 180 #define STS2_DATBSYTO           (1 << 13)
 181 #define STS2_CRCSTTO            (1 << 12)
 182 #define STS2_AC12BSYTO          (1 << 11)
 183 #define STS2_RSPBSYTO           (1 << 10)
 184 #define STS2_AC12RSPTO          (1 << 9)
 185 #define STS2_RSPTO              (1 << 8)
 186
 187 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 188                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 189 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 190                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 191                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 192                                  STS2_AC12RSPTO | STS2_RSPTO)
 193
 194 /* CE_VERSION */
 195 #define SOFT_RST_ON             (1 << 31)
 196 #define SOFT_RST_OFF            (0 << 31)
 197
 198 #define CLKDEV_EMMC_DATA        52000000        /* 52MHz */
 199 #ifdef CONFIG_ARCH_RMOBILE
 200 #define MMC_CLK_DIV_MIN(clk)    (clk / (1 << 9))
 201 #define MMC_CLK_DIV_MAX(clk)    (clk / (1 << 1))
 202 #else
 203 #define MMC_CLK_DIV_MIN(clk)    (clk / (1 << 8))
 204 #define MMC_CLK_DIV_MAX(clk)    CLKDEV_EMMC_DATA
 205 #endif
 206
 207 #define MMC_BUS_WIDTH_1         0
 208 #define MMC_BUS_WIDTH_4         2
 209 #define MMC_BUS_WIDTH_8         3
 210
 211 struct sh_mmcif_host {
 212         struct mmc_data         *data;
 213         struct sh_mmcif_regs    *regs;
 214         unsigned int            clk;
 215         int                     bus_width;
 216         u16                     wait_int;
 217         u16                     sd_error;
 218         u8                      last_cmd;
 219 };
 220
 221 static inline u32 sh_mmcif_read(unsigned long *reg)
 222 {
 223         return readl(reg);
 224 }
 225
 226 static inline void sh_mmcif_write(u32 val, unsigned long *reg)
 227 {
 228         writel(val, reg);
 229 }
 230
 231 static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
 232 {
 233         sh_mmcif_write(val | sh_mmcif_read(reg), reg);
 234 }
 235
 236 static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
 237 {
 238         sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
 239 }
 240
 241 #endif /* _SH_MMCIF_H_ */