drivers/mmc/sunxi_mmc.c

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   4  * Aaron <leafy.myeh@allwinnertech.com>
   5  *
   6  * MMC driver for allwinner sunxi platform.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc.h>
  19 #include <asm-generic/gpio.h>
  20
  21 struct sunxi_mmc_host {
  22         unsigned mmc_no;
  23         uint32_t *mclkreg;
  24         unsigned fatal_err;
  25         struct sunxi_mmc *reg;
  26         struct mmc_config cfg;
  27 };
  28
  29 /* support 4 mmc hosts */
  30 struct sunxi_mmc_host mmc_host[4];
  31
  32 static int sunxi_mmc_getcd_gpio(int sdc_no)
  33 {
  34         switch (sdc_no) {
  35         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  36         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  37         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  38         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  39         }
  40         return -1;
  41 }
  42
  43 static int mmc_resource_init(int sdc_no)
  44 {
  45         struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
  46         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  47         int cd_pin, ret = 0;
  48
  49         debug("init mmc %d resource\n", sdc_no);
  50
  51         switch (sdc_no) {
  52         case 0:
  53                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  54                 mmchost->mclkreg = &ccm->sd0_clk_cfg;
  55                 break;
  56         case 1:
  57                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  58                 mmchost->mclkreg = &ccm->sd1_clk_cfg;
  59                 break;
  60         case 2:
  61                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  62                 mmchost->mclkreg = &ccm->sd2_clk_cfg;
  63                 break;
  64         case 3:
  65                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  66                 mmchost->mclkreg = &ccm->sd3_clk_cfg;
  67                 break;
  68         default:
  69                 printf("Wrong mmc number %d\n", sdc_no);
  70                 return -1;
  71         }
  72         mmchost->mmc_no = sdc_no;
  73
  74         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  75         if (cd_pin != -1) {
  76                 ret = gpio_request(cd_pin, "mmc_cd");
  77                 if (!ret)
  78                         ret = gpio_direction_input(cd_pin);
  79         }
  80
  81         return ret;
  82 }
  83
  84 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
  85 {
  86         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
  87
  88         if (hz <= 24000000) {
  89                 pll = CCM_MMC_CTRL_OSCM24;
  90                 pll_hz = 24000000;
  91         } else {
  92 #ifdef CONFIG_MACH_SUN9I
  93                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
  94                 pll_hz = clock_get_pll4_periph0();
  95 #else
  96                 pll = CCM_MMC_CTRL_PLL6;
  97                 pll_hz = clock_get_pll6();
  98 #endif
  99         }
 100
 101         div = pll_hz / hz;
 102         if (pll_hz % hz)
 103                 div++;
 104
 105         n = 0;
 106         while (div > 16) {
 107                 n++;
 108                 div = (div + 1) / 2;
 109         }
 110
 111         if (n > 3) {
 112                 printf("mmc %u error cannot set clock to %u\n",
 113                        mmchost->mmc_no, hz);
 114                 return -1;
 115         }
 116
 117         /* determine delays */
 118         if (hz <= 400000) {
 119                 oclk_dly = 0;
 120                 sclk_dly = 7;
 121         } else if (hz <= 25000000) {
 122                 oclk_dly = 0;
 123                 sclk_dly = 5;
 124         } else if (hz <= 50000000) {
 125                 oclk_dly = 3;
 126                 sclk_dly = 5;
 127         } else {
 128                 /* hz > 50000000 */
 129                 oclk_dly = 2;
 130                 sclk_dly = 4;
 131         }
 132
 133         writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
 134                CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 135                CCM_MMC_CTRL_M(div), mmchost->mclkreg);
 136
 137         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 138               mmchost->mmc_no, hz, pll_hz, 1u << n, div,
 139               pll_hz / (1u << n) / div);
 140
 141         return 0;
 142 }
 143
 144 static int mmc_clk_io_on(int sdc_no)
 145 {
 146         struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
 147         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 148
 149         debug("init mmc %d clock and io\n", sdc_no);
 150
 151         /* config ahb clock */
 152         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 153
 154 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
 155     defined(CONFIG_MACH_SUN9I)
 156         /* unassert reset */
 157         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 158 #endif
 159 #if defined(CONFIG_MACH_SUN9I)
 160         /* sun9i has a mmc-common module, also set the gate and reset there */
 161         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 162                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 163 #endif
 164
 165         return mmc_set_mod_clk(mmchost, 24000000);
 166 }
 167
 168 static int mmc_update_clk(struct mmc *mmc)
 169 {
 170         struct sunxi_mmc_host *mmchost = mmc->priv;
 171         unsigned int cmd;
 172         unsigned timeout_msecs = 2000;
 173
 174         cmd = SUNXI_MMC_CMD_START |
 175               SUNXI_MMC_CMD_UPCLK_ONLY |
 176               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 177         writel(cmd, &mmchost->reg->cmd);
 178         while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
 179                 if (!timeout_msecs--)
 180                         return -1;
 181                 udelay(1000);
 182         }
 183
 184         /* clock update sets various irq status bits, clear these */
 185         writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
 186
 187         return 0;
 188 }
 189
 190 static int mmc_config_clock(struct mmc *mmc)
 191 {
 192         struct sunxi_mmc_host *mmchost = mmc->priv;
 193         unsigned rval = readl(&mmchost->reg->clkcr);
 194
 195         /* Disable Clock */
 196         rval &= ~SUNXI_MMC_CLK_ENABLE;
 197         writel(rval, &mmchost->reg->clkcr);
 198         if (mmc_update_clk(mmc))
 199                 return -1;
 200
 201         /* Set mod_clk to new rate */
 202         if (mmc_set_mod_clk(mmchost, mmc->clock))
 203                 return -1;
 204
 205         /* Clear internal divider */
 206         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 207         writel(rval, &mmchost->reg->clkcr);
 208
 209         /* Re-enable Clock */
 210         rval |= SUNXI_MMC_CLK_ENABLE;
 211         writel(rval, &mmchost->reg->clkcr);
 212         if (mmc_update_clk(mmc))
 213                 return -1;
 214
 215         return 0;
 216 }
 217
 218 static void mmc_set_ios(struct mmc *mmc)
 219 {
 220         struct sunxi_mmc_host *mmchost = mmc->priv;
 221
 222         debug("set ios: bus_width: %x, clock: %d\n",
 223               mmc->bus_width, mmc->clock);
 224
 225         /* Change clock first */
 226         if (mmc->clock && mmc_config_clock(mmc) != 0) {
 227                 mmchost->fatal_err = 1;
 228                 return;
 229         }
 230
 231         /* Change bus width */
 232         if (mmc->bus_width == 8)
 233                 writel(0x2, &mmchost->reg->width);
 234         else if (mmc->bus_width == 4)
 235                 writel(0x1, &mmchost->reg->width);
 236         else
 237                 writel(0x0, &mmchost->reg->width);
 238 }
 239
 240 static int mmc_core_init(struct mmc *mmc)
 241 {
 242         struct sunxi_mmc_host *mmchost = mmc->priv;
 243
 244         /* Reset controller */
 245         writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 246         udelay(1000);
 247
 248         return 0;
 249 }
 250
 251 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 252 {
 253         struct sunxi_mmc_host *mmchost = mmc->priv;
 254         const int reading = !!(data->flags & MMC_DATA_READ);
 255         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 256                                               SUNXI_MMC_STATUS_FIFO_FULL;
 257         unsigned i;
 258         unsigned byte_cnt = data->blocksize * data->blocks;
 259         unsigned timeout_msecs = 2000;
 260         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 261
 262         /* Always read / write data through the CPU */
 263         setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 264
 265         for (i = 0; i < (byte_cnt >> 2); i++) {
 266                 while (readl(&mmchost->reg->status) & status_bit) {
 267                         if (!timeout_msecs--)
 268                                 return -1;
 269                         udelay(1000);
 270                 }
 271
 272                 if (reading)
 273                         buff[i] = readl(&mmchost->reg->fifo);
 274                 else
 275                         writel(buff[i], &mmchost->reg->fifo);
 276         }
 277
 278         return 0;
 279 }
 280
 281 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
 282                          unsigned int done_bit, const char *what)
 283 {
 284         struct sunxi_mmc_host *mmchost = mmc->priv;
 285         unsigned int status;
 286
 287         do {
 288                 status = readl(&mmchost->reg->rint);
 289                 if (!timeout_msecs-- ||
 290                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 291                         debug("%s timeout %x\n", what,
 292                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 293                         return TIMEOUT;
 294                 }
 295                 udelay(1000);
 296         } while (!(status & done_bit));
 297
 298         return 0;
 299 }
 300
 301 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 302                         struct mmc_data *data)
 303 {
 304         struct sunxi_mmc_host *mmchost = mmc->priv;
 305         unsigned int cmdval = SUNXI_MMC_CMD_START;
 306         unsigned int timeout_msecs;
 307         int error = 0;
 308         unsigned int status = 0;
 309         unsigned int bytecnt = 0;
 310
 311         if (mmchost->fatal_err)
 312                 return -1;
 313         if (cmd->resp_type & MMC_RSP_BUSY)
 314                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 315         if (cmd->cmdidx == 12)
 316                 return 0;
 317
 318         if (!cmd->cmdidx)
 319                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 320         if (cmd->resp_type & MMC_RSP_PRESENT)
 321                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 322         if (cmd->resp_type & MMC_RSP_136)
 323                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 324         if (cmd->resp_type & MMC_RSP_CRC)
 325                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 326
 327         if (data) {
 328                 if ((u32) data->dest & 0x3) {
 329                         error = -1;
 330                         goto out;
 331                 }
 332
 333                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 334                 if (data->flags & MMC_DATA_WRITE)
 335                         cmdval |= SUNXI_MMC_CMD_WRITE;
 336                 if (data->blocks > 1)
 337                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 338                 writel(data->blocksize, &mmchost->reg->blksz);
 339                 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
 340         }
 341
 342         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
 343               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 344         writel(cmd->cmdarg, &mmchost->reg->arg);
 345
 346         if (!data)
 347                 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
 348
 349         /*
 350          * transfer data and check status
 351          * STATREG[2] : FIFO empty
 352          * STATREG[3] : FIFO full
 353          */
 354         if (data) {
 355                 int ret = 0;
 356
 357                 bytecnt = data->blocksize * data->blocks;
 358                 debug("trans data %d bytes\n", bytecnt);
 359                 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
 360                 ret = mmc_trans_data_by_cpu(mmc, data);
 361                 if (ret) {
 362                         error = readl(&mmchost->reg->rint) & \
 363                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 364                         error = TIMEOUT;
 365                         goto out;
 366                 }
 367         }
 368
 369         error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
 370         if (error)
 371                 goto out;
 372
 373         if (data) {
 374                 timeout_msecs = 120;
 375                 debug("cacl timeout %x msec\n", timeout_msecs);
 376                 error = mmc_rint_wait(mmc, timeout_msecs,
 377                                       data->blocks > 1 ?
 378                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 379                                       SUNXI_MMC_RINT_DATA_OVER,
 380                                       "data");
 381                 if (error)
 382                         goto out;
 383         }
 384
 385         if (cmd->resp_type & MMC_RSP_BUSY) {
 386                 timeout_msecs = 2000;
 387                 do {
 388                         status = readl(&mmchost->reg->status);
 389                         if (!timeout_msecs--) {
 390                                 debug("busy timeout\n");
 391                                 error = TIMEOUT;
 392                                 goto out;
 393                         }
 394                         udelay(1000);
 395                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 396         }
 397
 398         if (cmd->resp_type & MMC_RSP_136) {
 399                 cmd->response[0] = readl(&mmchost->reg->resp3);
 400                 cmd->response[1] = readl(&mmchost->reg->resp2);
 401                 cmd->response[2] = readl(&mmchost->reg->resp1);
 402                 cmd->response[3] = readl(&mmchost->reg->resp0);
 403                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 404                       cmd->response[3], cmd->response[2],
 405                       cmd->response[1], cmd->response[0]);
 406         } else {
 407                 cmd->response[0] = readl(&mmchost->reg->resp0);
 408                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 409         }
 410 out:
 411         if (error < 0) {
 412                 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 413                 mmc_update_clk(mmc);
 414         }
 415         writel(0xffffffff, &mmchost->reg->rint);
 416         writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 417                &mmchost->reg->gctrl);
 418
 419         return error;
 420 }
 421
 422 static int sunxi_mmc_getcd(struct mmc *mmc)
 423 {
 424         struct sunxi_mmc_host *mmchost = mmc->priv;
 425         int cd_pin;
 426
 427         cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
 428         if (cd_pin == -1)
 429                 return 1;
 430
 431         return !gpio_get_value(cd_pin);
 432 }
 433
 434 static const struct mmc_ops sunxi_mmc_ops = {
 435         .send_cmd       = mmc_send_cmd,
 436         .set_ios        = mmc_set_ios,
 437         .init           = mmc_core_init,
 438         .getcd          = sunxi_mmc_getcd,
 439 };
 440
 441 struct mmc *sunxi_mmc_init(int sdc_no)
 442 {
 443         struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
 444
 445         memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
 446
 447         cfg->name = "SUNXI SD/MMC";
 448         cfg->ops  = &sunxi_mmc_ops;
 449
 450         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 451         cfg->host_caps = MMC_MODE_4BIT;
 452         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 453 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
 454     defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
 455         cfg->host_caps |= MMC_MODE_HC;
 456 #endif
 457         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 458
 459         cfg->f_min = 400000;
 460         cfg->f_max = 52000000;
 461
 462         if (mmc_resource_init(sdc_no) != 0)
 463                 return NULL;
 464
 465         mmc_clk_io_on(sdc_no);
 466
 467         return mmc_create(cfg, &mmc_host[sdc_no]);
 468 }