2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm-generic/gpio.h>
23 struct sunxi_mmc_plat
{
24 struct mmc_config cfg
;
28 struct sunxi_mmc_priv
{
32 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
33 struct sunxi_mmc
*reg
;
34 struct mmc_config cfg
;
37 #if !CONFIG_IS_ENABLED(DM_MMC)
38 /* support 4 mmc hosts */
39 struct sunxi_mmc_priv mmc_host
[4];
41 static int sunxi_mmc_getcd_gpio(int sdc_no
)
44 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN
);
45 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN
);
46 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN
);
47 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN
);
52 static int mmc_resource_init(int sdc_no
)
54 struct sunxi_mmc_priv
*priv
= &mmc_host
[sdc_no
];
55 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
58 debug("init mmc %d resource\n", sdc_no
);
62 priv
->reg
= (struct sunxi_mmc
*)SUNXI_MMC0_BASE
;
63 priv
->mclkreg
= &ccm
->sd0_clk_cfg
;
66 priv
->reg
= (struct sunxi_mmc
*)SUNXI_MMC1_BASE
;
67 priv
->mclkreg
= &ccm
->sd1_clk_cfg
;
70 priv
->reg
= (struct sunxi_mmc
*)SUNXI_MMC2_BASE
;
71 priv
->mclkreg
= &ccm
->sd2_clk_cfg
;
74 priv
->reg
= (struct sunxi_mmc
*)SUNXI_MMC3_BASE
;
75 priv
->mclkreg
= &ccm
->sd3_clk_cfg
;
78 printf("Wrong mmc number %d\n", sdc_no
);
81 priv
->mmc_no
= sdc_no
;
83 cd_pin
= sunxi_mmc_getcd_gpio(sdc_no
);
85 ret
= gpio_request(cd_pin
, "mmc_cd");
87 sunxi_gpio_set_pull(cd_pin
, SUNXI_GPIO_PULL_UP
);
88 ret
= gpio_direction_input(cd_pin
);
96 static int mmc_set_mod_clk(struct sunxi_mmc_priv
*priv
, unsigned int hz
)
98 unsigned int pll
, pll_hz
, div
, n
, oclk_dly
, sclk_dly
;
100 if (hz
<= 24000000) {
101 pll
= CCM_MMC_CTRL_OSCM24
;
104 #ifdef CONFIG_MACH_SUN9I
105 pll
= CCM_MMC_CTRL_PLL_PERIPH0
;
106 pll_hz
= clock_get_pll4_periph0();
108 pll
= CCM_MMC_CTRL_PLL6
;
109 pll_hz
= clock_get_pll6();
124 printf("mmc %u error cannot set clock to %u\n", priv
->mmc_no
,
129 /* determine delays */
133 } else if (hz
<= 25000000) {
136 #ifdef CONFIG_MACH_SUN9I
137 } else if (hz
<= 50000000) {
145 } else if (hz
<= 50000000) {
155 writel(CCM_MMC_CTRL_ENABLE
| pll
| CCM_MMC_CTRL_SCLK_DLY(sclk_dly
) |
156 CCM_MMC_CTRL_N(n
) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly
) |
157 CCM_MMC_CTRL_M(div
), priv
->mclkreg
);
159 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
160 priv
->mmc_no
, hz
, pll_hz
, 1u << n
, div
, pll_hz
/ (1u << n
) / div
);
165 static int mmc_update_clk(struct sunxi_mmc_priv
*priv
)
168 unsigned timeout_msecs
= 2000;
170 cmd
= SUNXI_MMC_CMD_START
|
171 SUNXI_MMC_CMD_UPCLK_ONLY
|
172 SUNXI_MMC_CMD_WAIT_PRE_OVER
;
173 writel(cmd
, &priv
->reg
->cmd
);
174 while (readl(&priv
->reg
->cmd
) & SUNXI_MMC_CMD_START
) {
175 if (!timeout_msecs
--)
180 /* clock update sets various irq status bits, clear these */
181 writel(readl(&priv
->reg
->rint
), &priv
->reg
->rint
);
186 static int mmc_config_clock(struct sunxi_mmc_priv
*priv
, struct mmc
*mmc
)
188 unsigned rval
= readl(&priv
->reg
->clkcr
);
191 rval
&= ~SUNXI_MMC_CLK_ENABLE
;
192 writel(rval
, &priv
->reg
->clkcr
);
193 if (mmc_update_clk(priv
))
196 /* Set mod_clk to new rate */
197 if (mmc_set_mod_clk(priv
, mmc
->clock
))
200 /* Clear internal divider */
201 rval
&= ~SUNXI_MMC_CLK_DIVIDER_MASK
;
202 writel(rval
, &priv
->reg
->clkcr
);
204 /* Re-enable Clock */
205 rval
|= SUNXI_MMC_CLK_ENABLE
;
206 writel(rval
, &priv
->reg
->clkcr
);
207 if (mmc_update_clk(priv
))
213 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv
*priv
,
216 debug("set ios: bus_width: %x, clock: %d\n",
217 mmc
->bus_width
, mmc
->clock
);
219 /* Change clock first */
220 if (mmc
->clock
&& mmc_config_clock(priv
, mmc
) != 0) {
225 /* Change bus width */
226 if (mmc
->bus_width
== 8)
227 writel(0x2, &priv
->reg
->width
);
228 else if (mmc
->bus_width
== 4)
229 writel(0x1, &priv
->reg
->width
);
231 writel(0x0, &priv
->reg
->width
);
236 #if !CONFIG_IS_ENABLED(DM_MMC)
237 static int sunxi_mmc_core_init(struct mmc
*mmc
)
239 struct sunxi_mmc_priv
*priv
= mmc
->priv
;
241 /* Reset controller */
242 writel(SUNXI_MMC_GCTRL_RESET
, &priv
->reg
->gctrl
);
249 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv
*priv
, struct mmc
*mmc
,
250 struct mmc_data
*data
)
252 const int reading
= !!(data
->flags
& MMC_DATA_READ
);
253 const uint32_t status_bit
= reading
? SUNXI_MMC_STATUS_FIFO_EMPTY
:
254 SUNXI_MMC_STATUS_FIFO_FULL
;
256 unsigned *buff
= (unsigned int *)(reading
? data
->dest
: data
->src
);
257 unsigned byte_cnt
= data
->blocksize
* data
->blocks
;
258 unsigned timeout_usecs
= (byte_cnt
>> 8) * 1000;
259 if (timeout_usecs
< 2000000)
260 timeout_usecs
= 2000000;
262 /* Always read / write data through the CPU */
263 setbits_le32(&priv
->reg
->gctrl
, SUNXI_MMC_GCTRL_ACCESS_BY_AHB
);
265 for (i
= 0; i
< (byte_cnt
>> 2); i
++) {
266 while (readl(&priv
->reg
->status
) & status_bit
) {
267 if (!timeout_usecs
--)
273 buff
[i
] = readl(&priv
->reg
->fifo
);
275 writel(buff
[i
], &priv
->reg
->fifo
);
281 static int mmc_rint_wait(struct sunxi_mmc_priv
*priv
, struct mmc
*mmc
,
282 uint timeout_msecs
, uint done_bit
, const char *what
)
287 status
= readl(&priv
->reg
->rint
);
288 if (!timeout_msecs
-- ||
289 (status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
)) {
290 debug("%s timeout %x\n", what
,
291 status
& SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
);
295 } while (!(status
& done_bit
));
300 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv
*priv
,
301 struct mmc
*mmc
, struct mmc_cmd
*cmd
,
302 struct mmc_data
*data
)
304 unsigned int cmdval
= SUNXI_MMC_CMD_START
;
305 unsigned int timeout_msecs
;
307 unsigned int status
= 0;
308 unsigned int bytecnt
= 0;
312 if (cmd
->resp_type
& MMC_RSP_BUSY
)
313 debug("mmc cmd %d check rsp busy\n", cmd
->cmdidx
);
314 if (cmd
->cmdidx
== 12)
318 cmdval
|= SUNXI_MMC_CMD_SEND_INIT_SEQ
;
319 if (cmd
->resp_type
& MMC_RSP_PRESENT
)
320 cmdval
|= SUNXI_MMC_CMD_RESP_EXPIRE
;
321 if (cmd
->resp_type
& MMC_RSP_136
)
322 cmdval
|= SUNXI_MMC_CMD_LONG_RESPONSE
;
323 if (cmd
->resp_type
& MMC_RSP_CRC
)
324 cmdval
|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC
;
327 if ((u32
)(long)data
->dest
& 0x3) {
332 cmdval
|= SUNXI_MMC_CMD_DATA_EXPIRE
|SUNXI_MMC_CMD_WAIT_PRE_OVER
;
333 if (data
->flags
& MMC_DATA_WRITE
)
334 cmdval
|= SUNXI_MMC_CMD_WRITE
;
335 if (data
->blocks
> 1)
336 cmdval
|= SUNXI_MMC_CMD_AUTO_STOP
;
337 writel(data
->blocksize
, &priv
->reg
->blksz
);
338 writel(data
->blocks
* data
->blocksize
, &priv
->reg
->bytecnt
);
341 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv
->mmc_no
,
342 cmd
->cmdidx
, cmdval
| cmd
->cmdidx
, cmd
->cmdarg
);
343 writel(cmd
->cmdarg
, &priv
->reg
->arg
);
346 writel(cmdval
| cmd
->cmdidx
, &priv
->reg
->cmd
);
349 * transfer data and check status
350 * STATREG[2] : FIFO empty
351 * STATREG[3] : FIFO full
356 bytecnt
= data
->blocksize
* data
->blocks
;
357 debug("trans data %d bytes\n", bytecnt
);
358 writel(cmdval
| cmd
->cmdidx
, &priv
->reg
->cmd
);
359 ret
= mmc_trans_data_by_cpu(priv
, mmc
, data
);
361 error
= readl(&priv
->reg
->rint
) &
362 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT
;
368 error
= mmc_rint_wait(priv
, mmc
, 1000, SUNXI_MMC_RINT_COMMAND_DONE
,
375 debug("cacl timeout %x msec\n", timeout_msecs
);
376 error
= mmc_rint_wait(priv
, mmc
, timeout_msecs
,
378 SUNXI_MMC_RINT_AUTO_COMMAND_DONE
:
379 SUNXI_MMC_RINT_DATA_OVER
,
385 if (cmd
->resp_type
& MMC_RSP_BUSY
) {
386 timeout_msecs
= 2000;
388 status
= readl(&priv
->reg
->status
);
389 if (!timeout_msecs
--) {
390 debug("busy timeout\n");
395 } while (status
& SUNXI_MMC_STATUS_CARD_DATA_BUSY
);
398 if (cmd
->resp_type
& MMC_RSP_136
) {
399 cmd
->response
[0] = readl(&priv
->reg
->resp3
);
400 cmd
->response
[1] = readl(&priv
->reg
->resp2
);
401 cmd
->response
[2] = readl(&priv
->reg
->resp1
);
402 cmd
->response
[3] = readl(&priv
->reg
->resp0
);
403 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
404 cmd
->response
[3], cmd
->response
[2],
405 cmd
->response
[1], cmd
->response
[0]);
407 cmd
->response
[0] = readl(&priv
->reg
->resp0
);
408 debug("mmc resp 0x%08x\n", cmd
->response
[0]);
412 writel(SUNXI_MMC_GCTRL_RESET
, &priv
->reg
->gctrl
);
413 mmc_update_clk(priv
);
415 writel(0xffffffff, &priv
->reg
->rint
);
416 writel(readl(&priv
->reg
->gctrl
) | SUNXI_MMC_GCTRL_FIFO_RESET
,
422 #if !CONFIG_IS_ENABLED(DM_MMC)
423 static int sunxi_mmc_set_ios_legacy(struct mmc
*mmc
)
425 struct sunxi_mmc_priv
*priv
= mmc
->priv
;
427 return sunxi_mmc_set_ios_common(priv
, mmc
);
430 static int sunxi_mmc_send_cmd_legacy(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
431 struct mmc_data
*data
)
433 struct sunxi_mmc_priv
*priv
= mmc
->priv
;
435 return sunxi_mmc_send_cmd_common(priv
, mmc
, cmd
, data
);
438 static int sunxi_mmc_getcd_legacy(struct mmc
*mmc
)
440 struct sunxi_mmc_priv
*priv
= mmc
->priv
;
443 cd_pin
= sunxi_mmc_getcd_gpio(priv
->mmc_no
);
447 return !gpio_get_value(cd_pin
);
450 static const struct mmc_ops sunxi_mmc_ops
= {
451 .send_cmd
= sunxi_mmc_send_cmd_legacy
,
452 .set_ios
= sunxi_mmc_set_ios_legacy
,
453 .init
= sunxi_mmc_core_init
,
454 .getcd
= sunxi_mmc_getcd_legacy
,
457 struct mmc
*sunxi_mmc_init(int sdc_no
)
459 struct sunxi_ccm_reg
*ccm
= (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
460 struct sunxi_mmc_priv
*priv
= &mmc_host
[sdc_no
];
461 struct mmc_config
*cfg
= &priv
->cfg
;
464 memset(priv
, '\0', sizeof(struct sunxi_mmc_priv
));
466 cfg
->name
= "SUNXI SD/MMC";
467 cfg
->ops
= &sunxi_mmc_ops
;
469 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
470 cfg
->host_caps
= MMC_MODE_4BIT
;
471 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
473 cfg
->host_caps
= MMC_MODE_8BIT
;
475 cfg
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
476 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
479 cfg
->f_max
= 52000000;
481 if (mmc_resource_init(sdc_no
) != 0)
484 /* config ahb clock */
485 debug("init mmc %d clock and io\n", sdc_no
);
486 setbits_le32(&ccm
->ahb_gate0
, 1 << AHB_GATE_OFFSET_MMC(sdc_no
));
488 #ifdef CONFIG_SUNXI_GEN_SUN6I
490 setbits_le32(&ccm
->ahb_reset0_cfg
, 1 << AHB_RESET_OFFSET_MMC(sdc_no
));
492 #if defined(CONFIG_MACH_SUN9I)
493 /* sun9i has a mmc-common module, also set the gate and reset there */
494 writel(SUNXI_MMC_COMMON_CLK_GATE
| SUNXI_MMC_COMMON_RESET
,
495 SUNXI_MMC_COMMON_BASE
+ 4 * sdc_no
);
497 ret
= mmc_set_mod_clk(priv
, 24000000);
501 return mmc_create(cfg
, mmc_host
);
505 static int sunxi_mmc_set_ios(struct udevice
*dev
)
507 struct sunxi_mmc_plat
*plat
= dev_get_platdata(dev
);
508 struct sunxi_mmc_priv
*priv
= dev_get_priv(dev
);
510 return sunxi_mmc_set_ios_common(priv
, &plat
->mmc
);
513 static int sunxi_mmc_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
514 struct mmc_data
*data
)
516 struct sunxi_mmc_plat
*plat
= dev_get_platdata(dev
);
517 struct sunxi_mmc_priv
*priv
= dev_get_priv(dev
);
519 return sunxi_mmc_send_cmd_common(priv
, &plat
->mmc
, cmd
, data
);
522 static int sunxi_mmc_getcd(struct udevice
*dev
)
524 struct sunxi_mmc_priv
*priv
= dev_get_priv(dev
);
526 if (dm_gpio_is_valid(&priv
->cd_gpio
))
527 return dm_gpio_get_value(&priv
->cd_gpio
);
532 static const struct dm_mmc_ops sunxi_mmc_ops
= {
533 .send_cmd
= sunxi_mmc_send_cmd
,
534 .set_ios
= sunxi_mmc_set_ios
,
535 .get_cd
= sunxi_mmc_getcd
,
538 static int sunxi_mmc_probe(struct udevice
*dev
)
540 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
541 struct sunxi_mmc_plat
*plat
= dev_get_platdata(dev
);
542 struct sunxi_mmc_priv
*priv
= dev_get_priv(dev
);
543 struct mmc_config
*cfg
= &plat
->cfg
;
544 struct ofnode_phandle_args args
;
548 cfg
->name
= dev
->name
;
549 bus_width
= dev_read_u32_default(dev
, "bus-width", 1);
551 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
554 cfg
->host_caps
|= MMC_MODE_8BIT
;
556 cfg
->host_caps
|= MMC_MODE_4BIT
;
557 cfg
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
558 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
561 cfg
->f_max
= 52000000;
563 priv
->reg
= (void *)dev_read_addr(dev
);
565 /* We don't have a sunxi clock driver so find the clock address here */
566 ret
= dev_read_phandle_with_args(dev
, "clocks", "#clock-cells", 0,
570 priv
->mclkreg
= (u32
*)ofnode_get_addr(args
.node
);
572 ret
= dev_read_phandle_with_args(dev
, "clocks", "#clock-cells", 0,
576 gate_reg
= (u32
*)ofnode_get_addr(args
.node
);
577 setbits_le32(gate_reg
, 1 << args
.args
[0]);
578 priv
->mmc_no
= args
.args
[0] - 8;
580 ret
= mmc_set_mod_clk(priv
, 24000000);
584 /* This GPIO is optional */
585 if (!gpio_request_by_name(dev
, "cd-gpios", 0, &priv
->cd_gpio
,
587 int cd_pin
= gpio_get_number(&priv
->cd_gpio
);
589 sunxi_gpio_set_pull(cd_pin
, SUNXI_GPIO_PULL_UP
);
592 upriv
->mmc
= &plat
->mmc
;
594 /* Reset controller */
595 writel(SUNXI_MMC_GCTRL_RESET
, &priv
->reg
->gctrl
);
601 static int sunxi_mmc_bind(struct udevice
*dev
)
603 struct sunxi_mmc_plat
*plat
= dev_get_platdata(dev
);
605 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
608 static const struct udevice_id sunxi_mmc_ids
[] = {
609 { .compatible
= "allwinner,sun5i-a13-mmc" },
613 U_BOOT_DRIVER(sunxi_mmc_drv
) = {
616 .of_match
= sunxi_mmc_ids
,
617 .bind
= sunxi_mmc_bind
,
618 .probe
= sunxi_mmc_probe
,
619 .ops
= &sunxi_mmc_ops
,
620 .platdata_auto_alloc_size
= sizeof(struct sunxi_mmc_plat
),
621 .priv_auto_alloc_size
= sizeof(struct sunxi_mmc_priv
),