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mmc: Split mmc struct, rework mmc initialization (v2)
[people/ms/u-boot.git] / drivers / mmc / tegra_mmc.c
1 /*
2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011-2013 NVIDIA Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <bouncebuf.h>
11 #include <common.h>
12 #include <asm/gpio.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/tegra_mmc.h>
17 #include <mmc.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 struct mmc_host mmc_host[MAX_HOSTS];
22
23 #ifndef CONFIG_OF_CONTROL
24 #error "Please enable device tree support to use this driver"
25 #endif
26
27 static void mmc_set_power(struct mmc_host *host, unsigned short power)
28 {
29 u8 pwr = 0;
30 debug("%s: power = %x\n", __func__, power);
31
32 if (power != (unsigned short)-1) {
33 switch (1 << power) {
34 case MMC_VDD_165_195:
35 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
36 break;
37 case MMC_VDD_29_30:
38 case MMC_VDD_30_31:
39 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
40 break;
41 case MMC_VDD_32_33:
42 case MMC_VDD_33_34:
43 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
44 break;
45 }
46 }
47 debug("%s: pwr = %X\n", __func__, pwr);
48
49 /* Set the bus voltage first (if any) */
50 writeb(pwr, &host->reg->pwrcon);
51 if (pwr == 0)
52 return;
53
54 /* Now enable bus power */
55 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
56 writeb(pwr, &host->reg->pwrcon);
57 }
58
59 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
60 struct bounce_buffer *bbstate)
61 {
62 unsigned char ctrl;
63
64
65 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
66 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
67 data->blocksize);
68
69 writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
70 /*
71 * DMASEL[4:3]
72 * 00 = Selects SDMA
73 * 01 = Reserved
74 * 10 = Selects 32-bit Address ADMA2
75 * 11 = Selects 64-bit Address ADMA2
76 */
77 ctrl = readb(&host->reg->hostctl);
78 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
79 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
80 writeb(ctrl, &host->reg->hostctl);
81
82 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
83 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
84 writew(data->blocks, &host->reg->blkcnt);
85 }
86
87 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
88 {
89 unsigned short mode;
90 debug(" mmc_set_transfer_mode called\n");
91 /*
92 * TRNMOD
93 * MUL1SIN0[5] : Multi/Single Block Select
94 * RD1WT0[4] : Data Transfer Direction Select
95 * 1 = read
96 * 0 = write
97 * ENACMD12[2] : Auto CMD12 Enable
98 * ENBLKCNT[1] : Block Count Enable
99 * ENDMA[0] : DMA Enable
100 */
101 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
102 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
103
104 if (data->blocks > 1)
105 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
106
107 if (data->flags & MMC_DATA_READ)
108 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
109
110 writew(mode, &host->reg->trnmod);
111 }
112
113 static int mmc_wait_inhibit(struct mmc_host *host,
114 struct mmc_cmd *cmd,
115 struct mmc_data *data,
116 unsigned int timeout)
117 {
118 /*
119 * PRNSTS
120 * CMDINHDAT[1] : Command Inhibit (DAT)
121 * CMDINHCMD[0] : Command Inhibit (CMD)
122 */
123 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
124
125 /*
126 * We shouldn't wait for data inhibit for stop commands, even
127 * though they might use busy signaling
128 */
129 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
130 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
131
132 while (readl(&host->reg->prnsts) & mask) {
133 if (timeout == 0) {
134 printf("%s: timeout error\n", __func__);
135 return -1;
136 }
137 timeout--;
138 udelay(1000);
139 }
140
141 return 0;
142 }
143
144 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
145 struct mmc_data *data, struct bounce_buffer *bbstate)
146 {
147 struct mmc_host *host = mmc->priv;
148 int flags, i;
149 int result;
150 unsigned int mask = 0;
151 unsigned int retry = 0x100000;
152 debug(" mmc_send_cmd called\n");
153
154 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
155
156 if (result < 0)
157 return result;
158
159 if (data)
160 mmc_prepare_data(host, data, bbstate);
161
162 debug("cmd->arg: %08x\n", cmd->cmdarg);
163 writel(cmd->cmdarg, &host->reg->argument);
164
165 if (data)
166 mmc_set_transfer_mode(host, data);
167
168 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
169 return -1;
170
171 /*
172 * CMDREG
173 * CMDIDX[13:8] : Command index
174 * DATAPRNT[5] : Data Present Select
175 * ENCMDIDX[4] : Command Index Check Enable
176 * ENCMDCRC[3] : Command CRC Check Enable
177 * RSPTYP[1:0]
178 * 00 = No Response
179 * 01 = Length 136
180 * 10 = Length 48
181 * 11 = Length 48 Check busy after response
182 */
183 if (!(cmd->resp_type & MMC_RSP_PRESENT))
184 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
185 else if (cmd->resp_type & MMC_RSP_136)
186 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
187 else if (cmd->resp_type & MMC_RSP_BUSY)
188 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
189 else
190 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
191
192 if (cmd->resp_type & MMC_RSP_CRC)
193 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
194 if (cmd->resp_type & MMC_RSP_OPCODE)
195 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
196 if (data)
197 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
198
199 debug("cmd: %d\n", cmd->cmdidx);
200
201 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
202
203 for (i = 0; i < retry; i++) {
204 mask = readl(&host->reg->norintsts);
205 /* Command Complete */
206 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
207 if (!data)
208 writel(mask, &host->reg->norintsts);
209 break;
210 }
211 }
212
213 if (i == retry) {
214 printf("%s: waiting for status update\n", __func__);
215 writel(mask, &host->reg->norintsts);
216 return TIMEOUT;
217 }
218
219 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
220 /* Timeout Error */
221 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
222 writel(mask, &host->reg->norintsts);
223 return TIMEOUT;
224 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
225 /* Error Interrupt */
226 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
227 writel(mask, &host->reg->norintsts);
228 return -1;
229 }
230
231 if (cmd->resp_type & MMC_RSP_PRESENT) {
232 if (cmd->resp_type & MMC_RSP_136) {
233 /* CRC is stripped so we need to do some shifting. */
234 for (i = 0; i < 4; i++) {
235 unsigned int offset =
236 (unsigned int)(&host->reg->rspreg3 - i);
237 cmd->response[i] = readl(offset) << 8;
238
239 if (i != 3) {
240 cmd->response[i] |=
241 readb(offset - 1);
242 }
243 debug("cmd->resp[%d]: %08x\n",
244 i, cmd->response[i]);
245 }
246 } else if (cmd->resp_type & MMC_RSP_BUSY) {
247 for (i = 0; i < retry; i++) {
248 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
249 if (readl(&host->reg->prnsts)
250 & (1 << 20)) /* DAT[0] */
251 break;
252 }
253
254 if (i == retry) {
255 printf("%s: card is still busy\n", __func__);
256 writel(mask, &host->reg->norintsts);
257 return TIMEOUT;
258 }
259
260 cmd->response[0] = readl(&host->reg->rspreg0);
261 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
262 } else {
263 cmd->response[0] = readl(&host->reg->rspreg0);
264 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
265 }
266 }
267
268 if (data) {
269 unsigned long start = get_timer(0);
270
271 while (1) {
272 mask = readl(&host->reg->norintsts);
273
274 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
275 /* Error Interrupt */
276 writel(mask, &host->reg->norintsts);
277 printf("%s: error during transfer: 0x%08x\n",
278 __func__, mask);
279 return -1;
280 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
281 /*
282 * DMA Interrupt, restart the transfer where
283 * it was interrupted.
284 */
285 unsigned int address = readl(&host->reg->sysad);
286
287 debug("DMA end\n");
288 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
289 &host->reg->norintsts);
290 writel(address, &host->reg->sysad);
291 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
292 /* Transfer Complete */
293 debug("r/w is done\n");
294 break;
295 } else if (get_timer(start) > 2000UL) {
296 writel(mask, &host->reg->norintsts);
297 printf("%s: MMC Timeout\n"
298 " Interrupt status 0x%08x\n"
299 " Interrupt status enable 0x%08x\n"
300 " Interrupt signal enable 0x%08x\n"
301 " Present status 0x%08x\n",
302 __func__, mask,
303 readl(&host->reg->norintstsen),
304 readl(&host->reg->norintsigen),
305 readl(&host->reg->prnsts));
306 return -1;
307 }
308 }
309 writel(mask, &host->reg->norintsts);
310 }
311
312 udelay(1000);
313 return 0;
314 }
315
316 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
317 struct mmc_data *data)
318 {
319 void *buf;
320 unsigned int bbflags;
321 size_t len;
322 struct bounce_buffer bbstate;
323 int ret;
324
325 if (data) {
326 if (data->flags & MMC_DATA_READ) {
327 buf = data->dest;
328 bbflags = GEN_BB_WRITE;
329 } else {
330 buf = (void *)data->src;
331 bbflags = GEN_BB_READ;
332 }
333 len = data->blocks * data->blocksize;
334
335 bounce_buffer_start(&bbstate, buf, len, bbflags);
336 }
337
338 ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
339
340 if (data)
341 bounce_buffer_stop(&bbstate);
342
343 return ret;
344 }
345
346 static void mmc_change_clock(struct mmc_host *host, uint clock)
347 {
348 int div;
349 unsigned short clk;
350 unsigned long timeout;
351
352 debug(" mmc_change_clock called\n");
353
354 /*
355 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
356 */
357 if (clock == 0)
358 goto out;
359 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
360 &div);
361 debug("div = %d\n", div);
362
363 writew(0, &host->reg->clkcon);
364
365 /*
366 * CLKCON
367 * SELFREQ[15:8] : base clock divided by value
368 * ENSDCLK[2] : SD Clock Enable
369 * STBLINTCLK[1] : Internal Clock Stable
370 * ENINTCLK[0] : Internal Clock Enable
371 */
372 div >>= 1;
373 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
374 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
375 writew(clk, &host->reg->clkcon);
376
377 /* Wait max 10 ms */
378 timeout = 10;
379 while (!(readw(&host->reg->clkcon) &
380 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
381 if (timeout == 0) {
382 printf("%s: timeout error\n", __func__);
383 return;
384 }
385 timeout--;
386 udelay(1000);
387 }
388
389 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
390 writew(clk, &host->reg->clkcon);
391
392 debug("mmc_change_clock: clkcon = %08X\n", clk);
393
394 out:
395 host->clock = clock;
396 }
397
398 static void tegra_mmc_set_ios(struct mmc *mmc)
399 {
400 struct mmc_host *host = mmc->priv;
401 unsigned char ctrl;
402 debug(" mmc_set_ios called\n");
403
404 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
405
406 /* Change clock first */
407 mmc_change_clock(host, mmc->clock);
408
409 ctrl = readb(&host->reg->hostctl);
410
411 /*
412 * WIDE8[5]
413 * 0 = Depend on WIDE4
414 * 1 = 8-bit mode
415 * WIDE4[1]
416 * 1 = 4-bit mode
417 * 0 = 1-bit mode
418 */
419 if (mmc->bus_width == 8)
420 ctrl |= (1 << 5);
421 else if (mmc->bus_width == 4)
422 ctrl |= (1 << 1);
423 else
424 ctrl &= ~(1 << 1);
425
426 writeb(ctrl, &host->reg->hostctl);
427 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
428 }
429
430 static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
431 {
432 unsigned int timeout;
433 debug(" mmc_reset called\n");
434
435 /*
436 * RSTALL[0] : Software reset for all
437 * 1 = reset
438 * 0 = work
439 */
440 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
441
442 host->clock = 0;
443
444 /* Wait max 100 ms */
445 timeout = 100;
446
447 /* hw clears the bit when it's done */
448 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
449 if (timeout == 0) {
450 printf("%s: timeout error\n", __func__);
451 return;
452 }
453 timeout--;
454 udelay(1000);
455 }
456
457 /* Set SD bus voltage & enable bus power */
458 mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
459 debug("%s: power control = %02X, host control = %02X\n", __func__,
460 readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
461
462 /* Make sure SDIO pads are set up */
463 pad_init_mmc(host);
464 }
465
466 static int tegra_mmc_core_init(struct mmc *mmc)
467 {
468 struct mmc_host *host = mmc->priv;
469 unsigned int mask;
470 debug(" mmc_core_init called\n");
471
472 mmc_reset(host, mmc);
473
474 host->version = readw(&host->reg->hcver);
475 debug("host version = %x\n", host->version);
476
477 /* mask all */
478 writel(0xffffffff, &host->reg->norintstsen);
479 writel(0xffffffff, &host->reg->norintsigen);
480
481 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
482 /*
483 * NORMAL Interrupt Status Enable Register init
484 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
485 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
486 * [3] ENSTADMAINT : DMA boundary interrupt
487 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
488 * [0] ENSTACMDCMPLT : Command Complete Status Enable
489 */
490 mask = readl(&host->reg->norintstsen);
491 mask &= ~(0xffff);
492 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
493 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
494 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
495 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
496 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
497 writel(mask, &host->reg->norintstsen);
498
499 /*
500 * NORMAL Interrupt Signal Enable Register init
501 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
502 */
503 mask = readl(&host->reg->norintsigen);
504 mask &= ~(0xffff);
505 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
506 writel(mask, &host->reg->norintsigen);
507
508 return 0;
509 }
510
511 int tegra_mmc_getcd(struct mmc *mmc)
512 {
513 struct mmc_host *host = mmc->priv;
514
515 debug("tegra_mmc_getcd called\n");
516
517 if (fdt_gpio_isvalid(&host->cd_gpio))
518 return fdtdec_get_gpio(&host->cd_gpio);
519
520 return 1;
521 }
522
523 static const struct mmc_ops tegra_mmc_ops = {
524 .send_cmd = tegra_mmc_send_cmd,
525 .set_ios = tegra_mmc_set_ios,
526 .init = tegra_mmc_core_init,
527 .getcd = tegra_mmc_getcd,
528 };
529
530 static int do_mmc_init(int dev_index)
531 {
532 struct mmc_host *host;
533 char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
534 struct mmc *mmc;
535
536 /* DT should have been read & host config filled in */
537 host = &mmc_host[dev_index];
538 if (!host->enabled)
539 return -1;
540
541 debug(" do_mmc_init: index %d, bus width %d "
542 "pwr_gpio %d cd_gpio %d\n",
543 dev_index, host->width,
544 host->pwr_gpio.gpio, host->cd_gpio.gpio);
545
546 host->clock = 0;
547 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
548
549 if (fdt_gpio_isvalid(&host->pwr_gpio)) {
550 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
551 gpio_request(host->pwr_gpio.gpio, gpusage);
552 gpio_direction_output(host->pwr_gpio.gpio, 1);
553 debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
554 }
555
556 if (fdt_gpio_isvalid(&host->cd_gpio)) {
557 sprintf(gpusage, "SD/MMC%d CD", dev_index);
558 gpio_request(host->cd_gpio.gpio, gpusage);
559 gpio_direction_input(host->cd_gpio.gpio);
560 debug(" CD GPIO name = %s\n", host->cd_gpio.name);
561 }
562
563 memset(&host->cfg, 0, sizeof(host->cfg));
564
565 host->cfg.name = "Tegra SD/MMC";
566 host->cfg.ops = &tegra_mmc_ops;
567
568 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
569 host->cfg.host_caps = 0;
570 if (host->width == 8)
571 host->cfg.host_caps |= MMC_MODE_8BIT;
572 if (host->width >= 4)
573 host->cfg.host_caps |= MMC_MODE_4BIT;
574 host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
575
576 /*
577 * min freq is for card identification, and is the highest
578 * low-speed SDIO card frequency (actually 400KHz)
579 * max freq is highest HS eMMC clock as per the SD/MMC spec
580 * (actually 52MHz)
581 */
582 host->cfg.f_min = 375000;
583 host->cfg.f_max = 48000000;
584
585 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
586
587 mmc = mmc_create(&host->cfg, host);
588 if (mmc == NULL)
589 return -1;
590
591 return 0;
592 }
593
594 /**
595 * Get the host address and peripheral ID for a node.
596 *
597 * @param blob fdt blob
598 * @param node Device index (0-3)
599 * @param host Structure to fill in (reg, width, mmc_id)
600 */
601 static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
602 {
603 debug("%s: node = %d\n", __func__, node);
604
605 host->enabled = fdtdec_get_is_enabled(blob, node);
606
607 host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
608 if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
609 debug("%s: no sdmmc base reg info found\n", __func__);
610 return -FDT_ERR_NOTFOUND;
611 }
612
613 host->mmc_id = clock_decode_periph_id(blob, node);
614 if (host->mmc_id == PERIPH_ID_NONE) {
615 debug("%s: could not decode periph id\n", __func__);
616 return -FDT_ERR_NOTFOUND;
617 }
618
619 /*
620 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
621 * TBD: Override it with this value?
622 */
623 host->width = fdtdec_get_int(blob, node, "bus-width", 0);
624 if (!host->width)
625 debug("%s: no sdmmc width found\n", __func__);
626
627 /* These GPIOs are optional */
628 fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
629 fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
630 fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
631
632 debug("%s: found controller at %p, width = %d, periph_id = %d\n",
633 __func__, host->reg, host->width, host->mmc_id);
634 return 0;
635 }
636
637 /*
638 * Process a list of nodes, adding them to our list of SDMMC ports.
639 *
640 * @param blob fdt blob
641 * @param node_list list of nodes to process (any <=0 are ignored)
642 * @param count number of nodes to process
643 * @return 0 if ok, -1 on error
644 */
645 static int process_nodes(const void *blob, int node_list[], int count)
646 {
647 struct mmc_host *host;
648 int i, node;
649
650 debug("%s: count = %d\n", __func__, count);
651
652 /* build mmc_host[] for each controller */
653 for (i = 0; i < count; i++) {
654 node = node_list[i];
655 if (node <= 0)
656 continue;
657
658 host = &mmc_host[i];
659 host->id = i;
660
661 if (mmc_get_config(blob, node, host)) {
662 printf("%s: failed to decode dev %d\n", __func__, i);
663 return -1;
664 }
665 do_mmc_init(i);
666 }
667 return 0;
668 }
669
670 void tegra_mmc_init(void)
671 {
672 int node_list[MAX_HOSTS], count;
673 const void *blob = gd->fdt_blob;
674 debug("%s entry\n", __func__);
675
676 /* See if any Tegra124 MMC controllers are present */
677 count = fdtdec_find_aliases_for_id(blob, "sdhci",
678 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
679 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
680 if (process_nodes(blob, node_list, count)) {
681 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
682 return;
683 }
684
685 /* See if any Tegra30 MMC controllers are present */
686 count = fdtdec_find_aliases_for_id(blob, "sdhci",
687 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
688 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
689 if (process_nodes(blob, node_list, count)) {
690 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
691 return;
692 }
693
694 /* Now look for any Tegra20 MMC controllers */
695 count = fdtdec_find_aliases_for_id(blob, "sdhci",
696 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
697 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
698 if (process_nodes(blob, node_list, count)) {
699 printf("%s: Error processing T20 mmc node(s)!\n", __func__);
700 return;
701 }
702 }
"Das U-Boot" Source Tree