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[people/ms/u-boot.git] / drivers / mtd / cfi_flash.c
1 /*
2 * (C) Copyright 2002-2004
3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 *
8 * Copyright (C) 2004
9 * Ed Okerson
10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
13 *
14 * SPDX-License-Identifier: GPL-2.0+
15 */
16
17 /* The DEBUG define must be before common to enable debugging */
18 /* #define DEBUG */
19
20 #include <common.h>
21 #include <console.h>
22 #include <dm.h>
23 #include <errno.h>
24 #include <fdt_support.h>
25 #include <asm/processor.h>
26 #include <asm/io.h>
27 #include <asm/byteorder.h>
28 #include <asm/unaligned.h>
29 #include <environment.h>
30 #include <mtd/cfi_flash.h>
31 #include <watchdog.h>
32
33 /*
34 * This file implements a Common Flash Interface (CFI) driver for
35 * U-Boot.
36 *
37 * The width of the port and the width of the chips are determined at
38 * initialization. These widths are used to calculate the address for
39 * access CFI data structures.
40 *
41 * References
42 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
43 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
44 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
45 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
46 * AMD CFI Specification, Release 2.0 December 1, 2001
47 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
48 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
49 *
50 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
51 * reading and writing ... (yes there is such a Hardware).
52 */
53
54 DECLARE_GLOBAL_DATA_PTR;
55
56 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
57 #ifdef CONFIG_FLASH_CFI_MTD
58 static uint flash_verbose = 1;
59 #else
60 #define flash_verbose 1
61 #endif
62
63 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
64
65 /*
66 * Check if chip width is defined. If not, start detecting with 8bit.
67 */
68 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH
69 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
70 #endif
71
72 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
73 #define __maybe_weak __weak
74 #else
75 #define __maybe_weak static
76 #endif
77
78 /*
79 * 0xffff is an undefined value for the configuration register. When
80 * this value is returned, the configuration register shall not be
81 * written at all (default mode).
82 */
83 static u16 cfi_flash_config_reg(int i)
84 {
85 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
87 #else
88 return 0xffff;
89 #endif
90 }
91
92 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
93 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
94 #endif
95
96 #ifdef CONFIG_CFI_FLASH /* for driver model */
97 static void cfi_flash_init_dm(void)
98 {
99 struct udevice *dev;
100
101 cfi_flash_num_flash_banks = 0;
102 /*
103 * The uclass_first_device() will probe the first device and
104 * uclass_next_device() will probe the rest if they exist. So
105 * that cfi_flash_probe() will get called assigning the base
106 * addresses that are available.
107 */
108 for (uclass_first_device(UCLASS_MTD, &dev);
109 dev;
110 uclass_next_device(&dev)) {
111 }
112 }
113
114 phys_addr_t cfi_flash_bank_addr(int i)
115 {
116 return flash_info[i].base;
117 }
118 #else
119 __weak phys_addr_t cfi_flash_bank_addr(int i)
120 {
121 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
122 }
123 #endif
124
125 __weak unsigned long cfi_flash_bank_size(int i)
126 {
127 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES
128 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
129 #else
130 return 0;
131 #endif
132 }
133
134 __maybe_weak void flash_write8(u8 value, void *addr)
135 {
136 __raw_writeb(value, addr);
137 }
138
139 __maybe_weak void flash_write16(u16 value, void *addr)
140 {
141 __raw_writew(value, addr);
142 }
143
144 __maybe_weak void flash_write32(u32 value, void *addr)
145 {
146 __raw_writel(value, addr);
147 }
148
149 __maybe_weak void flash_write64(u64 value, void *addr)
150 {
151 /* No architectures currently implement __raw_writeq() */
152 *(volatile u64 *)addr = value;
153 }
154
155 __maybe_weak u8 flash_read8(void *addr)
156 {
157 return __raw_readb(addr);
158 }
159
160 __maybe_weak u16 flash_read16(void *addr)
161 {
162 return __raw_readw(addr);
163 }
164
165 __maybe_weak u32 flash_read32(void *addr)
166 {
167 return __raw_readl(addr);
168 }
169
170 __maybe_weak u64 flash_read64(void *addr)
171 {
172 /* No architectures currently implement __raw_readq() */
173 return *(volatile u64 *)addr;
174 }
175
176 /*-----------------------------------------------------------------------
177 */
178 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
179 static flash_info_t *flash_get_info(ulong base)
180 {
181 int i;
182 flash_info_t *info;
183
184 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
185 info = &flash_info[i];
186 if (info->size && info->start[0] <= base &&
187 base <= info->start[0] + info->size - 1)
188 return info;
189 }
190
191 return NULL;
192 }
193 #endif
194
195 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
196 {
197 if (sect != (info->sector_count - 1))
198 return info->start[sect + 1] - info->start[sect];
199 else
200 return info->start[0] + info->size - info->start[sect];
201 }
202
203 /*-----------------------------------------------------------------------
204 * create an address based on the offset and the port width
205 */
206 static inline void *
207 flash_map(flash_info_t *info, flash_sect_t sect, uint offset)
208 {
209 unsigned int byte_offset = offset * info->portwidth;
210
211 return (void *)(info->start[sect] + byte_offset);
212 }
213
214 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
215 unsigned int offset, void *addr)
216 {
217 }
218
219 /*-----------------------------------------------------------------------
220 * make a proper sized command based on the port and chip widths
221 */
222 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
223 {
224 int i;
225 int cword_offset;
226 int cp_offset;
227 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
228 u32 cmd_le = cpu_to_le32(cmd);
229 #endif
230 uchar val;
231 uchar *cp = (uchar *) cmdbuf;
232
233 for (i = info->portwidth; i > 0; i--) {
234 cword_offset = (info->portwidth - i) % info->chipwidth;
235 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
236 cp_offset = info->portwidth - i;
237 val = *((uchar *)&cmd_le + cword_offset);
238 #else
239 cp_offset = i - 1;
240 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1);
241 #endif
242 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
243 }
244 }
245
246 #ifdef DEBUG
247 /*-----------------------------------------------------------------------
248 * Debug support
249 */
250 static void print_longlong(char *str, unsigned long long data)
251 {
252 int i;
253 char *cp;
254
255 cp = (char *)&data;
256 for (i = 0; i < 8; i++)
257 sprintf(&str[i * 2], "%2.2x", *cp++);
258 }
259
260 static void flash_printqry(struct cfi_qry *qry)
261 {
262 u8 *p = (u8 *)qry;
263 int x, y;
264
265 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
266 debug("%02x : ", x);
267 for (y = 0; y < 16; y++)
268 debug("%2.2x ", p[x + y]);
269 debug(" ");
270 for (y = 0; y < 16; y++) {
271 unsigned char c = p[x + y];
272
273 if (c >= 0x20 && c <= 0x7e)
274 debug("%c", c);
275 else
276 debug(".");
277 }
278 debug("\n");
279 }
280 }
281 #endif
282
283 /*-----------------------------------------------------------------------
284 * read a character at a port width address
285 */
286 static inline uchar flash_read_uchar(flash_info_t *info, uint offset)
287 {
288 uchar *cp;
289 uchar retval;
290
291 cp = flash_map(info, 0, offset);
292 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
293 retval = flash_read8(cp);
294 #else
295 retval = flash_read8(cp + info->portwidth - 1);
296 #endif
297 flash_unmap(info, 0, offset, cp);
298 return retval;
299 }
300
301 /*-----------------------------------------------------------------------
302 * read a word at a port width address, assume 16bit bus
303 */
304 static inline ushort flash_read_word(flash_info_t *info, uint offset)
305 {
306 ushort *addr, retval;
307
308 addr = flash_map(info, 0, offset);
309 retval = flash_read16(addr);
310 flash_unmap(info, 0, offset, addr);
311 return retval;
312 }
313
314 /*-----------------------------------------------------------------------
315 * read a long word by picking the least significant byte of each maximum
316 * port size word. Swap for ppc format.
317 */
318 static ulong flash_read_long (flash_info_t *info, flash_sect_t sect,
319 uint offset)
320 {
321 uchar *addr;
322 ulong retval;
323
324 #ifdef DEBUG
325 int x;
326 #endif
327 addr = flash_map(info, sect, offset);
328
329 #ifdef DEBUG
330 debug("long addr is at %p info->portwidth = %d\n", addr,
331 info->portwidth);
332 for (x = 0; x < 4 * info->portwidth; x++)
333 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
334 #endif
335 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
336 retval = ((flash_read8(addr) << 16) |
337 (flash_read8(addr + info->portwidth) << 24) |
338 (flash_read8(addr + 2 * info->portwidth)) |
339 (flash_read8(addr + 3 * info->portwidth) << 8));
340 #else
341 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
342 (flash_read8(addr + info->portwidth - 1) << 16) |
343 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
344 (flash_read8(addr + 3 * info->portwidth - 1)));
345 #endif
346 flash_unmap(info, sect, offset, addr);
347
348 return retval;
349 }
350
351 /*
352 * Write a proper sized command to the correct address
353 */
354 static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
355 uint offset, u32 cmd)
356 {
357 void *addr;
358 cfiword_t cword;
359
360 addr = flash_map(info, sect, offset);
361 flash_make_cmd(info, cmd, &cword);
362 switch (info->portwidth) {
363 case FLASH_CFI_8BIT:
364 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
365 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
366 flash_write8(cword.w8, addr);
367 break;
368 case FLASH_CFI_16BIT:
369 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
370 cmd, cword.w16,
371 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
372 flash_write16(cword.w16, addr);
373 break;
374 case FLASH_CFI_32BIT:
375 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
376 cmd, cword.w32,
377 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
378 flash_write32(cword.w32, addr);
379 break;
380 case FLASH_CFI_64BIT:
381 #ifdef DEBUG
382 {
383 char str[20];
384
385 print_longlong(str, cword.w64);
386
387 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
388 addr, cmd, str,
389 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
390 }
391 #endif
392 flash_write64(cword.w64, addr);
393 break;
394 }
395
396 /* Ensure all the instructions are fully finished */
397 sync();
398
399 flash_unmap(info, sect, offset, addr);
400 }
401
402 static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect)
403 {
404 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
405 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
406 }
407
408 /*-----------------------------------------------------------------------
409 */
410 static int flash_isequal(flash_info_t *info, flash_sect_t sect,
411 uint offset, uchar cmd)
412 {
413 void *addr;
414 cfiword_t cword;
415 int retval;
416
417 addr = flash_map(info, sect, offset);
418 flash_make_cmd(info, cmd, &cword);
419
420 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
421 switch (info->portwidth) {
422 case FLASH_CFI_8BIT:
423 debug("is= %x %x\n", flash_read8(addr), cword.w8);
424 retval = (flash_read8(addr) == cword.w8);
425 break;
426 case FLASH_CFI_16BIT:
427 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
428 retval = (flash_read16(addr) == cword.w16);
429 break;
430 case FLASH_CFI_32BIT:
431 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
432 retval = (flash_read32(addr) == cword.w32);
433 break;
434 case FLASH_CFI_64BIT:
435 #ifdef DEBUG
436 {
437 char str1[20];
438 char str2[20];
439
440 print_longlong(str1, flash_read64(addr));
441 print_longlong(str2, cword.w64);
442 debug("is= %s %s\n", str1, str2);
443 }
444 #endif
445 retval = (flash_read64(addr) == cword.w64);
446 break;
447 default:
448 retval = 0;
449 break;
450 }
451 flash_unmap(info, sect, offset, addr);
452
453 return retval;
454 }
455
456 /*-----------------------------------------------------------------------
457 */
458 static int flash_isset(flash_info_t *info, flash_sect_t sect,
459 uint offset, uchar cmd)
460 {
461 void *addr;
462 cfiword_t cword;
463 int retval;
464
465 addr = flash_map(info, sect, offset);
466 flash_make_cmd(info, cmd, &cword);
467 switch (info->portwidth) {
468 case FLASH_CFI_8BIT:
469 retval = ((flash_read8(addr) & cword.w8) == cword.w8);
470 break;
471 case FLASH_CFI_16BIT:
472 retval = ((flash_read16(addr) & cword.w16) == cword.w16);
473 break;
474 case FLASH_CFI_32BIT:
475 retval = ((flash_read32(addr) & cword.w32) == cword.w32);
476 break;
477 case FLASH_CFI_64BIT:
478 retval = ((flash_read64(addr) & cword.w64) == cword.w64);
479 break;
480 default:
481 retval = 0;
482 break;
483 }
484 flash_unmap(info, sect, offset, addr);
485
486 return retval;
487 }
488
489 /*-----------------------------------------------------------------------
490 */
491 static int flash_toggle(flash_info_t *info, flash_sect_t sect,
492 uint offset, uchar cmd)
493 {
494 void *addr;
495 cfiword_t cword;
496 int retval;
497
498 addr = flash_map(info, sect, offset);
499 flash_make_cmd(info, cmd, &cword);
500 switch (info->portwidth) {
501 case FLASH_CFI_8BIT:
502 retval = flash_read8(addr) != flash_read8(addr);
503 break;
504 case FLASH_CFI_16BIT:
505 retval = flash_read16(addr) != flash_read16(addr);
506 break;
507 case FLASH_CFI_32BIT:
508 retval = flash_read32(addr) != flash_read32(addr);
509 break;
510 case FLASH_CFI_64BIT:
511 retval = ((flash_read32(addr) != flash_read32(addr)) ||
512 (flash_read32(addr + 4) != flash_read32(addr + 4)));
513 break;
514 default:
515 retval = 0;
516 break;
517 }
518 flash_unmap(info, sect, offset, addr);
519
520 return retval;
521 }
522
523 /*
524 * flash_is_busy - check to see if the flash is busy
525 *
526 * This routine checks the status of the chip and returns true if the
527 * chip is busy.
528 */
529 static int flash_is_busy(flash_info_t *info, flash_sect_t sect)
530 {
531 int retval;
532
533 switch (info->vendor) {
534 case CFI_CMDSET_INTEL_PROG_REGIONS:
535 case CFI_CMDSET_INTEL_STANDARD:
536 case CFI_CMDSET_INTEL_EXTENDED:
537 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
538 break;
539 case CFI_CMDSET_AMD_STANDARD:
540 case CFI_CMDSET_AMD_EXTENDED:
541 #ifdef CONFIG_FLASH_CFI_LEGACY
542 case CFI_CMDSET_AMD_LEGACY:
543 #endif
544 if (info->sr_supported) {
545 flash_write_cmd(info, sect, info->addr_unlock1,
546 FLASH_CMD_READ_STATUS);
547 retval = !flash_isset(info, sect, 0,
548 FLASH_STATUS_DONE);
549 } else {
550 retval = flash_toggle(info, sect, 0,
551 AMD_STATUS_TOGGLE);
552 }
553
554 break;
555 default:
556 retval = 0;
557 }
558 debug("%s: %d\n", __func__, retval);
559 return retval;
560 }
561
562 /*-----------------------------------------------------------------------
563 * wait for XSR.7 to be set. Time out with an error if it does not.
564 * This routine does not set the flash to read-array mode.
565 */
566 static int flash_status_check(flash_info_t *info, flash_sect_t sector,
567 ulong tout, char *prompt)
568 {
569 ulong start;
570
571 #if CONFIG_SYS_HZ != 1000
572 if ((ulong)CONFIG_SYS_HZ > 100000)
573 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
574 else
575 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
576 #endif
577
578 /* Wait for command completion */
579 #ifdef CONFIG_SYS_LOW_RES_TIMER
580 reset_timer();
581 #endif
582 start = get_timer(0);
583 WATCHDOG_RESET();
584 while (flash_is_busy(info, sector)) {
585 if (get_timer(start) > tout) {
586 printf("Flash %s timeout at address %lx data %lx\n",
587 prompt, info->start[sector],
588 flash_read_long(info, sector, 0));
589 flash_write_cmd(info, sector, 0, info->cmd_reset);
590 udelay(1);
591 return ERR_TIMOUT;
592 }
593 udelay(1); /* also triggers watchdog */
594 }
595 return ERR_OK;
596 }
597
598 /*-----------------------------------------------------------------------
599 * Wait for XSR.7 to be set, if it times out print an error, otherwise
600 * do a full status check.
601 *
602 * This routine sets the flash to read-array mode.
603 */
604 static int flash_full_status_check(flash_info_t *info, flash_sect_t sector,
605 ulong tout, char *prompt)
606 {
607 int retcode;
608
609 retcode = flash_status_check(info, sector, tout, prompt);
610 switch (info->vendor) {
611 case CFI_CMDSET_INTEL_PROG_REGIONS:
612 case CFI_CMDSET_INTEL_EXTENDED:
613 case CFI_CMDSET_INTEL_STANDARD:
614 if (retcode == ERR_OK &&
615 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
616 retcode = ERR_INVAL;
617 printf("Flash %s error at address %lx\n", prompt,
618 info->start[sector]);
619 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS |
620 FLASH_STATUS_PSLBS)) {
621 puts("Command Sequence Error.\n");
622 } else if (flash_isset(info, sector, 0,
623 FLASH_STATUS_ECLBS)) {
624 puts("Block Erase Error.\n");
625 retcode = ERR_NOT_ERASED;
626 } else if (flash_isset(info, sector, 0,
627 FLASH_STATUS_PSLBS)) {
628 puts("Locking Error\n");
629 }
630 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
631 puts("Block locked.\n");
632 retcode = ERR_PROTECTED;
633 }
634 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
635 puts("Vpp Low Error.\n");
636 }
637 flash_write_cmd(info, sector, 0, info->cmd_reset);
638 udelay(1);
639 break;
640 default:
641 break;
642 }
643 return retcode;
644 }
645
646 static int use_flash_status_poll(flash_info_t *info)
647 {
648 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
649 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
650 info->vendor == CFI_CMDSET_AMD_STANDARD)
651 return 1;
652 #endif
653 return 0;
654 }
655
656 static int flash_status_poll(flash_info_t *info, void *src, void *dst,
657 ulong tout, char *prompt)
658 {
659 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
660 ulong start;
661 int ready;
662
663 #if CONFIG_SYS_HZ != 1000
664 if ((ulong)CONFIG_SYS_HZ > 100000)
665 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
666 else
667 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
668 #endif
669
670 /* Wait for command completion */
671 #ifdef CONFIG_SYS_LOW_RES_TIMER
672 reset_timer();
673 #endif
674 start = get_timer(0);
675 WATCHDOG_RESET();
676 while (1) {
677 switch (info->portwidth) {
678 case FLASH_CFI_8BIT:
679 ready = flash_read8(dst) == flash_read8(src);
680 break;
681 case FLASH_CFI_16BIT:
682 ready = flash_read16(dst) == flash_read16(src);
683 break;
684 case FLASH_CFI_32BIT:
685 ready = flash_read32(dst) == flash_read32(src);
686 break;
687 case FLASH_CFI_64BIT:
688 ready = flash_read64(dst) == flash_read64(src);
689 break;
690 default:
691 ready = 0;
692 break;
693 }
694 if (ready)
695 break;
696 if (get_timer(start) > tout) {
697 printf("Flash %s timeout at address %lx data %lx\n",
698 prompt, (ulong)dst, (ulong)flash_read8(dst));
699 return ERR_TIMOUT;
700 }
701 udelay(1); /* also triggers watchdog */
702 }
703 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
704 return ERR_OK;
705 }
706
707 /*-----------------------------------------------------------------------
708 */
709 static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
710 {
711 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
712 unsigned short w;
713 unsigned int l;
714 unsigned long long ll;
715 #endif
716
717 switch (info->portwidth) {
718 case FLASH_CFI_8BIT:
719 cword->w8 = c;
720 break;
721 case FLASH_CFI_16BIT:
722 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
723 w = c;
724 w <<= 8;
725 cword->w16 = (cword->w16 >> 8) | w;
726 #else
727 cword->w16 = (cword->w16 << 8) | c;
728 #endif
729 break;
730 case FLASH_CFI_32BIT:
731 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
732 l = c;
733 l <<= 24;
734 cword->w32 = (cword->w32 >> 8) | l;
735 #else
736 cword->w32 = (cword->w32 << 8) | c;
737 #endif
738 break;
739 case FLASH_CFI_64BIT:
740 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
741 ll = c;
742 ll <<= 56;
743 cword->w64 = (cword->w64 >> 8) | ll;
744 #else
745 cword->w64 = (cword->w64 << 8) | c;
746 #endif
747 break;
748 }
749 }
750
751 /*
752 * Loop through the sector table starting from the previously found sector.
753 * Searches forwards or backwards, dependent on the passed address.
754 */
755 static flash_sect_t find_sector(flash_info_t *info, ulong addr)
756 {
757 static flash_sect_t saved_sector; /* previously found sector */
758 static flash_info_t *saved_info; /* previously used flash bank */
759 flash_sect_t sector = saved_sector;
760
761 if (info != saved_info || sector >= info->sector_count)
762 sector = 0;
763
764 while ((info->start[sector] < addr) &&
765 (sector < info->sector_count - 1))
766 sector++;
767 while ((info->start[sector] > addr) && (sector > 0))
768 /*
769 * also decrements the sector in case of an overshot
770 * in the first loop
771 */
772 sector--;
773
774 saved_sector = sector;
775 saved_info = info;
776 return sector;
777 }
778
779 /*-----------------------------------------------------------------------
780 */
781 static int flash_write_cfiword(flash_info_t *info, ulong dest,
782 cfiword_t cword)
783 {
784 void *dstaddr = (void *)dest;
785 int flag;
786 flash_sect_t sect = 0;
787 char sect_found = 0;
788
789 /* Check if Flash is (sufficiently) erased */
790 switch (info->portwidth) {
791 case FLASH_CFI_8BIT:
792 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8);
793 break;
794 case FLASH_CFI_16BIT:
795 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16);
796 break;
797 case FLASH_CFI_32BIT:
798 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32);
799 break;
800 case FLASH_CFI_64BIT:
801 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64);
802 break;
803 default:
804 flag = 0;
805 break;
806 }
807 if (!flag)
808 return ERR_NOT_ERASED;
809
810 /* Disable interrupts which might cause a timeout here */
811 flag = disable_interrupts();
812
813 switch (info->vendor) {
814 case CFI_CMDSET_INTEL_PROG_REGIONS:
815 case CFI_CMDSET_INTEL_EXTENDED:
816 case CFI_CMDSET_INTEL_STANDARD:
817 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
818 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
819 break;
820 case CFI_CMDSET_AMD_EXTENDED:
821 case CFI_CMDSET_AMD_STANDARD:
822 sect = find_sector(info, dest);
823 flash_unlock_seq(info, sect);
824 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE);
825 sect_found = 1;
826 break;
827 #ifdef CONFIG_FLASH_CFI_LEGACY
828 case CFI_CMDSET_AMD_LEGACY:
829 sect = find_sector(info, dest);
830 flash_unlock_seq(info, 0);
831 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE);
832 sect_found = 1;
833 break;
834 #endif
835 }
836
837 switch (info->portwidth) {
838 case FLASH_CFI_8BIT:
839 flash_write8(cword.w8, dstaddr);
840 break;
841 case FLASH_CFI_16BIT:
842 flash_write16(cword.w16, dstaddr);
843 break;
844 case FLASH_CFI_32BIT:
845 flash_write32(cword.w32, dstaddr);
846 break;
847 case FLASH_CFI_64BIT:
848 flash_write64(cword.w64, dstaddr);
849 break;
850 }
851
852 /* re-enable interrupts if necessary */
853 if (flag)
854 enable_interrupts();
855
856 if (!sect_found)
857 sect = find_sector(info, dest);
858
859 if (use_flash_status_poll(info))
860 return flash_status_poll(info, &cword, dstaddr,
861 info->write_tout, "write");
862 else
863 return flash_full_status_check(info, sect,
864 info->write_tout, "write");
865 }
866
867 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
868
869 static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp,
870 int len)
871 {
872 flash_sect_t sector;
873 int cnt;
874 int retcode;
875 void *src = cp;
876 void *dst = (void *)dest;
877 void *dst2 = dst;
878 int flag = 1;
879 uint offset = 0;
880 unsigned int shift;
881 uchar write_cmd;
882
883 switch (info->portwidth) {
884 case FLASH_CFI_8BIT:
885 shift = 0;
886 break;
887 case FLASH_CFI_16BIT:
888 shift = 1;
889 break;
890 case FLASH_CFI_32BIT:
891 shift = 2;
892 break;
893 case FLASH_CFI_64BIT:
894 shift = 3;
895 break;
896 default:
897 retcode = ERR_INVAL;
898 goto out_unmap;
899 }
900
901 cnt = len >> shift;
902
903 while ((cnt-- > 0) && (flag == 1)) {
904 switch (info->portwidth) {
905 case FLASH_CFI_8BIT:
906 flag = ((flash_read8(dst2) & flash_read8(src)) ==
907 flash_read8(src));
908 src += 1, dst2 += 1;
909 break;
910 case FLASH_CFI_16BIT:
911 flag = ((flash_read16(dst2) & flash_read16(src)) ==
912 flash_read16(src));
913 src += 2, dst2 += 2;
914 break;
915 case FLASH_CFI_32BIT:
916 flag = ((flash_read32(dst2) & flash_read32(src)) ==
917 flash_read32(src));
918 src += 4, dst2 += 4;
919 break;
920 case FLASH_CFI_64BIT:
921 flag = ((flash_read64(dst2) & flash_read64(src)) ==
922 flash_read64(src));
923 src += 8, dst2 += 8;
924 break;
925 }
926 }
927 if (!flag) {
928 retcode = ERR_NOT_ERASED;
929 goto out_unmap;
930 }
931
932 src = cp;
933 sector = find_sector(info, dest);
934
935 switch (info->vendor) {
936 case CFI_CMDSET_INTEL_PROG_REGIONS:
937 case CFI_CMDSET_INTEL_STANDARD:
938 case CFI_CMDSET_INTEL_EXTENDED:
939 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
940 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
941 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
942 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
943 flash_write_cmd(info, sector, 0, write_cmd);
944 retcode = flash_status_check(info, sector,
945 info->buffer_write_tout,
946 "write to buffer");
947 if (retcode == ERR_OK) {
948 /* reduce the number of loops by the width of
949 * the port
950 */
951 cnt = len >> shift;
952 flash_write_cmd(info, sector, 0, cnt - 1);
953 while (cnt-- > 0) {
954 switch (info->portwidth) {
955 case FLASH_CFI_8BIT:
956 flash_write8(flash_read8(src), dst);
957 src += 1, dst += 1;
958 break;
959 case FLASH_CFI_16BIT:
960 flash_write16(flash_read16(src), dst);
961 src += 2, dst += 2;
962 break;
963 case FLASH_CFI_32BIT:
964 flash_write32(flash_read32(src), dst);
965 src += 4, dst += 4;
966 break;
967 case FLASH_CFI_64BIT:
968 flash_write64(flash_read64(src), dst);
969 src += 8, dst += 8;
970 break;
971 default:
972 retcode = ERR_INVAL;
973 goto out_unmap;
974 }
975 }
976 flash_write_cmd(info, sector, 0,
977 FLASH_CMD_WRITE_BUFFER_CONFIRM);
978 retcode = flash_full_status_check(
979 info, sector, info->buffer_write_tout,
980 "buffer write");
981 }
982
983 break;
984
985 case CFI_CMDSET_AMD_STANDARD:
986 case CFI_CMDSET_AMD_EXTENDED:
987 flash_unlock_seq(info, sector);
988
989 #ifdef CONFIG_FLASH_SPANSION_S29WS_N
990 offset = ((unsigned long)dst - info->start[sector]) >> shift;
991 #endif
992 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
993 cnt = len >> shift;
994 flash_write_cmd(info, sector, offset, cnt - 1);
995
996 switch (info->portwidth) {
997 case FLASH_CFI_8BIT:
998 while (cnt-- > 0) {
999 flash_write8(flash_read8(src), dst);
1000 src += 1, dst += 1;
1001 }
1002 break;
1003 case FLASH_CFI_16BIT:
1004 while (cnt-- > 0) {
1005 flash_write16(flash_read16(src), dst);
1006 src += 2, dst += 2;
1007 }
1008 break;
1009 case FLASH_CFI_32BIT:
1010 while (cnt-- > 0) {
1011 flash_write32(flash_read32(src), dst);
1012 src += 4, dst += 4;
1013 }
1014 break;
1015 case FLASH_CFI_64BIT:
1016 while (cnt-- > 0) {
1017 flash_write64(flash_read64(src), dst);
1018 src += 8, dst += 8;
1019 }
1020 break;
1021 default:
1022 retcode = ERR_INVAL;
1023 goto out_unmap;
1024 }
1025
1026 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
1027 if (use_flash_status_poll(info))
1028 retcode = flash_status_poll(info, src - (1 << shift),
1029 dst - (1 << shift),
1030 info->buffer_write_tout,
1031 "buffer write");
1032 else
1033 retcode = flash_full_status_check(info, sector,
1034 info->buffer_write_tout,
1035 "buffer write");
1036 break;
1037
1038 default:
1039 debug("Unknown Command Set\n");
1040 retcode = ERR_INVAL;
1041 break;
1042 }
1043
1044 out_unmap:
1045 return retcode;
1046 }
1047 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
1048
1049 /*-----------------------------------------------------------------------
1050 */
1051 int flash_erase(flash_info_t *info, int s_first, int s_last)
1052 {
1053 int rcode = 0;
1054 int prot;
1055 flash_sect_t sect;
1056 int st;
1057
1058 if (info->flash_id != FLASH_MAN_CFI) {
1059 puts("Can't erase unknown flash type - aborted\n");
1060 return 1;
1061 }
1062 if (s_first < 0 || s_first > s_last) {
1063 puts("- no sectors to erase\n");
1064 return 1;
1065 }
1066
1067 prot = 0;
1068 for (sect = s_first; sect <= s_last; ++sect)
1069 if (info->protect[sect])
1070 prot++;
1071 if (prot) {
1072 printf("- Warning: %d protected sectors will not be erased!\n",
1073 prot);
1074 } else if (flash_verbose) {
1075 putc('\n');
1076 }
1077
1078 for (sect = s_first; sect <= s_last; sect++) {
1079 if (ctrlc()) {
1080 printf("\n");
1081 return 1;
1082 }
1083
1084 if (info->protect[sect] == 0) { /* not protected */
1085 #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
1086 int k;
1087 int size;
1088 int erased;
1089 u32 *flash;
1090
1091 /*
1092 * Check if whole sector is erased
1093 */
1094 size = flash_sector_size(info, sect);
1095 erased = 1;
1096 flash = (u32 *)info->start[sect];
1097 /* divide by 4 for longword access */
1098 size = size >> 2;
1099 for (k = 0; k < size; k++) {
1100 if (flash_read32(flash++) != 0xffffffff) {
1101 erased = 0;
1102 break;
1103 }
1104 }
1105 if (erased) {
1106 if (flash_verbose)
1107 putc(',');
1108 continue;
1109 }
1110 #endif
1111 switch (info->vendor) {
1112 case CFI_CMDSET_INTEL_PROG_REGIONS:
1113 case CFI_CMDSET_INTEL_STANDARD:
1114 case CFI_CMDSET_INTEL_EXTENDED:
1115 flash_write_cmd(info, sect, 0,
1116 FLASH_CMD_CLEAR_STATUS);
1117 flash_write_cmd(info, sect, 0,
1118 FLASH_CMD_BLOCK_ERASE);
1119 flash_write_cmd(info, sect, 0,
1120 FLASH_CMD_ERASE_CONFIRM);
1121 break;
1122 case CFI_CMDSET_AMD_STANDARD:
1123 case CFI_CMDSET_AMD_EXTENDED:
1124 flash_unlock_seq(info, sect);
1125 flash_write_cmd(info, sect,
1126 info->addr_unlock1,
1127 AMD_CMD_ERASE_START);
1128 flash_unlock_seq(info, sect);
1129 flash_write_cmd(info, sect, 0,
1130 info->cmd_erase_sector);
1131 break;
1132 #ifdef CONFIG_FLASH_CFI_LEGACY
1133 case CFI_CMDSET_AMD_LEGACY:
1134 flash_unlock_seq(info, 0);
1135 flash_write_cmd(info, 0, info->addr_unlock1,
1136 AMD_CMD_ERASE_START);
1137 flash_unlock_seq(info, 0);
1138 flash_write_cmd(info, sect, 0,
1139 AMD_CMD_ERASE_SECTOR);
1140 break;
1141 #endif
1142 default:
1143 debug("Unknown flash vendor %d\n",
1144 info->vendor);
1145 break;
1146 }
1147
1148 if (use_flash_status_poll(info)) {
1149 cfiword_t cword;
1150 void *dest;
1151
1152 cword.w64 = 0xffffffffffffffffULL;
1153 dest = flash_map(info, sect, 0);
1154 st = flash_status_poll(info, &cword, dest,
1155 info->erase_blk_tout, "erase");
1156 flash_unmap(info, sect, 0, dest);
1157 } else {
1158 st = flash_full_status_check(info, sect,
1159 info->erase_blk_tout,
1160 "erase");
1161 }
1162
1163 if (st)
1164 rcode = 1;
1165 else if (flash_verbose)
1166 putc('.');
1167 }
1168 }
1169
1170 if (flash_verbose)
1171 puts(" done\n");
1172
1173 return rcode;
1174 }
1175
1176 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1177 static int sector_erased(flash_info_t *info, int i)
1178 {
1179 int k;
1180 int size;
1181 u32 *flash;
1182
1183 /*
1184 * Check if whole sector is erased
1185 */
1186 size = flash_sector_size(info, i);
1187 flash = (u32 *)info->start[i];
1188 /* divide by 4 for longword access */
1189 size = size >> 2;
1190
1191 for (k = 0; k < size; k++) {
1192 if (flash_read32(flash++) != 0xffffffff)
1193 return 0; /* not erased */
1194 }
1195
1196 return 1; /* erased */
1197 }
1198 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1199
1200 void flash_print_info(flash_info_t *info)
1201 {
1202 int i;
1203
1204 if (info->flash_id != FLASH_MAN_CFI) {
1205 puts("missing or unknown FLASH type\n");
1206 return;
1207 }
1208
1209 printf("%s flash (%d x %d)",
1210 info->name,
1211 (info->portwidth << 3), (info->chipwidth << 3));
1212 if (info->size < 1024 * 1024)
1213 printf(" Size: %ld kB in %d Sectors\n",
1214 info->size >> 10, info->sector_count);
1215 else
1216 printf(" Size: %ld MB in %d Sectors\n",
1217 info->size >> 20, info->sector_count);
1218 printf(" ");
1219 switch (info->vendor) {
1220 case CFI_CMDSET_INTEL_PROG_REGIONS:
1221 printf("Intel Prog Regions");
1222 break;
1223 case CFI_CMDSET_INTEL_STANDARD:
1224 printf("Intel Standard");
1225 break;
1226 case CFI_CMDSET_INTEL_EXTENDED:
1227 printf("Intel Extended");
1228 break;
1229 case CFI_CMDSET_AMD_STANDARD:
1230 printf("AMD Standard");
1231 break;
1232 case CFI_CMDSET_AMD_EXTENDED:
1233 printf("AMD Extended");
1234 break;
1235 #ifdef CONFIG_FLASH_CFI_LEGACY
1236 case CFI_CMDSET_AMD_LEGACY:
1237 printf("AMD Legacy");
1238 break;
1239 #endif
1240 default:
1241 printf("Unknown (%d)", info->vendor);
1242 break;
1243 }
1244 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
1245 info->manufacturer_id);
1246 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1247 info->device_id);
1248 if ((info->device_id & 0xff) == 0x7E) {
1249 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1250 info->device_id2);
1251 }
1252 if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock)
1253 printf("\n Advanced Sector Protection (PPB) enabled");
1254 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1255 info->erase_blk_tout,
1256 info->write_tout);
1257 if (info->buffer_size > 1) {
1258 printf(" Buffer write timeout: %ld ms, "
1259 "buffer size: %d bytes\n",
1260 info->buffer_write_tout,
1261 info->buffer_size);
1262 }
1263
1264 puts("\n Sector Start Addresses:");
1265 for (i = 0; i < info->sector_count; ++i) {
1266 if (ctrlc())
1267 break;
1268 if ((i % 5) == 0)
1269 putc('\n');
1270 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1271 /* print empty and read-only info */
1272 printf(" %08lX %c %s ",
1273 info->start[i],
1274 sector_erased(info, i) ? 'E' : ' ',
1275 info->protect[i] ? "RO" : " ");
1276 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
1277 printf(" %08lX %s ",
1278 info->start[i],
1279 info->protect[i] ? "RO" : " ");
1280 #endif
1281 }
1282 putc('\n');
1283 return;
1284 }
1285
1286 /*-----------------------------------------------------------------------
1287 * This is used in a few places in write_buf() to show programming
1288 * progress. Making it a function is nasty because it needs to do side
1289 * effect updates to digit and dots. Repeated code is nasty too, so
1290 * we define it once here.
1291 */
1292 #ifdef CONFIG_FLASH_SHOW_PROGRESS
1293 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
1294 if (flash_verbose) { \
1295 dots -= dots_sub; \
1296 if (scale > 0 && dots <= 0) { \
1297 if ((digit % 5) == 0) \
1298 printf("%d", digit / 5); \
1299 else \
1300 putc('.'); \
1301 digit--; \
1302 dots += scale; \
1303 } \
1304 }
1305 #else
1306 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1307 #endif
1308
1309 /*-----------------------------------------------------------------------
1310 * Copy memory to flash, returns:
1311 * 0 - OK
1312 * 1 - write timeout
1313 * 2 - Flash not erased
1314 */
1315 int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
1316 {
1317 ulong wp;
1318 uchar *p;
1319 int aln;
1320 cfiword_t cword;
1321 int i, rc;
1322 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1323 int buffered_size;
1324 #endif
1325 #ifdef CONFIG_FLASH_SHOW_PROGRESS
1326 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1327 int scale = 0;
1328 int dots = 0;
1329
1330 /*
1331 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1332 */
1333 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1334 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1335 CONFIG_FLASH_SHOW_PROGRESS);
1336 }
1337 #endif
1338
1339 /* get lower aligned address */
1340 wp = (addr & ~(info->portwidth - 1));
1341
1342 /* handle unaligned start */
1343 if ((aln = addr - wp) != 0) {
1344 cword.w32 = 0;
1345 p = (uchar *)wp;
1346 for (i = 0; i < aln; ++i)
1347 flash_add_byte(info, &cword, flash_read8(p + i));
1348
1349 for (; (i < info->portwidth) && (cnt > 0); i++) {
1350 flash_add_byte(info, &cword, *src++);
1351 cnt--;
1352 }
1353 for (; (cnt == 0) && (i < info->portwidth); ++i)
1354 flash_add_byte(info, &cword, flash_read8(p + i));
1355
1356 rc = flash_write_cfiword(info, wp, cword);
1357 if (rc != 0)
1358 return rc;
1359
1360 wp += i;
1361 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
1362 }
1363
1364 /* handle the aligned part */
1365 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1366 buffered_size = (info->portwidth / info->chipwidth);
1367 buffered_size *= info->buffer_size;
1368 while (cnt >= info->portwidth) {
1369 /* prohibit buffer write when buffer_size is 1 */
1370 if (info->buffer_size == 1) {
1371 cword.w32 = 0;
1372 for (i = 0; i < info->portwidth; i++)
1373 flash_add_byte(info, &cword, *src++);
1374 if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
1375 return rc;
1376 wp += info->portwidth;
1377 cnt -= info->portwidth;
1378 continue;
1379 }
1380
1381 /* write buffer until next buffered_size aligned boundary */
1382 i = buffered_size - (wp % buffered_size);
1383 if (i > cnt)
1384 i = cnt;
1385 if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
1386 return rc;
1387 i -= i & (info->portwidth - 1);
1388 wp += i;
1389 src += i;
1390 cnt -= i;
1391 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
1392 /* Only check every once in a while */
1393 if ((cnt & 0xFFFF) < buffered_size && ctrlc())
1394 return ERR_ABORTED;
1395 }
1396 #else
1397 while (cnt >= info->portwidth) {
1398 cword.w32 = 0;
1399 for (i = 0; i < info->portwidth; i++)
1400 flash_add_byte(info, &cword, *src++);
1401 if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
1402 return rc;
1403 wp += info->portwidth;
1404 cnt -= info->portwidth;
1405 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
1406 /* Only check every once in a while */
1407 if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
1408 return ERR_ABORTED;
1409 }
1410 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
1411
1412 if (cnt == 0)
1413 return (0);
1414
1415 /*
1416 * handle unaligned tail bytes
1417 */
1418 cword.w32 = 0;
1419 p = (uchar *)wp;
1420 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
1421 flash_add_byte(info, &cword, *src++);
1422 --cnt;
1423 }
1424 for (; i < info->portwidth; ++i)
1425 flash_add_byte(info, &cword, flash_read8(p + i));
1426
1427 return flash_write_cfiword(info, wp, cword);
1428 }
1429
1430 static inline int manufact_match(flash_info_t *info, u32 manu)
1431 {
1432 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16);
1433 }
1434
1435 /*-----------------------------------------------------------------------
1436 */
1437 #ifdef CONFIG_SYS_FLASH_PROTECTION
1438
1439 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
1440 {
1441 if (manufact_match(info, INTEL_MANUFACT) &&
1442 info->device_id == NUMONYX_256MBIT) {
1443 /*
1444 * see errata called
1445 * "Numonyx Axcell P33/P30 Specification Update" :)
1446 */
1447 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID);
1448 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT,
1449 prot)) {
1450 /*
1451 * cmd must come before FLASH_CMD_PROTECT + 20us
1452 * Disable interrupts which might cause a timeout here.
1453 */
1454 int flag = disable_interrupts();
1455 unsigned short cmd;
1456
1457 if (prot)
1458 cmd = FLASH_CMD_PROTECT_SET;
1459 else
1460 cmd = FLASH_CMD_PROTECT_CLEAR;
1461
1462 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
1463 flash_write_cmd(info, sector, 0, cmd);
1464 /* re-enable interrupts if necessary */
1465 if (flag)
1466 enable_interrupts();
1467 }
1468 return 1;
1469 }
1470 return 0;
1471 }
1472
1473 int flash_real_protect(flash_info_t *info, long sector, int prot)
1474 {
1475 int retcode = 0;
1476
1477 switch (info->vendor) {
1478 case CFI_CMDSET_INTEL_PROG_REGIONS:
1479 case CFI_CMDSET_INTEL_STANDARD:
1480 case CFI_CMDSET_INTEL_EXTENDED:
1481 if (!cfi_protect_bugfix(info, sector, prot)) {
1482 flash_write_cmd(info, sector, 0,
1483 FLASH_CMD_CLEAR_STATUS);
1484 flash_write_cmd(info, sector, 0,
1485 FLASH_CMD_PROTECT);
1486 if (prot)
1487 flash_write_cmd(info, sector, 0,
1488 FLASH_CMD_PROTECT_SET);
1489 else
1490 flash_write_cmd(info, sector, 0,
1491 FLASH_CMD_PROTECT_CLEAR);
1492 }
1493 break;
1494 case CFI_CMDSET_AMD_EXTENDED:
1495 case CFI_CMDSET_AMD_STANDARD:
1496 /* U-Boot only checks the first byte */
1497 if (manufact_match(info, ATM_MANUFACT)) {
1498 if (prot) {
1499 flash_unlock_seq(info, 0);
1500 flash_write_cmd(info, 0,
1501 info->addr_unlock1,
1502 ATM_CMD_SOFTLOCK_START);
1503 flash_unlock_seq(info, 0);
1504 flash_write_cmd(info, sector, 0,
1505 ATM_CMD_LOCK_SECT);
1506 } else {
1507 flash_write_cmd(info, 0,
1508 info->addr_unlock1,
1509 AMD_CMD_UNLOCK_START);
1510 if (info->device_id == ATM_ID_BV6416)
1511 flash_write_cmd(info, sector,
1512 0, ATM_CMD_UNLOCK_SECT);
1513 }
1514 }
1515 if (info->legacy_unlock) {
1516 int flag = disable_interrupts();
1517 int lock_flag;
1518
1519 flash_unlock_seq(info, 0);
1520 flash_write_cmd(info, 0, info->addr_unlock1,
1521 AMD_CMD_SET_PPB_ENTRY);
1522 lock_flag = flash_isset(info, sector, 0, 0x01);
1523 if (prot) {
1524 if (lock_flag) {
1525 flash_write_cmd(info, sector, 0,
1526 AMD_CMD_PPB_LOCK_BC1);
1527 flash_write_cmd(info, sector, 0,
1528 AMD_CMD_PPB_LOCK_BC2);
1529 }
1530 debug("sector %ld %slocked\n", sector,
1531 lock_flag ? "" : "already ");
1532 } else {
1533 if (!lock_flag) {
1534 debug("unlock %ld\n", sector);
1535 flash_write_cmd(info, 0, 0,
1536 AMD_CMD_PPB_UNLOCK_BC1);
1537 flash_write_cmd(info, 0, 0,
1538 AMD_CMD_PPB_UNLOCK_BC2);
1539 }
1540 debug("sector %ld %sunlocked\n", sector,
1541 !lock_flag ? "" : "already ");
1542 }
1543 if (flag)
1544 enable_interrupts();
1545
1546 if (flash_status_check(info, sector,
1547 info->erase_blk_tout,
1548 prot ? "protect" : "unprotect"))
1549 printf("status check error\n");
1550
1551 flash_write_cmd(info, 0, 0,
1552 AMD_CMD_SET_PPB_EXIT_BC1);
1553 flash_write_cmd(info, 0, 0,
1554 AMD_CMD_SET_PPB_EXIT_BC2);
1555 }
1556 break;
1557 #ifdef CONFIG_FLASH_CFI_LEGACY
1558 case CFI_CMDSET_AMD_LEGACY:
1559 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1560 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
1561 if (prot)
1562 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
1563 else
1564 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1565 #endif
1566 };
1567
1568 /*
1569 * Flash needs to be in status register read mode for
1570 * flash_full_status_check() to work correctly
1571 */
1572 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
1573 if ((retcode =
1574 flash_full_status_check(info, sector, info->erase_blk_tout,
1575 prot ? "protect" : "unprotect")) == 0) {
1576 info->protect[sector] = prot;
1577
1578 /*
1579 * On some of Intel's flash chips (marked via legacy_unlock)
1580 * unprotect unprotects all locking.
1581 */
1582 if (prot == 0 && info->legacy_unlock) {
1583 flash_sect_t i;
1584
1585 for (i = 0; i < info->sector_count; i++) {
1586 if (info->protect[i])
1587 flash_real_protect(info, i, 1);
1588 }
1589 }
1590 }
1591 return retcode;
1592 }
1593
1594 /*-----------------------------------------------------------------------
1595 * flash_read_user_serial - read the OneTimeProgramming cells
1596 */
1597 void flash_read_user_serial(flash_info_t *info, void *buffer, int offset,
1598 int len)
1599 {
1600 uchar *src;
1601 uchar *dst;
1602
1603 dst = buffer;
1604 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION);
1605 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1606 memcpy(dst, src + offset, len);
1607 flash_write_cmd(info, 0, 0, info->cmd_reset);
1608 udelay(1);
1609 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
1610 }
1611
1612 /*
1613 * flash_read_factory_serial - read the device Id from the protection area
1614 */
1615 void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset,
1616 int len)
1617 {
1618 uchar *src;
1619
1620 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
1621 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1622 memcpy(buffer, src + offset, len);
1623 flash_write_cmd(info, 0, 0, info->cmd_reset);
1624 udelay(1);
1625 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
1626 }
1627
1628 #endif /* CONFIG_SYS_FLASH_PROTECTION */
1629
1630 /*-----------------------------------------------------------------------
1631 * Reverse the order of the erase regions in the CFI QRY structure.
1632 * This is needed for chips that are either a) correctly detected as
1633 * top-boot, or b) buggy.
1634 */
1635 static void cfi_reverse_geometry(struct cfi_qry *qry)
1636 {
1637 unsigned int i, j;
1638 u32 tmp;
1639
1640 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1641 tmp = get_unaligned(&qry->erase_region_info[i]);
1642 put_unaligned(get_unaligned(&qry->erase_region_info[j]),
1643 &qry->erase_region_info[i]);
1644 put_unaligned(tmp, &qry->erase_region_info[j]);
1645 }
1646 }
1647
1648 /*-----------------------------------------------------------------------
1649 * read jedec ids from device and set corresponding fields in info struct
1650 *
1651 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1652 *
1653 */
1654 static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1655 {
1656 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1657 udelay(1);
1658 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1659 udelay(1000); /* some flash are slow to respond */
1660 info->manufacturer_id = flash_read_uchar(info,
1661 FLASH_OFFSET_MANUFACTURER_ID);
1662 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
1663 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) :
1664 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID);
1665 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1666 }
1667
1668 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1669 {
1670 info->cmd_reset = FLASH_CMD_RESET;
1671
1672 cmdset_intel_read_jedec_ids(info);
1673 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1674
1675 #ifdef CONFIG_SYS_FLASH_PROTECTION
1676 /* read legacy lock/unlock bit from intel flash */
1677 if (info->ext_addr) {
1678 info->legacy_unlock = flash_read_uchar(info,
1679 info->ext_addr + 5) & 0x08;
1680 }
1681 #endif
1682
1683 return 0;
1684 }
1685
1686 static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1687 {
1688 ushort bankId = 0;
1689 uchar manuId;
1690 uchar feature;
1691
1692 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1693 flash_unlock_seq(info, 0);
1694 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1695 udelay(1000); /* some flash are slow to respond */
1696
1697 manuId = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID);
1698 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
1699 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) {
1700 bankId += 0x100;
1701 manuId = flash_read_uchar(info,
1702 bankId | FLASH_OFFSET_MANUFACTURER_ID);
1703 }
1704 info->manufacturer_id = manuId;
1705
1706 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n",
1707 info->ext_addr, info->cfi_version);
1708 if (info->ext_addr && info->cfi_version >= 0x3134) {
1709 /* read software feature (at 0x53) */
1710 feature = flash_read_uchar(info, info->ext_addr + 0x13);
1711 debug("feature = 0x%x\n", feature);
1712 info->sr_supported = feature & 0x1;
1713 }
1714
1715 switch (info->chipwidth) {
1716 case FLASH_CFI_8BIT:
1717 info->device_id = flash_read_uchar(info,
1718 FLASH_OFFSET_DEVICE_ID);
1719 if (info->device_id == 0x7E) {
1720 /* AMD 3-byte (expanded) device ids */
1721 info->device_id2 = flash_read_uchar(info,
1722 FLASH_OFFSET_DEVICE_ID2);
1723 info->device_id2 <<= 8;
1724 info->device_id2 |= flash_read_uchar(info,
1725 FLASH_OFFSET_DEVICE_ID3);
1726 }
1727 break;
1728 case FLASH_CFI_16BIT:
1729 info->device_id = flash_read_word(info,
1730 FLASH_OFFSET_DEVICE_ID);
1731 if ((info->device_id & 0xff) == 0x7E) {
1732 /* AMD 3-byte (expanded) device ids */
1733 info->device_id2 = flash_read_uchar(info,
1734 FLASH_OFFSET_DEVICE_ID2);
1735 info->device_id2 <<= 8;
1736 info->device_id2 |= flash_read_uchar(info,
1737 FLASH_OFFSET_DEVICE_ID3);
1738 }
1739 break;
1740 default:
1741 break;
1742 }
1743 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1744 udelay(1);
1745 }
1746
1747 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1748 {
1749 info->cmd_reset = AMD_CMD_RESET;
1750 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR;
1751
1752 cmdset_amd_read_jedec_ids(info);
1753 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1754
1755 #ifdef CONFIG_SYS_FLASH_PROTECTION
1756 if (info->ext_addr) {
1757 /* read sector protect/unprotect scheme (at 0x49) */
1758 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8)
1759 info->legacy_unlock = 1;
1760 }
1761 #endif
1762
1763 return 0;
1764 }
1765
1766 #ifdef CONFIG_FLASH_CFI_LEGACY
1767 static void flash_read_jedec_ids(flash_info_t *info)
1768 {
1769 info->manufacturer_id = 0;
1770 info->device_id = 0;
1771 info->device_id2 = 0;
1772
1773 switch (info->vendor) {
1774 case CFI_CMDSET_INTEL_PROG_REGIONS:
1775 case CFI_CMDSET_INTEL_STANDARD:
1776 case CFI_CMDSET_INTEL_EXTENDED:
1777 cmdset_intel_read_jedec_ids(info);
1778 break;
1779 case CFI_CMDSET_AMD_STANDARD:
1780 case CFI_CMDSET_AMD_EXTENDED:
1781 cmdset_amd_read_jedec_ids(info);
1782 break;
1783 default:
1784 break;
1785 }
1786 }
1787
1788 /*-----------------------------------------------------------------------
1789 * Call board code to request info about non-CFI flash.
1790 * board_flash_get_legacy needs to fill in at least:
1791 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
1792 */
1793 static int flash_detect_legacy(phys_addr_t base, int banknum)
1794 {
1795 flash_info_t *info = &flash_info[banknum];
1796
1797 if (board_flash_get_legacy(base, banknum, info)) {
1798 /* board code may have filled info completely. If not, we
1799 * use JEDEC ID probing.
1800 */
1801 if (!info->vendor) {
1802 int modes[] = {
1803 CFI_CMDSET_AMD_STANDARD,
1804 CFI_CMDSET_INTEL_STANDARD
1805 };
1806 int i;
1807
1808 for (i = 0; i < ARRAY_SIZE(modes); i++) {
1809 info->vendor = modes[i];
1810 info->start[0] =
1811 (ulong)map_physmem(base,
1812 info->portwidth,
1813 MAP_NOCACHE);
1814 if (info->portwidth == FLASH_CFI_8BIT &&
1815 info->interface == FLASH_CFI_X8X16) {
1816 info->addr_unlock1 = 0x2AAA;
1817 info->addr_unlock2 = 0x5555;
1818 } else {
1819 info->addr_unlock1 = 0x5555;
1820 info->addr_unlock2 = 0x2AAA;
1821 }
1822 flash_read_jedec_ids(info);
1823 debug("JEDEC PROBE: ID %x %x %x\n",
1824 info->manufacturer_id,
1825 info->device_id,
1826 info->device_id2);
1827 if (jedec_flash_match(info, info->start[0]))
1828 break;
1829
1830 unmap_physmem((void *)info->start[0],
1831 info->portwidth);
1832 }
1833 }
1834
1835 switch (info->vendor) {
1836 case CFI_CMDSET_INTEL_PROG_REGIONS:
1837 case CFI_CMDSET_INTEL_STANDARD:
1838 case CFI_CMDSET_INTEL_EXTENDED:
1839 info->cmd_reset = FLASH_CMD_RESET;
1840 break;
1841 case CFI_CMDSET_AMD_STANDARD:
1842 case CFI_CMDSET_AMD_EXTENDED:
1843 case CFI_CMDSET_AMD_LEGACY:
1844 info->cmd_reset = AMD_CMD_RESET;
1845 break;
1846 }
1847 info->flash_id = FLASH_MAN_CFI;
1848 return 1;
1849 }
1850 return 0; /* use CFI */
1851 }
1852 #else
1853 static inline int flash_detect_legacy(phys_addr_t base, int banknum)
1854 {
1855 return 0; /* use CFI */
1856 }
1857 #endif
1858
1859 /*-----------------------------------------------------------------------
1860 * detect if flash is compatible with the Common Flash Interface (CFI)
1861 * http://www.jedec.org/download/search/jesd68.pdf
1862 */
1863 static void flash_read_cfi(flash_info_t *info, void *buf,
1864 unsigned int start, size_t len)
1865 {
1866 u8 *p = buf;
1867 unsigned int i;
1868
1869 for (i = 0; i < len; i++)
1870 p[i] = flash_read_uchar(info, start + i);
1871 }
1872
1873 static void __flash_cmd_reset(flash_info_t *info)
1874 {
1875 /*
1876 * We do not yet know what kind of commandset to use, so we issue
1877 * the reset command in both Intel and AMD variants, in the hope
1878 * that AMD flash roms ignore the Intel command.
1879 */
1880 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1881 udelay(1);
1882 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1883 }
1884
1885 void flash_cmd_reset(flash_info_t *info)
1886 __attribute__((weak, alias("__flash_cmd_reset")));
1887
1888 static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
1889 {
1890 int cfi_offset;
1891
1892 /* Issue FLASH reset command */
1893 flash_cmd_reset(info);
1894
1895 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi);
1896 cfi_offset++) {
1897 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset],
1898 FLASH_CMD_CFI);
1899 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
1900 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
1901 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
1902 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1903 sizeof(struct cfi_qry));
1904 info->interface = le16_to_cpu(qry->interface_desc);
1905
1906 info->cfi_offset = flash_offset_cfi[cfi_offset];
1907 debug("device interface is %d\n",
1908 info->interface);
1909 debug("found port %d chip %d ",
1910 info->portwidth, info->chipwidth);
1911 debug("port %d bits chip %d bits\n",
1912 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1913 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1914
1915 /* calculate command offsets as in the Linux driver */
1916 info->addr_unlock1 = 0x555;
1917 info->addr_unlock2 = 0x2aa;
1918
1919 /*
1920 * modify the unlock address if we are
1921 * in compatibility mode
1922 */
1923 if (/* x8/x16 in x8 mode */
1924 (info->chipwidth == FLASH_CFI_BY8 &&
1925 info->interface == FLASH_CFI_X8X16) ||
1926 /* x16/x32 in x16 mode */
1927 (info->chipwidth == FLASH_CFI_BY16 &&
1928 info->interface == FLASH_CFI_X16X32))
1929 {
1930 info->addr_unlock1 = 0xaaa;
1931 info->addr_unlock2 = 0x555;
1932 }
1933
1934 info->name = "CFI conformant";
1935 return 1;
1936 }
1937 }
1938
1939 return 0;
1940 }
1941
1942 static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
1943 {
1944 debug("flash detect cfi\n");
1945
1946 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
1947 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1948 for (info->chipwidth = FLASH_CFI_BY8;
1949 info->chipwidth <= info->portwidth;
1950 info->chipwidth <<= 1)
1951 if (__flash_detect_cfi(info, qry))
1952 return 1;
1953 }
1954 debug("not found\n");
1955 return 0;
1956 }
1957
1958 /*
1959 * Manufacturer-specific quirks. Add workarounds for geometry
1960 * reversal, etc. here.
1961 */
1962 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1963 {
1964 /* check if flash geometry needs reversal */
1965 if (qry->num_erase_regions > 1) {
1966 /* reverse geometry if top boot part */
1967 if (info->cfi_version < 0x3131) {
1968 /* CFI < 1.1, try to guess from device id */
1969 if ((info->device_id & 0x80) != 0)
1970 cfi_reverse_geometry(qry);
1971 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1972 /* CFI >= 1.1, deduct from top/bottom flag */
1973 /* note: ext_addr is valid since cfi_version > 0 */
1974 cfi_reverse_geometry(qry);
1975 }
1976 }
1977 }
1978
1979 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1980 {
1981 int reverse_geometry = 0;
1982
1983 /* Check the "top boot" bit in the PRI */
1984 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1985 reverse_geometry = 1;
1986
1987 /* AT49BV6416(T) list the erase regions in the wrong order.
1988 * However, the device ID is identical with the non-broken
1989 * AT49BV642D they differ in the high byte.
1990 */
1991 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1992 reverse_geometry = !reverse_geometry;
1993
1994 if (reverse_geometry)
1995 cfi_reverse_geometry(qry);
1996 }
1997
1998 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
1999 {
2000 /* check if flash geometry needs reversal */
2001 if (qry->num_erase_regions > 1) {
2002 /* reverse geometry if top boot part */
2003 if (info->cfi_version < 0x3131) {
2004 /* CFI < 1.1, guess by device id */
2005 if (info->device_id == 0x22CA || /* M29W320DT */
2006 info->device_id == 0x2256 || /* M29W320ET */
2007 info->device_id == 0x22D7) { /* M29W800DT */
2008 cfi_reverse_geometry(qry);
2009 }
2010 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
2011 /* CFI >= 1.1, deduct from top/bottom flag */
2012 /* note: ext_addr is valid since cfi_version > 0 */
2013 cfi_reverse_geometry(qry);
2014 }
2015 }
2016 }
2017
2018 static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry)
2019 {
2020 /*
2021 * SST, for many recent nor parallel flashes, says they are
2022 * CFI-conformant. This is not true, since qry struct.
2023 * reports a std. AMD command set (0x0002), while SST allows to
2024 * erase two different sector sizes for the same memory.
2025 * 64KB sector (SST call it block) needs 0x30 to be erased.
2026 * 4KB sector (SST call it sector) needs 0x50 to be erased.
2027 * Since CFI query detect the 4KB number of sectors, users expects
2028 * a sector granularity of 4KB, and it is here set.
2029 */
2030 if (info->device_id == 0x5D23 || /* SST39VF3201B */
2031 info->device_id == 0x5C23) { /* SST39VF3202B */
2032 /* set sector granularity to 4KB */
2033 info->cmd_erase_sector = 0x50;
2034 }
2035 }
2036
2037 static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry)
2038 {
2039 /*
2040 * The M29EW devices seem to report the CFI information wrong
2041 * when it's in 8 bit mode.
2042 * There's an app note from Numonyx on this issue.
2043 * So adjust the buffer size for M29EW while operating in 8-bit mode
2044 */
2045 if (qry->max_buf_write_size > 0x8 &&
2046 info->device_id == 0x7E &&
2047 (info->device_id2 == 0x2201 ||
2048 info->device_id2 == 0x2301 ||
2049 info->device_id2 == 0x2801 ||
2050 info->device_id2 == 0x4801)) {
2051 debug("Adjusted buffer size on Numonyx flash"
2052 " M29EW family in 8 bit mode\n");
2053 qry->max_buf_write_size = 0x8;
2054 }
2055 }
2056
2057 /*
2058 * The following code cannot be run from FLASH!
2059 *
2060 */
2061 ulong flash_get_size(phys_addr_t base, int banknum)
2062 {
2063 flash_info_t *info = &flash_info[banknum];
2064 int i, j;
2065 flash_sect_t sect_cnt;
2066 phys_addr_t sector;
2067 unsigned long tmp;
2068 int size_ratio;
2069 uchar num_erase_regions;
2070 int erase_region_size;
2071 int erase_region_count;
2072 struct cfi_qry qry;
2073 unsigned long max_size;
2074
2075 memset(&qry, 0, sizeof(qry));
2076
2077 info->ext_addr = 0;
2078 info->cfi_version = 0;
2079 #ifdef CONFIG_SYS_FLASH_PROTECTION
2080 info->legacy_unlock = 0;
2081 #endif
2082
2083 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
2084
2085 if (flash_detect_cfi(info, &qry)) {
2086 info->vendor = le16_to_cpu(get_unaligned(&qry.p_id));
2087 info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr));
2088 num_erase_regions = qry.num_erase_regions;
2089
2090 if (info->ext_addr) {
2091 info->cfi_version = (ushort)flash_read_uchar(info,
2092 info->ext_addr + 3) << 8;
2093 info->cfi_version |= (ushort)flash_read_uchar(info,
2094 info->ext_addr + 4);
2095 }
2096
2097 #ifdef DEBUG
2098 flash_printqry(&qry);
2099 #endif
2100
2101 switch (info->vendor) {
2102 case CFI_CMDSET_INTEL_PROG_REGIONS:
2103 case CFI_CMDSET_INTEL_STANDARD:
2104 case CFI_CMDSET_INTEL_EXTENDED:
2105 cmdset_intel_init(info, &qry);
2106 break;
2107 case CFI_CMDSET_AMD_STANDARD:
2108 case CFI_CMDSET_AMD_EXTENDED:
2109 cmdset_amd_init(info, &qry);
2110 break;
2111 default:
2112 printf("CFI: Unknown command set 0x%x\n",
2113 info->vendor);
2114 /*
2115 * Unfortunately, this means we don't know how
2116 * to get the chip back to Read mode. Might
2117 * as well try an Intel-style reset...
2118 */
2119 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
2120 return 0;
2121 }
2122
2123 /* Do manufacturer-specific fixups */
2124 switch (info->manufacturer_id) {
2125 case 0x0001: /* AMD */
2126 case 0x0037: /* AMIC */
2127 flash_fixup_amd(info, &qry);
2128 break;
2129 case 0x001f:
2130 flash_fixup_atmel(info, &qry);
2131 break;
2132 case 0x0020:
2133 flash_fixup_stm(info, &qry);
2134 break;
2135 case 0x00bf: /* SST */
2136 flash_fixup_sst(info, &qry);
2137 break;
2138 case 0x0089: /* Numonyx */
2139 flash_fixup_num(info, &qry);
2140 break;
2141 }
2142
2143 debug("manufacturer is %d\n", info->vendor);
2144 debug("manufacturer id is 0x%x\n", info->manufacturer_id);
2145 debug("device id is 0x%x\n", info->device_id);
2146 debug("device id2 is 0x%x\n", info->device_id2);
2147 debug("cfi version is 0x%04x\n", info->cfi_version);
2148
2149 size_ratio = info->portwidth / info->chipwidth;
2150 /* if the chip is x8/x16 reduce the ratio by half */
2151 if (info->interface == FLASH_CFI_X8X16 &&
2152 info->chipwidth == FLASH_CFI_BY8) {
2153 size_ratio >>= 1;
2154 }
2155 debug("size_ratio %d port %d bits chip %d bits\n",
2156 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
2157 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
2158 info->size = 1 << qry.dev_size;
2159 /* multiply the size by the number of chips */
2160 info->size *= size_ratio;
2161 max_size = cfi_flash_bank_size(banknum);
2162 if (max_size && info->size > max_size) {
2163 debug("[truncated from %ldMiB]", info->size >> 20);
2164 info->size = max_size;
2165 }
2166 debug("found %d erase regions\n", num_erase_regions);
2167 sect_cnt = 0;
2168 sector = base;
2169 for (i = 0; i < num_erase_regions; i++) {
2170 if (i > NUM_ERASE_REGIONS) {
2171 printf("%d erase regions found, only %d used\n",
2172 num_erase_regions, NUM_ERASE_REGIONS);
2173 break;
2174 }
2175
2176 tmp = le32_to_cpu(get_unaligned(
2177 &qry.erase_region_info[i]));
2178 debug("erase region %u: 0x%08lx\n", i, tmp);
2179
2180 erase_region_count = (tmp & 0xffff) + 1;
2181 tmp >>= 16;
2182 erase_region_size =
2183 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
2184 debug("erase_region_count = %d erase_region_size = %d\n",
2185 erase_region_count, erase_region_size);
2186 for (j = 0; j < erase_region_count; j++) {
2187 if (sector - base >= info->size)
2188 break;
2189 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
2190 printf("ERROR: too many flash sectors\n");
2191 break;
2192 }
2193 info->start[sect_cnt] =
2194 (ulong)map_physmem(sector,
2195 info->portwidth,
2196 MAP_NOCACHE);
2197 sector += (erase_region_size * size_ratio);
2198
2199 /*
2200 * Only read protection status from
2201 * supported devices (intel...)
2202 */
2203 switch (info->vendor) {
2204 case CFI_CMDSET_INTEL_PROG_REGIONS:
2205 case CFI_CMDSET_INTEL_EXTENDED:
2206 case CFI_CMDSET_INTEL_STANDARD:
2207 /*
2208 * Set flash to read-id mode. Otherwise
2209 * reading protected status is not
2210 * guaranteed.
2211 */
2212 flash_write_cmd(info, sect_cnt, 0,
2213 FLASH_CMD_READ_ID);
2214 info->protect[sect_cnt] =
2215 flash_isset(info, sect_cnt,
2216 FLASH_OFFSET_PROTECT,
2217 FLASH_STATUS_PROTECT);
2218 flash_write_cmd(info, sect_cnt, 0,
2219 FLASH_CMD_RESET);
2220 break;
2221 case CFI_CMDSET_AMD_EXTENDED:
2222 case CFI_CMDSET_AMD_STANDARD:
2223 if (!info->legacy_unlock) {
2224 /* default: not protected */
2225 info->protect[sect_cnt] = 0;
2226 break;
2227 }
2228
2229 /* Read protection (PPB) from sector */
2230 flash_write_cmd(info, 0, 0,
2231 info->cmd_reset);
2232 flash_unlock_seq(info, 0);
2233 flash_write_cmd(info, 0,
2234 info->addr_unlock1,
2235 FLASH_CMD_READ_ID);
2236 info->protect[sect_cnt] =
2237 flash_isset(
2238 info, sect_cnt,
2239 FLASH_OFFSET_PROTECT,
2240 FLASH_STATUS_PROTECT);
2241 break;
2242 default:
2243 /* default: not protected */
2244 info->protect[sect_cnt] = 0;
2245 }
2246
2247 sect_cnt++;
2248 }
2249 }
2250
2251 info->sector_count = sect_cnt;
2252 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
2253 tmp = 1 << qry.block_erase_timeout_typ;
2254 info->erase_blk_tout = tmp *
2255 (1 << qry.block_erase_timeout_max);
2256 tmp = (1 << qry.buf_write_timeout_typ) *
2257 (1 << qry.buf_write_timeout_max);
2258
2259 /* round up when converting to ms */
2260 info->buffer_write_tout = (tmp + 999) / 1000;
2261 tmp = (1 << qry.word_write_timeout_typ) *
2262 (1 << qry.word_write_timeout_max);
2263 /* round up when converting to ms */
2264 info->write_tout = (tmp + 999) / 1000;
2265 info->flash_id = FLASH_MAN_CFI;
2266 if (info->interface == FLASH_CFI_X8X16 &&
2267 info->chipwidth == FLASH_CFI_BY8) {
2268 /* XXX - Need to test on x8/x16 in parallel. */
2269 info->portwidth >>= 1;
2270 }
2271
2272 flash_write_cmd(info, 0, 0, info->cmd_reset);
2273 }
2274
2275 return (info->size);
2276 }
2277
2278 #ifdef CONFIG_FLASH_CFI_MTD
2279 void flash_set_verbose(uint v)
2280 {
2281 flash_verbose = v;
2282 }
2283 #endif
2284
2285 static void cfi_flash_set_config_reg(u32 base, u16 val)
2286 {
2287 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
2288 /*
2289 * Only set this config register if really defined
2290 * to a valid value (0xffff is invalid)
2291 */
2292 if (val == 0xffff)
2293 return;
2294
2295 /*
2296 * Set configuration register. Data is "encrypted" in the 16 lower
2297 * address bits.
2298 */
2299 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
2300 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
2301
2302 /*
2303 * Finally issue reset-command to bring device back to
2304 * read-array mode
2305 */
2306 flash_write16(FLASH_CMD_RESET, (void *)base);
2307 #endif
2308 }
2309
2310 /*-----------------------------------------------------------------------
2311 */
2312
2313 static void flash_protect_default(void)
2314 {
2315 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2316 int i;
2317 struct apl_s {
2318 ulong start;
2319 ulong size;
2320 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
2321 #endif
2322
2323 /* Monitor protection ON by default */
2324 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
2325 (!defined(CONFIG_MONITOR_IS_IN_RAM))
2326 flash_protect(FLAG_PROTECT_SET,
2327 CONFIG_SYS_MONITOR_BASE,
2328 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2329 flash_get_info(CONFIG_SYS_MONITOR_BASE));
2330 #endif
2331
2332 /* Environment protection ON by default */
2333 #ifdef CONFIG_ENV_IS_IN_FLASH
2334 flash_protect(FLAG_PROTECT_SET,
2335 CONFIG_ENV_ADDR,
2336 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2337 flash_get_info(CONFIG_ENV_ADDR));
2338 #endif
2339
2340 /* Redundant environment protection ON by default */
2341 #ifdef CONFIG_ENV_ADDR_REDUND
2342 flash_protect(FLAG_PROTECT_SET,
2343 CONFIG_ENV_ADDR_REDUND,
2344 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
2345 flash_get_info(CONFIG_ENV_ADDR_REDUND));
2346 #endif
2347
2348 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2349 for (i = 0; i < ARRAY_SIZE(apl); i++) {
2350 debug("autoprotecting from %08lx to %08lx\n",
2351 apl[i].start, apl[i].start + apl[i].size - 1);
2352 flash_protect(FLAG_PROTECT_SET,
2353 apl[i].start,
2354 apl[i].start + apl[i].size - 1,
2355 flash_get_info(apl[i].start));
2356 }
2357 #endif
2358 }
2359
2360 unsigned long flash_init(void)
2361 {
2362 unsigned long size = 0;
2363 int i;
2364
2365 #ifdef CONFIG_SYS_FLASH_PROTECTION
2366 /* read environment from EEPROM */
2367 char s[64];
2368
2369 env_get_f("unlock", s, sizeof(s));
2370 #endif
2371
2372 #ifdef CONFIG_CFI_FLASH /* for driver model */
2373 cfi_flash_init_dm();
2374 #endif
2375
2376 /* Init: no FLASHes known */
2377 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
2378 flash_info[i].flash_id = FLASH_UNKNOWN;
2379
2380 /* Optionally write flash configuration register */
2381 cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
2382 cfi_flash_config_reg(i));
2383
2384 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
2385 flash_get_size(cfi_flash_bank_addr(i), i);
2386 size += flash_info[i].size;
2387 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
2388 #ifndef CONFIG_SYS_FLASH_QUIET_TEST
2389 printf("## Unknown flash on Bank %d "
2390 "- Size = 0x%08lx = %ld MB\n",
2391 i + 1, flash_info[i].size,
2392 flash_info[i].size >> 20);
2393 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */
2394 }
2395 #ifdef CONFIG_SYS_FLASH_PROTECTION
2396 else if (strcmp(s, "yes") == 0) {
2397 /*
2398 * Only the U-Boot image and it's environment
2399 * is protected, all other sectors are
2400 * unprotected (unlocked) if flash hardware
2401 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
2402 * and the environment variable "unlock" is
2403 * set to "yes".
2404 */
2405 if (flash_info[i].legacy_unlock) {
2406 int k;
2407
2408 /*
2409 * Disable legacy_unlock temporarily,
2410 * since flash_real_protect would
2411 * relock all other sectors again
2412 * otherwise.
2413 */
2414 flash_info[i].legacy_unlock = 0;
2415
2416 /*
2417 * Legacy unlocking (e.g. Intel J3) ->
2418 * unlock only one sector. This will
2419 * unlock all sectors.
2420 */
2421 flash_real_protect(&flash_info[i], 0, 0);
2422
2423 flash_info[i].legacy_unlock = 1;
2424
2425 /*
2426 * Manually mark other sectors as
2427 * unlocked (unprotected)
2428 */
2429 for (k = 1; k < flash_info[i].sector_count; k++)
2430 flash_info[i].protect[k] = 0;
2431 } else {
2432 /*
2433 * No legancy unlocking -> unlock all sectors
2434 */
2435 flash_protect(FLAG_PROTECT_CLEAR,
2436 flash_info[i].start[0],
2437 flash_info[i].start[0]
2438 + flash_info[i].size - 1,
2439 &flash_info[i]);
2440 }
2441 }
2442 #endif /* CONFIG_SYS_FLASH_PROTECTION */
2443 }
2444
2445 flash_protect_default();
2446 #ifdef CONFIG_FLASH_CFI_MTD
2447 cfi_mtd_init();
2448 #endif
2449
2450 return (size);
2451 }
2452
2453 #ifdef CONFIG_CFI_FLASH /* for driver model */
2454 static int cfi_flash_probe(struct udevice *dev)
2455 {
2456 void *blob = (void *)gd->fdt_blob;
2457 int node = dev_of_offset(dev);
2458 const fdt32_t *cell;
2459 phys_addr_t addr;
2460 int parent, addrc, sizec;
2461 int len, idx;
2462
2463 parent = fdt_parent_offset(blob, node);
2464 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
2465 /* decode regs, there may be multiple reg tuples. */
2466 cell = fdt_getprop(blob, node, "reg", &len);
2467 if (!cell)
2468 return -ENOENT;
2469 idx = 0;
2470 len /= sizeof(fdt32_t);
2471 while (idx < len) {
2472 addr = fdt_translate_address((void *)blob,
2473 node, cell + idx);
2474 flash_info[cfi_flash_num_flash_banks].dev = dev;
2475 flash_info[cfi_flash_num_flash_banks].base = addr;
2476 cfi_flash_num_flash_banks++;
2477 idx += addrc + sizec;
2478 }
2479 gd->bd->bi_flashstart = flash_info[0].base;
2480
2481 return 0;
2482 }
2483
2484 static const struct udevice_id cfi_flash_ids[] = {
2485 { .compatible = "cfi-flash" },
2486 { .compatible = "jedec-flash" },
2487 {}
2488 };
2489
2490 U_BOOT_DRIVER(cfi_flash) = {
2491 .name = "cfi_flash",
2492 .id = UCLASS_MTD,
2493 .of_match = cfi_flash_ids,
2494 .probe = cfi_flash_probe,
2495 };
2496 #endif /* CONFIG_CFI_FLASH */
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