2 * Arasan NAND Flash Controller Driver
4 * Copyright (C) 2014 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/nand_ecc.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
21 struct arasan_nand_info
{
22 void __iomem
*nand_base
;
57 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
59 struct arasan_nand_command_format
{
66 #define ONDIE_ECC_FEATURE_ADDR 0x90
68 #define ARASAN_PROG_RD_MASK 0x00000001
69 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
70 #define ARASAN_PROG_RD_ID_MASK 0x00000040
71 #define ARASAN_PROG_RD_STS_MASK 0x00000008
72 #define ARASAN_PROG_PG_PROG_MASK 0x00000010
73 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
74 #define ARASAN_PROG_RST_MASK 0x00000100
75 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
76 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
77 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
79 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
80 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
81 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
82 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
83 #define ARASAN_NAND_CMD_CMD2_SHIFT 8
84 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
85 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
87 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
88 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
89 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
90 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
91 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
92 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
93 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
95 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
96 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
97 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
98 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
99 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
101 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
102 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
103 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
105 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
106 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
107 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
109 #define ARASAN_NAND_ECC_SIZE_SHIFT 16
110 #define ARASAN_NAND_ECC_BCH_SHIFT 27
112 #define ARASAN_NAND_PKTSIZE_1K 1024
113 #define ARASAN_NAND_PKTSIZE_512 512
115 #define ARASAN_NAND_POLL_TIMEOUT 1000000
116 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
118 #define ERR_ADDR_CYCLE -1
119 #define READ_BUFF_SIZE 0x4000
121 static struct arasan_nand_command_format
*curr_cmd
;
131 static struct arasan_nand_command_format arasan_nand_commands
[] = {
132 {NAND_CMD_READ0
, NAND_CMD_READSTART
, NAND_ADDR_CYCL_BOTH
,
133 ARASAN_PROG_RD_MASK
},
134 {NAND_CMD_RNDOUT
, NAND_CMD_RNDOUTSTART
, NAND_ADDR_CYCL_COL
,
135 ARASAN_PROG_RD_MASK
},
136 {NAND_CMD_READID
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
137 ARASAN_PROG_RD_ID_MASK
},
138 {NAND_CMD_STATUS
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
,
139 ARASAN_PROG_RD_STS_MASK
},
140 {NAND_CMD_SEQIN
, NAND_CMD_PAGEPROG
, NAND_ADDR_CYCL_BOTH
,
141 ARASAN_PROG_PG_PROG_MASK
},
142 {NAND_CMD_RNDIN
, NAND_CMD_NONE
, NAND_ADDR_CYCL_COL
,
143 ARASAN_PROG_CHNG_ROWADR_END_MASK
},
144 {NAND_CMD_ERASE1
, NAND_CMD_ERASE2
, NAND_ADDR_CYCL_ROW
,
145 ARASAN_PROG_BLK_ERS_MASK
},
146 {NAND_CMD_RESET
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
,
147 ARASAN_PROG_RST_MASK
},
148 {NAND_CMD_PARAM
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
149 ARASAN_PROG_RD_PARAM_PG_MASK
},
150 {NAND_CMD_GET_FEATURES
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
151 ARASAN_PROG_GET_FTRS_MASK
},
152 {NAND_CMD_SET_FEATURES
, NAND_CMD_NONE
, NAND_ADDR_CYCL_ONE
,
153 ARASAN_PROG_SET_FTRS_MASK
},
154 {NAND_CMD_NONE
, NAND_CMD_NONE
, NAND_ADDR_CYCL_NONE
, 0},
157 struct arasan_ecc_matrix
{
159 u32 ecc_codeword_size
;
167 static const struct arasan_ecc_matrix ecc_matrix
[] = {
168 {512, 512, 1, 0, 0, 0x20D, 0x3},
169 {512, 512, 4, 1, 3, 0x209, 0x7},
170 {512, 512, 8, 1, 2, 0x203, 0xD},
174 {2048, 512, 1, 0, 0, 0x834, 0xC},
175 {2048, 512, 4, 1, 3, 0x826, 0x1A},
176 {2048, 512, 8, 1, 2, 0x80c, 0x34},
177 {2048, 512, 12, 1, 1, 0x822, 0x4E},
178 {2048, 512, 16, 1, 0, 0x808, 0x68},
179 {2048, 1024, 24, 1, 4, 0x81c, 0x54},
183 {4096, 512, 1, 0, 0, 0x1068, 0x18},
184 {4096, 512, 4, 1, 3, 0x104c, 0x34},
185 {4096, 512, 8, 1, 2, 0x1018, 0x68},
186 {4096, 512, 12, 1, 1, 0x1044, 0x9C},
187 {4096, 512, 16, 1, 0, 0x1010, 0xD0},
188 {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
192 {8192, 512, 1, 0, 0, 0x20d0, 0x30},
193 {8192, 512, 4, 1, 3, 0x2098, 0x68},
194 {8192, 512, 8, 1, 2, 0x2030, 0xD0},
195 {8192, 512, 12, 1, 1, 0x2088, 0x138},
196 {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
197 {8192, 1024, 24, 1, 4, 0x2070, 0x150},
201 {16384, 512, 1, 0, 0, 0x4460, 0x60},
202 {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
203 {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
204 {16384, 512, 12, 1, 1, 0x4250, 0x270},
205 {16384, 512, 16, 1, 0, 0x4180, 0x340},
206 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
209 static u8 buf_data
[READ_BUFF_SIZE
];
210 static u32 buf_index
;
212 static struct nand_ecclayout nand_oob
;
214 static struct nand_chip nand_chip
[CONFIG_SYS_MAX_NAND_DEVICE
];
216 static void arasan_nand_select_chip(struct mtd_info
*mtd
, int chip
)
220 static void arasan_nand_enable_ecc(void)
224 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
225 reg_val
|= ARASAN_NAND_CMD_ECC_ON_MASK
;
227 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
230 static u8
arasan_nand_get_addrcycle(struct mtd_info
*mtd
)
233 struct nand_chip
*chip
= mtd_to_nand(mtd
);
235 switch (curr_cmd
->addr_cycles
) {
236 case NAND_ADDR_CYCL_NONE
:
239 case NAND_ADDR_CYCL_ONE
:
242 case NAND_ADDR_CYCL_ROW
:
243 addrcycles
= chip
->onfi_params
.addr_cycles
&
244 ARASAN_NAND_ROW_ADDR_CYCL_MASK
;
246 case NAND_ADDR_CYCL_COL
:
247 addrcycles
= (chip
->onfi_params
.addr_cycles
&
248 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
249 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
251 case NAND_ADDR_CYCL_BOTH
:
252 addrcycles
= chip
->onfi_params
.addr_cycles
&
253 ARASAN_NAND_ROW_ADDR_CYCL_MASK
;
254 addrcycles
+= (chip
->onfi_params
.addr_cycles
&
255 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
256 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
259 addrcycles
= ARASAN_NAND_INVALID_ADDR_CYCL
;
265 static int arasan_nand_read_page(struct mtd_info
*mtd
, u8
*buf
, u32 size
)
267 struct nand_chip
*chip
= mtd_to_nand(mtd
);
268 u32 reg_val
, i
, pktsize
, pktnum
;
269 u32
*bufptr
= (u32
*)buf
;
274 if (chip
->ecc_step_ds
>= ARASAN_NAND_PKTSIZE_1K
)
275 pktsize
= ARASAN_NAND_PKTSIZE_1K
;
277 pktsize
= ARASAN_NAND_PKTSIZE_512
;
280 pktnum
= size
/pktsize
+ 1;
282 pktnum
= size
/pktsize
;
284 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
285 reg_val
|= ARASAN_NAND_INT_STS_ERR_EN_MASK
|
286 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK
;
287 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
289 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
290 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
291 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
292 reg_val
|= (pktnum
<< ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) |
294 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
296 arasan_nand_enable_ecc();
297 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
298 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
299 return ERR_ADDR_CYCLE
;
301 writel((NAND_CMD_RNDOUTSTART
<< ARASAN_NAND_CMD_CMD2_SHIFT
) |
302 NAND_CMD_RNDOUT
| (addr_cycles
<<
303 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
),
304 &arasan_nand_base
->ecc_sprcmd_reg
);
305 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
307 while (rdcount
< pktnum
) {
308 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
309 while (!(readl(&arasan_nand_base
->intsts_reg
) &
310 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
) && timeout
) {
315 puts("arasan_read_page: timedout:Buff RDY\n");
321 if (pktnum
== rdcount
) {
322 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
323 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
324 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
326 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
327 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
328 &arasan_nand_base
->intsts_enr
);
330 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
331 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
332 &arasan_nand_base
->intsts_reg
);
334 for (i
= 0; i
< pktsize
/4; i
++)
335 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
340 if (rdcount
>= pktnum
)
343 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
344 &arasan_nand_base
->intsts_enr
);
347 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
349 while (!(readl(&arasan_nand_base
->intsts_reg
) &
350 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
355 puts("arasan rd_page timedout:Xfer CMPLT\n");
359 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
360 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
361 &arasan_nand_base
->intsts_enr
);
362 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
363 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
364 &arasan_nand_base
->intsts_reg
);
366 if (readl(&arasan_nand_base
->intsts_reg
) &
367 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK
) {
368 printf("arasan rd_page:sbiterror\n");
372 if (readl(&arasan_nand_base
->intsts_reg
) &
373 ARASAN_NAND_INT_STS_ERR_EN_MASK
) {
374 mtd
->ecc_stats
.failed
++;
375 printf("arasan rd_page:multibiterror\n");
382 static int arasan_nand_read_page_hwecc(struct mtd_info
*mtd
,
383 struct nand_chip
*chip
, u8
*buf
, int oob_required
, int page
)
387 status
= arasan_nand_read_page(mtd
, buf
, (mtd
->writesize
));
390 chip
->ecc
.read_oob(mtd
, chip
, page
);
395 static void arasan_nand_fill_tx(const u8
*buf
, int len
)
397 u32 __iomem
*nand
= &arasan_nand_base
->buf_dataport
;
399 if (((unsigned long)buf
& 0x3) != 0) {
400 if (((unsigned long)buf
& 0x1) != 0) {
408 if (((unsigned long)buf
& 0x3) != 0) {
410 writew(*(u16
*)buf
, nand
);
418 writel(*(u32
*)buf
, nand
);
425 writew(*(u16
*)buf
, nand
);
435 static int arasan_nand_write_page_hwecc(struct mtd_info
*mtd
,
436 struct nand_chip
*chip
, const u8
*buf
, int oob_required
)
438 u32 reg_val
, i
, pktsize
, pktnum
;
439 const u32
*bufptr
= (const u32
*)buf
;
440 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
441 u32 size
= mtd
->writesize
;
443 u8 column_addr_cycles
;
444 struct arasan_nand_info
*nand
= nand_get_controller_data(chip
);
446 if (chip
->ecc_step_ds
>= ARASAN_NAND_PKTSIZE_1K
)
447 pktsize
= ARASAN_NAND_PKTSIZE_1K
;
449 pktsize
= ARASAN_NAND_PKTSIZE_512
;
452 pktnum
= size
/pktsize
+ 1;
454 pktnum
= size
/pktsize
;
456 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
457 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
458 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
459 reg_val
|= (pktnum
<< ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | pktsize
;
460 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
462 arasan_nand_enable_ecc();
463 column_addr_cycles
= (chip
->onfi_params
.addr_cycles
&
464 ARASAN_NAND_COL_ADDR_CYCL_MASK
) >>
465 ARASAN_NAND_COL_ADDR_CYCL_SHIFT
;
466 writel((NAND_CMD_RNDIN
| (column_addr_cycles
<< 28)),
467 &arasan_nand_base
->ecc_sprcmd_reg
);
468 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
470 while (rdcount
< pktnum
) {
471 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
472 while (!(readl(&arasan_nand_base
->intsts_reg
) &
473 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
) && timeout
) {
479 puts("arasan_write_page: timedout:Buff RDY\n");
485 if (pktnum
== rdcount
) {
486 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
487 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
488 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
490 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
491 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
492 &arasan_nand_base
->intsts_enr
);
495 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
496 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
497 &arasan_nand_base
->intsts_reg
);
499 for (i
= 0; i
< pktsize
/4; i
++)
500 writel(bufptr
[i
], &arasan_nand_base
->buf_dataport
);
504 if (rdcount
>= pktnum
)
507 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
508 &arasan_nand_base
->intsts_enr
);
511 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
513 while (!(readl(&arasan_nand_base
->intsts_reg
) &
514 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
519 puts("arasan write_page timedout:Xfer CMPLT\n");
523 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
524 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
525 &arasan_nand_base
->intsts_enr
);
526 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
527 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
528 &arasan_nand_base
->intsts_reg
);
531 chip
->ecc
.write_oob(mtd
, chip
, nand
->page
);
536 static int arasan_nand_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
539 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
540 chip
->read_buf(mtd
, chip
->oob_poi
, (mtd
->oobsize
));
545 static int arasan_nand_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
549 const u8
*buf
= chip
->oob_poi
;
551 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
552 chip
->write_buf(mtd
, buf
, mtd
->oobsize
);
557 static int arasan_nand_reset(struct arasan_nand_command_format
*curr_cmd
)
559 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
562 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
563 &arasan_nand_base
->intsts_enr
);
564 cmd_reg
= readl(&arasan_nand_base
->cmd_reg
);
565 cmd_reg
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
567 cmd_reg
|= curr_cmd
->cmd1
|
568 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
569 writel(cmd_reg
, &arasan_nand_base
->cmd_reg
);
570 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
572 while (!(readl(&arasan_nand_base
->intsts_reg
) &
573 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
578 printf("ERROR:%s timedout\n", __func__
);
582 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
583 &arasan_nand_base
->intsts_enr
);
585 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
586 &arasan_nand_base
->intsts_reg
);
591 static u8
arasan_nand_page(struct mtd_info
*mtd
)
595 switch (mtd
->writesize
) {
615 printf("%s:Pagesize>16K\n", __func__
);
622 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format
*curr_cmd
,
623 int column
, int page_addr
, struct mtd_info
*mtd
)
626 u8 page_val
, addr_cycles
;
628 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
629 &arasan_nand_base
->intsts_enr
);
630 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
631 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
632 reg_val
|= curr_cmd
->cmd1
|
633 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
634 if (curr_cmd
->cmd1
== NAND_CMD_SEQIN
) {
635 reg_val
&= ~ARASAN_NAND_CMD_PG_SIZE_MASK
;
636 page_val
= arasan_nand_page(mtd
);
637 reg_val
|= (page_val
<< ARASAN_NAND_CMD_PG_SIZE_SHIFT
);
640 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
641 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
643 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
644 return ERR_ADDR_CYCLE
;
646 reg_val
|= (addr_cycles
<<
647 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
648 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
653 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
654 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
655 column
&= ARASAN_NAND_MEM_ADDR1_COL_MASK
;
656 writel(page
|column
, &arasan_nand_base
->memadr_reg1
);
658 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
659 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
660 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
661 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
662 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
663 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
664 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
669 static void arasan_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
672 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
674 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
675 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
676 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
678 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | len
;
679 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
680 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
682 while (!(readl(&arasan_nand_base
->intsts_reg
) &
683 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
) && timeout
) {
689 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
691 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
692 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
693 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
694 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
695 &arasan_nand_base
->intsts_enr
);
696 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
697 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK
,
698 &arasan_nand_base
->intsts_reg
);
700 arasan_nand_fill_tx(buf
, len
);
702 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
703 while (!(readl(&arasan_nand_base
->intsts_reg
) &
704 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
709 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
711 writel(readl(&arasan_nand_base
->intsts_enr
) |
712 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
713 &arasan_nand_base
->intsts_enr
);
714 writel(readl(&arasan_nand_base
->intsts_reg
) |
715 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
716 &arasan_nand_base
->intsts_reg
);
719 static int arasan_nand_erase(struct arasan_nand_command_format
*curr_cmd
,
720 int column
, int page_addr
, struct mtd_info
*mtd
)
723 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
726 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
727 &arasan_nand_base
->intsts_enr
);
728 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
729 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
730 reg_val
|= curr_cmd
->cmd1
|
731 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
732 row_addr_cycles
= arasan_nand_get_addrcycle(mtd
);
734 if (row_addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
735 return ERR_ADDR_CYCLE
;
737 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
738 reg_val
|= (row_addr_cycles
<<
739 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
741 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
743 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
744 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
745 column
= page_addr
& ARASAN_NAND_MEM_ADDR1_COL_MASK
;
746 writel(page
| column
, &arasan_nand_base
->memadr_reg1
);
748 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
749 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
750 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
751 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
752 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
753 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
754 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
755 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
757 while (!(readl(&arasan_nand_base
->intsts_reg
) &
758 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
763 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__
);
767 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
768 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
769 &arasan_nand_base
->intsts_enr
);
770 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
771 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
772 &arasan_nand_base
->intsts_reg
);
777 static int arasan_nand_read_status(struct arasan_nand_command_format
*curr_cmd
,
778 int column
, int page_addr
, struct mtd_info
*mtd
)
781 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
784 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
785 &arasan_nand_base
->intsts_enr
);
786 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
787 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
788 reg_val
|= curr_cmd
->cmd1
|
789 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
790 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
792 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
793 return ERR_ADDR_CYCLE
;
795 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
796 reg_val
|= (addr_cycles
<<
797 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT
);
799 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
801 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
802 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
803 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
804 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | 1;
805 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
807 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
808 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
809 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
811 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
812 while (!(readl(&arasan_nand_base
->intsts_reg
) &
813 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
819 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__
);
823 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
824 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
825 &arasan_nand_base
->intsts_enr
);
826 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
827 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
828 &arasan_nand_base
->intsts_reg
);
833 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format
*curr_cmd
,
834 int column
, int page_addr
, struct mtd_info
*mtd
)
836 u32 reg_val
, addr_cycles
, page
;
839 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
840 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
841 &arasan_nand_base
->intsts_enr
);
843 reg_val
= readl(&arasan_nand_base
->cmd_reg
);
844 reg_val
&= ~ARASAN_NAND_CMD_CMD12_MASK
;
845 reg_val
|= curr_cmd
->cmd1
|
846 (curr_cmd
->cmd2
<< ARASAN_NAND_CMD_CMD2_SHIFT
);
848 if (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
||
849 curr_cmd
->cmd1
== NAND_CMD_READ0
) {
850 reg_val
&= ~ARASAN_NAND_CMD_PG_SIZE_MASK
;
851 page_val
= arasan_nand_page(mtd
);
852 reg_val
|= (page_val
<< ARASAN_NAND_CMD_PG_SIZE_SHIFT
);
855 reg_val
&= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK
;
857 addr_cycles
= arasan_nand_get_addrcycle(mtd
);
859 if (addr_cycles
== ARASAN_NAND_INVALID_ADDR_CYCL
)
860 return ERR_ADDR_CYCLE
;
862 reg_val
|= (addr_cycles
<< 28);
863 writel(reg_val
, &arasan_nand_base
->cmd_reg
);
868 page
= (page_addr
<< ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
) &
869 ARASAN_NAND_MEM_ADDR1_PAGE_MASK
;
870 column
&= ARASAN_NAND_MEM_ADDR1_COL_MASK
;
871 writel(page
| column
, &arasan_nand_base
->memadr_reg1
);
873 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
874 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK
;
875 reg_val
|= (page_addr
>> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT
);
876 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
878 reg_val
= readl(&arasan_nand_base
->memadr_reg2
);
879 reg_val
&= ~ARASAN_NAND_MEM_ADDR2_CS_MASK
;
880 writel(reg_val
, &arasan_nand_base
->memadr_reg2
);
886 static void arasan_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int size
)
889 u32
*bufptr
= (u32
*)buf
;
890 u32 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
892 reg_val
= readl(&arasan_nand_base
->pkt_reg
);
893 reg_val
&= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK
|
894 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK
);
895 reg_val
|= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT
) | size
;
896 writel(reg_val
, &arasan_nand_base
->pkt_reg
);
898 writel(curr_cmd
->pgm
, &arasan_nand_base
->pgm_reg
);
900 while (!(readl(&arasan_nand_base
->intsts_reg
) &
901 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
) && timeout
) {
907 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
909 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
910 reg_val
|= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
;
911 writel(reg_val
, &arasan_nand_base
->intsts_enr
);
913 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
914 &arasan_nand_base
->intsts_enr
);
915 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
916 writel(reg_val
| ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK
,
917 &arasan_nand_base
->intsts_reg
);
920 for (i
= 0; i
< size
/ 4; i
++)
921 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
924 bufptr
[i
] = readl(&arasan_nand_base
->buf_dataport
);
926 timeout
= ARASAN_NAND_POLL_TIMEOUT
;
928 while (!(readl(&arasan_nand_base
->intsts_reg
) &
929 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
) && timeout
) {
935 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
937 reg_val
= readl(&arasan_nand_base
->intsts_enr
);
938 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
939 &arasan_nand_base
->intsts_enr
);
940 reg_val
= readl(&arasan_nand_base
->intsts_reg
);
941 writel(reg_val
| ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
942 &arasan_nand_base
->intsts_reg
);
945 static u8
arasan_nand_read_byte(struct mtd_info
*mtd
)
947 struct nand_chip
*chip
= mtd_to_nand(mtd
);
950 struct nand_onfi_params
*p
;
952 if (buf_index
== 0) {
953 p
= &chip
->onfi_params
;
954 if (curr_cmd
->cmd1
== NAND_CMD_READID
)
956 else if (curr_cmd
->cmd1
== NAND_CMD_PARAM
)
957 size
= sizeof(struct nand_onfi_params
);
958 else if (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
)
959 size
= le16_to_cpu(p
->ext_param_page_length
) * 16;
960 else if (curr_cmd
->cmd1
== NAND_CMD_GET_FEATURES
)
962 else if (curr_cmd
->cmd1
== NAND_CMD_STATUS
)
963 return readb(&arasan_nand_base
->flash_sts_reg
);
966 chip
->read_buf(mtd
, &buf_data
[0], size
);
969 val
= *(&buf_data
[0] + buf_index
);
975 static void arasan_nand_cmd_function(struct mtd_info
*mtd
, unsigned int command
,
976 int column
, int page_addr
)
979 struct nand_chip
*chip
= mtd_to_nand(mtd
);
980 struct arasan_nand_info
*nand
= nand_get_controller_data(chip
);
983 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK
,
984 &arasan_nand_base
->intsts_enr
);
986 if ((command
== NAND_CMD_READOOB
) &&
987 (mtd
->writesize
> 512)) {
988 column
+= mtd
->writesize
;
989 command
= NAND_CMD_READ0
;
992 /* Get the command format */
993 for (i
= 0; (arasan_nand_commands
[i
].cmd1
!= NAND_CMD_NONE
||
994 arasan_nand_commands
[i
].cmd2
!= NAND_CMD_NONE
); i
++) {
995 if (command
== arasan_nand_commands
[i
].cmd1
) {
996 curr_cmd
= &arasan_nand_commands
[i
];
1001 if (curr_cmd
== NULL
) {
1002 printf("Unsupported Command; 0x%x\n", command
);
1006 if (curr_cmd
->cmd1
== NAND_CMD_RESET
)
1007 ret
= arasan_nand_reset(curr_cmd
);
1009 if ((curr_cmd
->cmd1
== NAND_CMD_READID
) ||
1010 (curr_cmd
->cmd1
== NAND_CMD_PARAM
) ||
1011 (curr_cmd
->cmd1
== NAND_CMD_RNDOUT
) ||
1012 (curr_cmd
->cmd1
== NAND_CMD_GET_FEATURES
) ||
1013 (curr_cmd
->cmd1
== NAND_CMD_READ0
))
1014 ret
= arasan_nand_send_rdcmd(curr_cmd
, column
, page_addr
, mtd
);
1016 if ((curr_cmd
->cmd1
== NAND_CMD_SET_FEATURES
) ||
1017 (curr_cmd
->cmd1
== NAND_CMD_SEQIN
)) {
1018 nand
->page
= page_addr
;
1019 ret
= arasan_nand_send_wrcmd(curr_cmd
, column
, page_addr
, mtd
);
1022 if (curr_cmd
->cmd1
== NAND_CMD_ERASE1
)
1023 ret
= arasan_nand_erase(curr_cmd
, column
, page_addr
, mtd
);
1025 if (curr_cmd
->cmd1
== NAND_CMD_STATUS
)
1026 ret
= arasan_nand_read_status(curr_cmd
, column
, page_addr
, mtd
);
1029 printf("ERROR:%s:command:0x%x\n", __func__
, curr_cmd
->cmd1
);
1032 static int arasan_nand_ecc_init(struct mtd_info
*mtd
)
1035 u32 regval
, eccpos_start
, i
;
1036 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1038 nand_chip
->ecc
.mode
= NAND_ECC_HW
;
1039 nand_chip
->ecc
.hwctl
= NULL
;
1040 nand_chip
->ecc
.read_page
= arasan_nand_read_page_hwecc
;
1041 nand_chip
->ecc
.write_page
= arasan_nand_write_page_hwecc
;
1042 nand_chip
->ecc
.read_oob
= arasan_nand_read_oob
;
1043 nand_chip
->ecc
.write_oob
= arasan_nand_write_oob
;
1045 for (i
= 0; i
< ARRAY_SIZE(ecc_matrix
); i
++) {
1046 if ((ecc_matrix
[i
].pagesize
== mtd
->writesize
) &&
1047 (ecc_matrix
[i
].ecc_codeword_size
>=
1048 nand_chip
->ecc_step_ds
)) {
1049 if (ecc_matrix
[i
].eccbits
>=
1050 nand_chip
->ecc_strength_ds
) {
1061 regval
= ecc_matrix
[found
].eccaddr
|
1062 (ecc_matrix
[found
].eccsize
<< ARASAN_NAND_ECC_SIZE_SHIFT
) |
1063 (ecc_matrix
[found
].bch
<< ARASAN_NAND_ECC_BCH_SHIFT
);
1064 writel(regval
, &arasan_nand_base
->ecc_reg
);
1066 if (ecc_matrix
[found
].bch
) {
1067 regval
= readl(&arasan_nand_base
->memadr_reg2
);
1068 regval
&= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK
;
1069 regval
|= (ecc_matrix
[found
].bchval
<<
1070 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT
);
1071 writel(regval
, &arasan_nand_base
->memadr_reg2
);
1074 nand_oob
.eccbytes
= ecc_matrix
[found
].eccsize
;
1075 eccpos_start
= mtd
->oobsize
- nand_oob
.eccbytes
;
1077 for (i
= 0; i
< nand_oob
.eccbytes
; i
++)
1078 nand_oob
.eccpos
[i
] = eccpos_start
+ i
;
1080 nand_oob
.oobfree
[0].offset
= 2;
1081 nand_oob
.oobfree
[0].length
= eccpos_start
- 2;
1083 nand_chip
->ecc
.size
= ecc_matrix
[found
].ecc_codeword_size
;
1084 nand_chip
->ecc
.strength
= ecc_matrix
[found
].eccbits
;
1085 nand_chip
->ecc
.bytes
= ecc_matrix
[found
].eccsize
;
1086 nand_chip
->ecc
.layout
= &nand_oob
;
1091 static int arasan_nand_init(struct nand_chip
*nand_chip
, int devnum
)
1093 struct arasan_nand_info
*nand
;
1094 struct mtd_info
*mtd
;
1097 nand
= calloc(1, sizeof(struct arasan_nand_info
));
1099 printf("%s: failed to allocate\n", __func__
);
1103 nand
->nand_base
= arasan_nand_base
;
1104 mtd
= nand_to_mtd(nand_chip
);
1105 nand_set_controller_data(nand_chip
, nand
);
1107 /* Set the driver entry points for MTD */
1108 nand_chip
->cmdfunc
= arasan_nand_cmd_function
;
1109 nand_chip
->select_chip
= arasan_nand_select_chip
;
1110 nand_chip
->read_byte
= arasan_nand_read_byte
;
1112 /* Buffer read/write routines */
1113 nand_chip
->read_buf
= arasan_nand_read_buf
;
1114 nand_chip
->write_buf
= arasan_nand_write_buf
;
1115 nand_chip
->bbt_options
= NAND_BBT_USE_FLASH
;
1117 writel(0x0, &arasan_nand_base
->cmd_reg
);
1118 writel(0x0, &arasan_nand_base
->pgm_reg
);
1120 /* first scan to find the device and get the page size */
1121 if (nand_scan_ident(mtd
, 1, NULL
)) {
1122 printf("%s: nand_scan_ident failed\n", __func__
);
1126 if (arasan_nand_ecc_init(mtd
)) {
1127 printf("%s: nand_ecc_init failed\n", __func__
);
1131 if (nand_scan_tail(mtd
)) {
1132 printf("%s: nand_scan_tail failed\n", __func__
);
1136 if (nand_register(devnum
, mtd
)) {
1137 printf("Nand Register Fail\n");
1147 void board_nand_init(void)
1149 struct nand_chip
*nand
= &nand_chip
[0];
1151 if (arasan_nand_init(nand
, 0))
1152 puts("NAND init failed\n");