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[people/ms/u-boot.git] / drivers / mtd / nand / davinci_nand.c
1 /*
2 * NAND driver for TI DaVinci based boards.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
7 */
8
9 /*
10 *
11 * linux/drivers/mtd/nand/nand_davinci.c
12 *
13 * NAND Flash Driver
14 *
15 * Copyright (C) 2006 Texas Instruments.
16 *
17 * ----------------------------------------------------------------------------
18 *
19 * SPDX-License-Identifier: GPL-2.0+
20 *
21 * ----------------------------------------------------------------------------
22 *
23 * Overview:
24 * This is a device driver for the NAND flash device found on the
25 * DaVinci board which utilizes the Samsung k9k2g08 part.
26 *
27 Modifications:
28 ver. 1.0: Feb 2005, Vinod/Sudhakar
29 -
30 */
31
32 #include <common.h>
33 #include <asm/io.h>
34 #include <nand.h>
35 #include <asm/ti-common/davinci_nand.h>
36
37 /* Definitions for 4-bit hardware ECC */
38 #define NAND_TIMEOUT 10240
39 #define NAND_ECC_BUSY 0xC
40 #define NAND_4BITECC_MASK 0x03FF03FF
41 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
42 #define ECC_STATE_NO_ERR 0x0
43 #define ECC_STATE_TOO_MANY_ERRS 0x1
44 #define ECC_STATE_ERR_CORR_COMP_P 0x2
45 #define ECC_STATE_ERR_CORR_COMP_N 0x3
46
47 /*
48 * Exploit the little endianness of the ARM to do multi-byte transfers
49 * per device read. This can perform over twice as quickly as individual
50 * byte transfers when buffer alignment is conducive.
51 *
52 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
53 * the address bus. On Davinci EVM platforms this has always been true.
54 */
55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
56 {
57 struct nand_chip *chip = mtd->priv;
58 const u32 *nand = chip->IO_ADDR_R;
59
60 /* Make sure that buf is 32 bit aligned */
61 if (((int)buf & 0x3) != 0) {
62 if (((int)buf & 0x1) != 0) {
63 if (len) {
64 *buf = readb(nand);
65 buf += 1;
66 len--;
67 }
68 }
69
70 if (((int)buf & 0x3) != 0) {
71 if (len >= 2) {
72 *(u16 *)buf = readw(nand);
73 buf += 2;
74 len -= 2;
75 }
76 }
77 }
78
79 /* copy aligned data */
80 while (len >= 4) {
81 *(u32 *)buf = __raw_readl(nand);
82 buf += 4;
83 len -= 4;
84 }
85
86 /* mop up any remaining bytes */
87 if (len) {
88 if (len >= 2) {
89 *(u16 *)buf = readw(nand);
90 buf += 2;
91 len -= 2;
92 }
93
94 if (len)
95 *buf = readb(nand);
96 }
97 }
98
99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
100 int len)
101 {
102 struct nand_chip *chip = mtd->priv;
103 const u32 *nand = chip->IO_ADDR_W;
104
105 /* Make sure that buf is 32 bit aligned */
106 if (((int)buf & 0x3) != 0) {
107 if (((int)buf & 0x1) != 0) {
108 if (len) {
109 writeb(*buf, nand);
110 buf += 1;
111 len--;
112 }
113 }
114
115 if (((int)buf & 0x3) != 0) {
116 if (len >= 2) {
117 writew(*(u16 *)buf, nand);
118 buf += 2;
119 len -= 2;
120 }
121 }
122 }
123
124 /* copy aligned data */
125 while (len >= 4) {
126 __raw_writel(*(u32 *)buf, nand);
127 buf += 4;
128 len -= 4;
129 }
130
131 /* mop up any remaining bytes */
132 if (len) {
133 if (len >= 2) {
134 writew(*(u16 *)buf, nand);
135 buf += 2;
136 len -= 2;
137 }
138
139 if (len)
140 writeb(*buf, nand);
141 }
142 }
143
144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
145 unsigned int ctrl)
146 {
147 struct nand_chip *this = mtd->priv;
148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
149
150 if (ctrl & NAND_CTRL_CHANGE) {
151 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
152
153 if (ctrl & NAND_CLE)
154 IO_ADDR_W |= MASK_CLE;
155 if (ctrl & NAND_ALE)
156 IO_ADDR_W |= MASK_ALE;
157 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
158 }
159
160 if (cmd != NAND_CMD_NONE)
161 writeb(cmd, IO_ADDR_W);
162 }
163
164 #ifdef CONFIG_SYS_NAND_HW_ECC
165
166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
167 {
168 u_int32_t ecc = 0;
169
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
171 CONFIG_SYS_NAND_CS - 2]));
172
173 return ecc;
174 }
175
176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
177 {
178 u_int32_t val;
179
180 /* reading the ECC result register resets the ECC calculation */
181 nand_davinci_readecc(mtd);
182
183 val = __raw_readl(&davinci_emif_regs->nandfcr);
184 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
185 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
186 __raw_writel(val, &davinci_emif_regs->nandfcr);
187 }
188
189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
190 u_char *ecc_code)
191 {
192 u_int32_t tmp;
193
194 tmp = nand_davinci_readecc(mtd);
195
196 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
197 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
198 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
199
200 /* Invert so that erased block ECC is correct */
201 tmp = ~tmp;
202
203 *ecc_code++ = tmp;
204 *ecc_code++ = tmp >> 8;
205 *ecc_code++ = tmp >> 16;
206
207 /* NOTE: the above code matches mainline Linux:
208 * .PQR.stu ==> ~PQRstu
209 *
210 * MontaVista/TI kernels encode those bytes differently, use
211 * complicated (and allegedly sometimes-wrong) correction code,
212 * and usually shipped with U-Boot that uses software ECC:
213 * .PQR.stu ==> PsQRtu
214 *
215 * If you need MV/TI compatible NAND I/O in U-Boot, it should
216 * be possible to (a) change the mangling above, (b) reverse
217 * that mangling in nand_davinci_correct_data() below.
218 */
219
220 return 0;
221 }
222
223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
224 u_char *read_ecc, u_char *calc_ecc)
225 {
226 struct nand_chip *this = mtd->priv;
227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
228 (read_ecc[2] << 16);
229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
230 (calc_ecc[2] << 16);
231 u_int32_t diff = ecc_calc ^ ecc_nand;
232
233 if (diff) {
234 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
235 /* Correctable error */
236 if ((diff >> (12 + 3)) < this->ecc.size) {
237 uint8_t find_bit = 1 << ((diff >> 12) & 7);
238 uint32_t find_byte = diff >> (12 + 3);
239
240 dat[find_byte] ^= find_bit;
241 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
242 "bit ECC error at offset: %d, bit: "
243 "%d\n", find_byte, find_bit);
244 return 1;
245 } else {
246 return -1;
247 }
248 } else if (!(diff & (diff - 1))) {
249 /* Single bit ECC error in the ECC itself,
250 nothing to fix */
251 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
252 "ECC.\n");
253 return 1;
254 } else {
255 /* Uncorrectable error */
256 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
257 return -1;
258 }
259 }
260 return 0;
261 }
262 #endif /* CONFIG_SYS_NAND_HW_ECC */
263
264 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
265 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
266 #if defined(CONFIG_SYS_NAND_PAGE_2K)
267 .eccbytes = 40,
268 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
269 .eccpos = {
270 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
271 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
272 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
273 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
274 },
275 .oobfree = {
276 {2, 4}, {16, 6}, {32, 6}, {48, 6},
277 },
278 #else
279 .eccpos = {
280 24, 25, 26, 27, 28,
281 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
282 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
283 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
284 59, 60, 61, 62, 63,
285 },
286 .oobfree = {
287 {.offset = 2, .length = 22, },
288 },
289 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
290 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
291 .eccbytes = 80,
292 .eccpos = {
293 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
294 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
295 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
296 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
297 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
298 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
299 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
300 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
301 },
302 .oobfree = {
303 {.offset = 2, .length = 46, },
304 },
305 #endif
306 };
307
308 #if defined CONFIG_KEYSTONE_RBL_NAND
309 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
310 #if defined(CONFIG_SYS_NAND_PAGE_2K)
311 .eccbytes = 40,
312 .eccpos = {
313 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
314 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
315 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
316 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
317 },
318 .oobfree = {
319 {.offset = 2, .length = 4, },
320 {.offset = 16, .length = 6, },
321 {.offset = 32, .length = 6, },
322 {.offset = 48, .length = 6, },
323 },
324 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
325 .eccbytes = 80,
326 .eccpos = {
327 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
328 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
329 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
330 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
331 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
332 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
333 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
334 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
335 },
336 .oobfree = {
337 {.offset = 2, .length = 4, },
338 {.offset = 16, .length = 6, },
339 {.offset = 32, .length = 6, },
340 {.offset = 48, .length = 6, },
341 {.offset = 64, .length = 6, },
342 {.offset = 80, .length = 6, },
343 {.offset = 96, .length = 6, },
344 {.offset = 112, .length = 6, },
345 },
346 #endif
347 };
348
349 #ifdef CONFIG_SYS_NAND_PAGE_2K
350 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
351 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
352 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
353 #endif
354
355 /**
356 * nand_davinci_write_page - write one page
357 * @mtd: MTD device structure
358 * @chip: NAND chip descriptor
359 * @buf: the data to write
360 * @oob_required: must write chip->oob_poi to OOB
361 * @page: page number to write
362 * @cached: cached programming
363 * @raw: use _raw version of write_page
364 */
365 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
366 uint32_t offset, int data_len,
367 const uint8_t *buf, int oob_required,
368 int page, int cached, int raw)
369 {
370 int status;
371 int ret = 0;
372 struct nand_ecclayout *saved_ecc_layout;
373
374 /* save current ECC layout and assign Keystone RBL ECC layout */
375 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
376 saved_ecc_layout = chip->ecc.layout;
377 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
378 mtd->oobavail = chip->ecc.layout->oobavail;
379 }
380
381 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
382
383 if (unlikely(raw))
384 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
385 else
386 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
387
388 if (status < 0) {
389 ret = status;
390 goto err;
391 }
392
393 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
394 status = chip->waitfunc(mtd, chip);
395
396 /*
397 * See if operation failed and additional status checks are
398 * available.
399 */
400 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
401 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
402
403 if (status & NAND_STATUS_FAIL) {
404 ret = -EIO;
405 goto err;
406 }
407
408 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
409 /* Send command to read back the data */
410 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
411
412 if (chip->verify_buf(mtd, buf, mtd->writesize)) {
413 ret = -EIO;
414 goto err;
415 }
416
417 /* Make sure the next page prog is preceded by a status read */
418 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
419 #endif
420 err:
421 /* restore ECC layout */
422 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
423 chip->ecc.layout = saved_ecc_layout;
424 mtd->oobavail = saved_ecc_layout->oobavail;
425 }
426
427 return ret;
428 }
429
430 /**
431 * nand_davinci_read_page_hwecc - hardware ECC based page read function
432 * @mtd: mtd info structure
433 * @chip: nand chip info structure
434 * @buf: buffer to store read data
435 * @oob_required: caller requires OOB data read to chip->oob_poi
436 * @page: page number to read
437 *
438 * Not for syndrome calculating ECC controllers which need a special oob layout.
439 */
440 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
441 uint8_t *buf, int oob_required, int page)
442 {
443 int i, eccsize = chip->ecc.size;
444 int eccbytes = chip->ecc.bytes;
445 int eccsteps = chip->ecc.steps;
446 uint32_t *eccpos;
447 uint8_t *p = buf;
448 uint8_t *ecc_code = chip->buffers->ecccode;
449 uint8_t *ecc_calc = chip->buffers->ecccalc;
450 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
451
452 /* save current ECC layout and assign Keystone RBL ECC layout */
453 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
454 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
455 mtd->oobavail = chip->ecc.layout->oobavail;
456 }
457
458 eccpos = chip->ecc.layout->eccpos;
459
460 /* Read the OOB area first */
461 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
462 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
463 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
464
465 for (i = 0; i < chip->ecc.total; i++)
466 ecc_code[i] = chip->oob_poi[eccpos[i]];
467
468 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
469 int stat;
470
471 chip->ecc.hwctl(mtd, NAND_ECC_READ);
472 chip->read_buf(mtd, p, eccsize);
473 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
474
475 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
476 if (stat < 0)
477 mtd->ecc_stats.failed++;
478 else
479 mtd->ecc_stats.corrected += stat;
480 }
481
482 /* restore ECC layout */
483 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
484 chip->ecc.layout = saved_ecc_layout;
485 mtd->oobavail = saved_ecc_layout->oobavail;
486 }
487
488 return 0;
489 }
490 #endif /* CONFIG_KEYSTONE_RBL_NAND */
491
492 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
493 {
494 u32 val;
495
496 switch (mode) {
497 case NAND_ECC_WRITE:
498 case NAND_ECC_READ:
499 /*
500 * Start a new ECC calculation for reading or writing 512 bytes
501 * of data.
502 */
503 val = __raw_readl(&davinci_emif_regs->nandfcr);
504 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
505 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
506 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
507 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
508 __raw_writel(val, &davinci_emif_regs->nandfcr);
509 break;
510 case NAND_ECC_READSYN:
511 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
512 break;
513 default:
514 break;
515 }
516 }
517
518 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
519 {
520 int i;
521
522 for (i = 0; i < 4; i++) {
523 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
524 NAND_4BITECC_MASK;
525 }
526
527 return 0;
528 }
529
530 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
531 const uint8_t *dat,
532 uint8_t *ecc_code)
533 {
534 unsigned int hw_4ecc[4];
535 unsigned int i;
536
537 nand_davinci_4bit_readecc(mtd, hw_4ecc);
538
539 /*Convert 10 bit ecc value to 8 bit */
540 for (i = 0; i < 2; i++) {
541 unsigned int hw_ecc_low = hw_4ecc[i * 2];
542 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
543
544 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
545 *ecc_code++ = hw_ecc_low & 0xFF;
546
547 /*
548 * Take 2 bits as LSB bits from val1 (count1=0) or val5
549 * (count1=1) and 6 bits from val2 (count1=0) or
550 * val5 (count1=1)
551 */
552 *ecc_code++ =
553 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
554
555 /*
556 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
557 * 4 bits from val3 (count1=0) or val6 (count1=1)
558 */
559 *ecc_code++ =
560 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
561
562 /*
563 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
564 * 2 bits from val4 (count1=0) or val7 (count1=1)
565 */
566 *ecc_code++ =
567 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
568
569 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
570 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
571 }
572
573 return 0;
574 }
575
576 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
577 uint8_t *read_ecc, uint8_t *calc_ecc)
578 {
579 int i;
580 unsigned int hw_4ecc[4];
581 unsigned int iserror;
582 unsigned short *ecc16;
583 unsigned int numerrors, erroraddress, errorvalue;
584 u32 val;
585
586 /*
587 * Check for an ECC where all bytes are 0xFF. If this is the case, we
588 * will assume we are looking at an erased page and we should ignore
589 * the ECC.
590 */
591 for (i = 0; i < 10; i++) {
592 if (read_ecc[i] != 0xFF)
593 break;
594 }
595 if (i == 10)
596 return 0;
597
598 /* Convert 8 bit in to 10 bit */
599 ecc16 = (unsigned short *)&read_ecc[0];
600
601 /*
602 * Write the parity values in the NAND Flash 4-bit ECC Load register.
603 * Write each parity value one at a time starting from 4bit_ecc_val8
604 * to 4bit_ecc_val1.
605 */
606
607 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
608 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
609 &davinci_emif_regs->nand4biteccload);
610
611 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
612 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
613 &davinci_emif_regs->nand4biteccload);
614
615 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
616 __raw_writel((ecc16[3] >> 2) & 0x3FF,
617 &davinci_emif_regs->nand4biteccload);
618
619 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
620 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
621 &davinci_emif_regs->nand4biteccload);
622
623 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
624 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
625 &davinci_emif_regs->nand4biteccload);
626
627 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
628 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
629 &davinci_emif_regs->nand4biteccload);
630
631 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
632 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
633 &davinci_emif_regs->nand4biteccload);
634
635 /* Take 10 bits from 0th and 1st bytes */
636 __raw_writel((ecc16[0]) & 0x3FF,
637 &davinci_emif_regs->nand4biteccload);
638
639 /*
640 * Perform a dummy read to the EMIF Revision Code and Status register.
641 * This is required to ensure time for syndrome calculation after
642 * writing the ECC values in previous step.
643 */
644
645 val = __raw_readl(&davinci_emif_regs->nandfsr);
646
647 /*
648 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
649 * A syndrome value of 0 means no bit errors. If the syndrome is
650 * non-zero then go further otherwise return.
651 */
652 nand_davinci_4bit_readecc(mtd, hw_4ecc);
653
654 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
655 return 0;
656
657 /*
658 * Clear any previous address calculation by doing a dummy read of an
659 * error address register.
660 */
661 val = __raw_readl(&davinci_emif_regs->nanderradd1);
662
663 /*
664 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
665 * register to 1.
666 */
667 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
668 &davinci_emif_regs->nandfcr);
669
670 /*
671 * Wait for the corr_state field (bits 8 to 11) in the
672 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
673 * Otherwise ECC calculation has not even begun and the next loop might
674 * fail because of a false positive!
675 */
676 i = NAND_TIMEOUT;
677 do {
678 val = __raw_readl(&davinci_emif_regs->nandfsr);
679 val &= 0xc00;
680 i--;
681 } while ((i > 0) && !val);
682
683 /*
684 * Wait for the corr_state field (bits 8 to 11) in the
685 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
686 */
687 i = NAND_TIMEOUT;
688 do {
689 val = __raw_readl(&davinci_emif_regs->nandfsr);
690 val &= 0xc00;
691 i--;
692 } while ((i > 0) && val);
693
694 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
695 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
696 iserror = iserror >> 8;
697
698 /*
699 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
700 * corrected (five or more errors). The number of errors
701 * calculated (err_num field) differs from the number of errors
702 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
703 * correction complete (errors on bit 8 or 9).
704 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
705 * complete (error exists).
706 */
707
708 if (iserror == ECC_STATE_NO_ERR) {
709 val = __raw_readl(&davinci_emif_regs->nanderrval1);
710 return 0;
711 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
712 val = __raw_readl(&davinci_emif_regs->nanderrval1);
713 return -1;
714 }
715
716 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
717 & 0x3) + 1;
718
719 /* Read the error address, error value and correct */
720 for (i = 0; i < numerrors; i++) {
721 if (i > 1) {
722 erroraddress =
723 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
724 (16 * (i & 1))) & 0x3FF);
725 erroraddress = ((512 + 7) - erroraddress);
726 errorvalue =
727 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
728 (16 * (i & 1))) & 0xFF);
729 } else {
730 erroraddress =
731 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
732 (16 * (i & 1))) & 0x3FF);
733 erroraddress = ((512 + 7) - erroraddress);
734 errorvalue =
735 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
736 (16 * (i & 1))) & 0xFF);
737 }
738 /* xor the corrupt data with error value */
739 if (erroraddress < 512)
740 dat[erroraddress] ^= errorvalue;
741 }
742
743 return numerrors;
744 }
745 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
746
747 static int nand_davinci_dev_ready(struct mtd_info *mtd)
748 {
749 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
750 }
751
752 static void nand_flash_init(void)
753 {
754 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
755 * Instead, have your board_init() set EMIF timings, based on its
756 * knowledge of the clocks and what devices are hooked up ... and
757 * don't even do that unless no UBL handled it.
758 */
759 #ifdef CONFIG_SOC_DM644X
760 u_int32_t acfg1 = 0x3ffffffc;
761
762 /*------------------------------------------------------------------*
763 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
764 * *
765 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
766 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
767 * *
768 *------------------------------------------------------------------*/
769 acfg1 = 0
770 | (0 << 31) /* selectStrobe */
771 | (0 << 30) /* extWait */
772 | (1 << 26) /* writeSetup 10 ns */
773 | (3 << 20) /* writeStrobe 40 ns */
774 | (1 << 17) /* writeHold 10 ns */
775 | (1 << 13) /* readSetup 10 ns */
776 | (5 << 7) /* readStrobe 60 ns */
777 | (1 << 4) /* readHold 10 ns */
778 | (3 << 2) /* turnAround ?? ns */
779 | (0 << 0) /* asyncSize 8-bit bus */
780 ;
781
782 __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
783
784 /* NAND flash on CS2 */
785 __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
786 #endif
787 }
788
789 void davinci_nand_init(struct nand_chip *nand)
790 {
791 #if defined CONFIG_KEYSTONE_RBL_NAND
792 int i;
793 struct nand_ecclayout *layout;
794
795 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
796 layout->oobavail = 0;
797 for (i = 0; layout->oobfree[i].length &&
798 i < ARRAY_SIZE(layout->oobfree); i++)
799 layout->oobavail += layout->oobfree[i].length;
800
801 nand->write_page = nand_davinci_write_page;
802 nand->ecc.read_page = nand_davinci_read_page_hwecc;
803 #endif
804 nand->chip_delay = 0;
805 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
806 nand->bbt_options |= NAND_BBT_USE_FLASH;
807 #endif
808 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
809 nand->options |= NAND_NO_SUBPAGE_WRITE;
810 #endif
811 #ifdef CONFIG_SYS_NAND_HW_ECC
812 nand->ecc.mode = NAND_ECC_HW;
813 nand->ecc.size = 512;
814 nand->ecc.bytes = 3;
815 nand->ecc.strength = 1;
816 nand->ecc.calculate = nand_davinci_calculate_ecc;
817 nand->ecc.correct = nand_davinci_correct_data;
818 nand->ecc.hwctl = nand_davinci_enable_hwecc;
819 #else
820 nand->ecc.mode = NAND_ECC_SOFT;
821 #endif /* CONFIG_SYS_NAND_HW_ECC */
822 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
823 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
824 nand->ecc.size = 512;
825 nand->ecc.bytes = 10;
826 nand->ecc.strength = 4;
827 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
828 nand->ecc.correct = nand_davinci_4bit_correct_data;
829 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
830 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
831 #endif
832 /* Set address of hardware control function */
833 nand->cmd_ctrl = nand_davinci_hwcontrol;
834
835 nand->read_buf = nand_davinci_read_buf;
836 nand->write_buf = nand_davinci_write_buf;
837
838 nand->dev_ready = nand_davinci_dev_ready;
839
840 nand_flash_init();
841 }
842
843 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
844
845 int board_nand_init(struct nand_chip *chip)
846 {
847 davinci_nand_init(chip);
848 return 0;
849 }
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