1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
3 * Copyright (c) 2006-2008 Freescale Semiconductor
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
31 #include <asm/errno.h>
35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
37 #define vdbg(format, arg...) do {} while (0)
40 /* Can't use plain old DEBUG because the linux mtd
41 * headers define it as a macro.
44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
46 #define dbg(format, arg...) do {} while (0)
50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
57 /* mtd information per set */
61 struct nand_chip chip
;
62 struct fsl_elbc_ctrl
*ctrl
;
65 int bank
; /* Chip select bank number */
66 u8 __iomem
*vbase
; /* Chip select base virtual address */
67 int page_size
; /* NAND page size (0=512, 1=2048) */
68 unsigned int fmr
; /* FCM Flash Mode Register value */
71 /* overview of the fsl elbc controller */
73 struct fsl_elbc_ctrl
{
74 struct nand_hw_control controller
;
75 struct fsl_elbc_mtd
*chips
[MAX_BANKS
];
79 u8 __iomem
*addr
; /* Address of assigned FCM buffer */
80 unsigned int page
; /* Last page written to / read from */
81 unsigned int read_bytes
; /* Number of bytes read during command */
82 unsigned int column
; /* Saved column from SEQIN */
83 unsigned int index
; /* Pointer to next byte to 'read' */
84 unsigned int status
; /* status read from LTESR after last op */
85 unsigned int mdr
; /* UPM/FCM Data Register value */
86 unsigned int use_mdr
; /* Non zero if the MDR is to be set */
87 unsigned int oob
; /* Non zero if operating on OOB data */
88 uint8_t *oob_poi
; /* Place to write ECC after read back */
91 /* These map to the positions used by the FCM hardware ECC generator */
93 /* Small Page FLASH with FMR[ECCM] = 0 */
94 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0
= {
97 .oobfree
= { {0, 5}, {9, 7} },
100 /* Small Page FLASH with FMR[ECCM] = 1 */
101 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1
= {
103 .eccpos
= {8, 9, 10},
104 .oobfree
= { {0, 5}, {6, 2}, {11, 5} },
107 /* Large Page FLASH with FMR[ECCM] = 0 */
108 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0
= {
110 .eccpos
= {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
111 .oobfree
= { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
114 /* Large Page FLASH with FMR[ECCM] = 1 */
115 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1
= {
117 .eccpos
= {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
118 .oobfree
= { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
122 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
123 * 1, so we have to adjust bad block pattern. This pattern should be used for
124 * x8 chips only. So far hardware does not support x16 chips anyway.
126 static u8 scan_ff_pattern
[] = { 0xff, };
128 static struct nand_bbt_descr largepage_memorybased
= {
132 .pattern
= scan_ff_pattern
,
136 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
137 * interfere with ECC positions, that's why we implement our own descriptors.
138 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
140 static u8 bbt_pattern
[] = {'B', 'b', 't', '0' };
141 static u8 mirror_pattern
[] = {'1', 't', 'b', 'B' };
143 static struct nand_bbt_descr bbt_main_descr
= {
144 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
145 NAND_BBT_2BIT
| NAND_BBT_VERSION
,
150 .pattern
= bbt_pattern
,
153 static struct nand_bbt_descr bbt_mirror_descr
= {
154 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
155 NAND_BBT_2BIT
| NAND_BBT_VERSION
,
160 .pattern
= mirror_pattern
,
163 /*=================================*/
166 * Set up the FCM hardware block and page address fields, and the fcm
167 * structure addr field to point to the correct FCM buffer in memory
169 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
, int oob
)
171 struct nand_chip
*chip
= mtd
->priv
;
172 struct fsl_elbc_mtd
*priv
= chip
->priv
;
173 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
174 fsl_lbc_t
*lbc
= ctrl
->regs
;
177 ctrl
->page
= page_addr
;
179 if (priv
->page_size
) {
180 out_be32(&lbc
->fbar
, page_addr
>> 6);
182 ((page_addr
<< FPAR_LP_PI_SHIFT
) & FPAR_LP_PI
) |
183 (oob
? FPAR_LP_MS
: 0) | column
);
184 buf_num
= (page_addr
& 1) << 2;
186 out_be32(&lbc
->fbar
, page_addr
>> 5);
188 ((page_addr
<< FPAR_SP_PI_SHIFT
) & FPAR_SP_PI
) |
189 (oob
? FPAR_SP_MS
: 0) | column
);
190 buf_num
= page_addr
& 7;
193 ctrl
->addr
= priv
->vbase
+ buf_num
* 1024;
194 ctrl
->index
= column
;
196 /* for OOB data point to the second half of the buffer */
198 ctrl
->index
+= priv
->page_size
? 2048 : 512;
200 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
201 "index %x, pes %d ps %d\n",
202 buf_num
, ctrl
->addr
, priv
->vbase
, ctrl
->index
,
203 chip
->phys_erase_shift
, chip
->page_shift
);
207 * execute FCM command and wait for it to complete
209 static int fsl_elbc_run_command(struct mtd_info
*mtd
)
211 struct nand_chip
*chip
= mtd
->priv
;
212 struct fsl_elbc_mtd
*priv
= chip
->priv
;
213 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
214 fsl_lbc_t
*lbc
= ctrl
->regs
;
218 /* Setup the FMR[OP] to execute without write protection */
219 out_be32(&lbc
->fmr
, priv
->fmr
| 3);
221 out_be32(&lbc
->mdr
, ctrl
->mdr
);
223 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
224 in_be32(&lbc
->fmr
), in_be32(&lbc
->fir
), in_be32(&lbc
->fcr
));
225 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
226 "fbcr=%08x bank=%d\n",
227 in_be32(&lbc
->fbar
), in_be32(&lbc
->fpar
),
228 in_be32(&lbc
->fbcr
), priv
->bank
);
230 /* execute special operation */
231 out_be32(&lbc
->lsor
, priv
->bank
);
233 /* wait for FCM complete flag or timeout */
234 end_tick
= usec2ticks(FCM_TIMEOUT_MSECS
* 1000) + get_ticks();
237 while (end_tick
> get_ticks()) {
238 ltesr
= in_be32(&lbc
->ltesr
);
239 if (ltesr
& LTESR_CC
)
243 ctrl
->status
= ltesr
& LTESR_NAND_MASK
;
244 out_be32(&lbc
->ltesr
, ctrl
->status
);
245 out_be32(&lbc
->lteatr
, 0);
247 /* store mdr value in case it was needed */
249 ctrl
->mdr
= in_be32(&lbc
->mdr
);
253 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
254 ctrl
->status
, ctrl
->mdr
, in_be32(&lbc
->fmr
));
256 /* returns 0 on success otherwise non-zero) */
257 return ctrl
->status
== LTESR_CC
? 0 : -EIO
;
260 static void fsl_elbc_do_read(struct nand_chip
*chip
, int oob
)
262 struct fsl_elbc_mtd
*priv
= chip
->priv
;
263 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
264 fsl_lbc_t
*lbc
= ctrl
->regs
;
266 if (priv
->page_size
) {
268 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
269 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
270 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
271 (FIR_OP_CW1
<< FIR_OP3_SHIFT
) |
272 (FIR_OP_RBW
<< FIR_OP4_SHIFT
));
274 out_be32(&lbc
->fcr
, (NAND_CMD_READ0
<< FCR_CMD0_SHIFT
) |
275 (NAND_CMD_READSTART
<< FCR_CMD1_SHIFT
));
278 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
279 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
280 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
281 (FIR_OP_RBW
<< FIR_OP3_SHIFT
));
285 NAND_CMD_READOOB
<< FCR_CMD0_SHIFT
);
287 out_be32(&lbc
->fcr
, NAND_CMD_READ0
<< FCR_CMD0_SHIFT
);
291 /* cmdfunc send commands to the FCM */
292 static void fsl_elbc_cmdfunc(struct mtd_info
*mtd
, unsigned int command
,
293 int column
, int page_addr
)
295 struct nand_chip
*chip
= mtd
->priv
;
296 struct fsl_elbc_mtd
*priv
= chip
->priv
;
297 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
298 fsl_lbc_t
*lbc
= ctrl
->regs
;
302 /* clear the read buffer */
303 ctrl
->read_bytes
= 0;
304 if (command
!= NAND_CMD_PAGEPROG
)
308 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
314 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
315 " 0x%x, column: 0x%x.\n", page_addr
, column
);
317 out_be32(&lbc
->fbcr
, 0); /* read entire page to enable ECC */
318 set_addr(mtd
, 0, page_addr
, 0);
320 ctrl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
321 ctrl
->index
+= column
;
323 fsl_elbc_do_read(chip
, 0);
324 fsl_elbc_run_command(mtd
);
327 /* READOOB reads only the OOB because no ECC is performed. */
328 case NAND_CMD_READOOB
:
329 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
330 " 0x%x, column: 0x%x.\n", page_addr
, column
);
332 out_be32(&lbc
->fbcr
, mtd
->oobsize
- column
);
333 set_addr(mtd
, column
, page_addr
, 1);
335 ctrl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
337 fsl_elbc_do_read(chip
, 1);
338 fsl_elbc_run_command(mtd
);
342 /* READID must read all 5 possible bytes while CEB is active */
343 case NAND_CMD_READID
:
344 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
346 out_be32(&lbc
->fir
, (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
347 (FIR_OP_UA
<< FIR_OP1_SHIFT
) |
348 (FIR_OP_RBW
<< FIR_OP2_SHIFT
));
349 out_be32(&lbc
->fcr
, NAND_CMD_READID
<< FCR_CMD0_SHIFT
);
350 /* 5 bytes for manuf, device and exts */
351 out_be32(&lbc
->fbcr
, 5);
352 ctrl
->read_bytes
= 5;
356 set_addr(mtd
, 0, 0, 0);
357 fsl_elbc_run_command(mtd
);
360 /* ERASE1 stores the block and page address */
361 case NAND_CMD_ERASE1
:
362 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
363 "page_addr: 0x%x.\n", page_addr
);
364 set_addr(mtd
, 0, page_addr
, 0);
367 /* ERASE2 uses the block and page address from ERASE1 */
368 case NAND_CMD_ERASE2
:
369 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
372 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
373 (FIR_OP_PA
<< FIR_OP1_SHIFT
) |
374 (FIR_OP_CM1
<< FIR_OP2_SHIFT
));
377 (NAND_CMD_ERASE1
<< FCR_CMD0_SHIFT
) |
378 (NAND_CMD_ERASE2
<< FCR_CMD1_SHIFT
));
380 out_be32(&lbc
->fbcr
, 0);
381 ctrl
->read_bytes
= 0;
383 fsl_elbc_run_command(mtd
);
386 /* SEQIN sets up the addr buffer and all registers except the length */
387 case NAND_CMD_SEQIN
: {
389 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
390 "page_addr: 0x%x, column: 0x%x.\n",
393 ctrl
->column
= column
;
396 if (priv
->page_size
) {
397 fcr
= (NAND_CMD_SEQIN
<< FCR_CMD0_SHIFT
) |
398 (NAND_CMD_PAGEPROG
<< FCR_CMD1_SHIFT
);
401 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
402 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
403 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
404 (FIR_OP_WB
<< FIR_OP3_SHIFT
) |
405 (FIR_OP_CW1
<< FIR_OP4_SHIFT
));
407 fcr
= (NAND_CMD_PAGEPROG
<< FCR_CMD1_SHIFT
) |
408 (NAND_CMD_SEQIN
<< FCR_CMD2_SHIFT
);
411 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
412 (FIR_OP_CM2
<< FIR_OP1_SHIFT
) |
413 (FIR_OP_CA
<< FIR_OP2_SHIFT
) |
414 (FIR_OP_PA
<< FIR_OP3_SHIFT
) |
415 (FIR_OP_WB
<< FIR_OP4_SHIFT
) |
416 (FIR_OP_CW1
<< FIR_OP5_SHIFT
));
418 if (column
>= mtd
->writesize
) {
419 /* OOB area --> READOOB */
420 column
-= mtd
->writesize
;
421 fcr
|= NAND_CMD_READOOB
<< FCR_CMD0_SHIFT
;
423 } else if (column
< 256) {
424 /* First 256 bytes --> READ0 */
425 fcr
|= NAND_CMD_READ0
<< FCR_CMD0_SHIFT
;
427 /* Second 256 bytes --> READ1 */
428 fcr
|= NAND_CMD_READ1
<< FCR_CMD0_SHIFT
;
432 out_be32(&lbc
->fcr
, fcr
);
433 set_addr(mtd
, column
, page_addr
, ctrl
->oob
);
437 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
438 case NAND_CMD_PAGEPROG
: {
440 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
441 "writing %d bytes.\n", ctrl
->index
);
443 /* if the write did not start at 0 or is not a full page
444 * then set the exact length, otherwise use a full page
445 * write so the HW generates the ECC.
447 if (ctrl
->oob
|| ctrl
->column
!= 0 ||
448 ctrl
->index
!= mtd
->writesize
+ mtd
->oobsize
) {
449 out_be32(&lbc
->fbcr
, ctrl
->index
);
452 out_be32(&lbc
->fbcr
, 0);
456 fsl_elbc_run_command(mtd
);
458 /* Read back the page in order to fill in the ECC for the
459 * caller. Is this really needed?
461 if (full_page
&& ctrl
->oob_poi
) {
462 out_be32(&lbc
->fbcr
, 3);
463 set_addr(mtd
, 6, page_addr
, 1);
465 ctrl
->read_bytes
= mtd
->writesize
+ 9;
467 fsl_elbc_do_read(chip
, 1);
468 fsl_elbc_run_command(mtd
);
470 memcpy_fromio(ctrl
->oob_poi
+ 6,
471 &ctrl
->addr
[ctrl
->index
], 3);
475 ctrl
->oob_poi
= NULL
;
479 /* CMD_STATUS must read the status byte while CEB is active */
480 /* Note - it does not wait for the ready line */
481 case NAND_CMD_STATUS
:
483 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
484 (FIR_OP_RBW
<< FIR_OP1_SHIFT
));
485 out_be32(&lbc
->fcr
, NAND_CMD_STATUS
<< FCR_CMD0_SHIFT
);
486 out_be32(&lbc
->fbcr
, 1);
487 set_addr(mtd
, 0, 0, 0);
488 ctrl
->read_bytes
= 1;
490 fsl_elbc_run_command(mtd
);
492 /* The chip always seems to report that it is
493 * write-protected, even when it is not.
495 out_8(ctrl
->addr
, in_8(ctrl
->addr
) | NAND_STATUS_WP
);
498 /* RESET without waiting for the ready line */
500 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
501 out_be32(&lbc
->fir
, FIR_OP_CM0
<< FIR_OP0_SHIFT
);
502 out_be32(&lbc
->fcr
, NAND_CMD_RESET
<< FCR_CMD0_SHIFT
);
503 fsl_elbc_run_command(mtd
);
507 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
512 static void fsl_elbc_select_chip(struct mtd_info
*mtd
, int chip
)
514 /* The hardware does not seem to support multiple
520 * Write buf to the FCM Controller Data Buffer
522 static void fsl_elbc_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
524 struct nand_chip
*chip
= mtd
->priv
;
525 struct fsl_elbc_mtd
*priv
= chip
->priv
;
526 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
527 unsigned int bufsize
= mtd
->writesize
+ mtd
->oobsize
;
530 printf("write_buf of %d bytes", len
);
535 if ((unsigned int)len
> bufsize
- ctrl
->index
) {
536 printf("write_buf beyond end of buffer "
537 "(%d requested, %u available)\n",
538 len
, bufsize
- ctrl
->index
);
539 len
= bufsize
- ctrl
->index
;
542 memcpy_toio(&ctrl
->addr
[ctrl
->index
], buf
, len
);
544 * This is workaround for the weird elbc hangs during nand write,
545 * Scott Wood says: "...perhaps difference in how long it takes a
546 * write to make it through the localbus compared to a write to IMMR
547 * is causing problems, and sync isn't helping for some reason."
548 * Reading back the last byte helps though.
550 in_8(&ctrl
->addr
[ctrl
->index
] + len
- 1);
556 * read a byte from either the FCM hardware buffer if it has any data left
557 * otherwise issue a command to read a single byte.
559 static u8
fsl_elbc_read_byte(struct mtd_info
*mtd
)
561 struct nand_chip
*chip
= mtd
->priv
;
562 struct fsl_elbc_mtd
*priv
= chip
->priv
;
563 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
565 /* If there are still bytes in the FCM, then use the next byte. */
566 if (ctrl
->index
< ctrl
->read_bytes
)
567 return in_8(&ctrl
->addr
[ctrl
->index
++]);
569 printf("read_byte beyond end of buffer\n");
574 * Read from the FCM Controller Data Buffer
576 static void fsl_elbc_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
578 struct nand_chip
*chip
= mtd
->priv
;
579 struct fsl_elbc_mtd
*priv
= chip
->priv
;
580 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
586 avail
= min((unsigned int)len
, ctrl
->read_bytes
- ctrl
->index
);
587 memcpy_fromio(buf
, &ctrl
->addr
[ctrl
->index
], avail
);
588 ctrl
->index
+= avail
;
591 printf("read_buf beyond end of buffer "
592 "(%d requested, %d available)\n",
597 * Verify buffer against the FCM Controller Data Buffer
599 static int fsl_elbc_verify_buf(struct mtd_info
*mtd
,
600 const u_char
*buf
, int len
)
602 struct nand_chip
*chip
= mtd
->priv
;
603 struct fsl_elbc_mtd
*priv
= chip
->priv
;
604 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
608 printf("write_buf of %d bytes", len
);
612 if ((unsigned int)len
> ctrl
->read_bytes
- ctrl
->index
) {
613 printf("verify_buf beyond end of buffer "
614 "(%d requested, %u available)\n",
615 len
, ctrl
->read_bytes
- ctrl
->index
);
617 ctrl
->index
= ctrl
->read_bytes
;
621 for (i
= 0; i
< len
; i
++)
622 if (in_8(&ctrl
->addr
[ctrl
->index
+ i
]) != buf
[i
])
626 return i
== len
&& ctrl
->status
== LTESR_CC
? 0 : -EIO
;
629 /* This function is called after Program and Erase Operations to
630 * check for success or failure.
632 static int fsl_elbc_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
634 struct fsl_elbc_mtd
*priv
= chip
->priv
;
635 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
636 fsl_lbc_t
*lbc
= ctrl
->regs
;
638 if (ctrl
->status
!= LTESR_CC
)
639 return NAND_STATUS_FAIL
;
641 /* Use READ_STATUS command, but wait for the device to be ready */
644 (FIR_OP_CW0
<< FIR_OP0_SHIFT
) |
645 (FIR_OP_RBW
<< FIR_OP1_SHIFT
));
646 out_be32(&lbc
->fcr
, NAND_CMD_STATUS
<< FCR_CMD0_SHIFT
);
647 out_be32(&lbc
->fbcr
, 1);
648 set_addr(mtd
, 0, 0, 0);
649 ctrl
->read_bytes
= 1;
651 fsl_elbc_run_command(mtd
);
653 if (ctrl
->status
!= LTESR_CC
)
654 return NAND_STATUS_FAIL
;
656 /* The chip always seems to report that it is
657 * write-protected, even when it is not.
659 out_8(ctrl
->addr
, in_8(ctrl
->addr
) | NAND_STATUS_WP
);
660 return fsl_elbc_read_byte(mtd
);
663 static int fsl_elbc_read_page(struct mtd_info
*mtd
,
664 struct nand_chip
*chip
,
665 uint8_t *buf
, int page
)
667 fsl_elbc_read_buf(mtd
, buf
, mtd
->writesize
);
668 fsl_elbc_read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
670 if (fsl_elbc_wait(mtd
, chip
) & NAND_STATUS_FAIL
)
671 mtd
->ecc_stats
.failed
++;
676 /* ECC will be calculated automatically, and errors will be detected in
679 static void fsl_elbc_write_page(struct mtd_info
*mtd
,
680 struct nand_chip
*chip
,
683 struct fsl_elbc_mtd
*priv
= chip
->priv
;
684 struct fsl_elbc_ctrl
*ctrl
= priv
->ctrl
;
686 fsl_elbc_write_buf(mtd
, buf
, mtd
->writesize
);
687 fsl_elbc_write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
689 ctrl
->oob_poi
= chip
->oob_poi
;
692 static struct fsl_elbc_ctrl
*elbc_ctrl
;
694 static void fsl_elbc_ctrl_init(void)
696 elbc_ctrl
= kzalloc(sizeof(*elbc_ctrl
), GFP_KERNEL
);
700 elbc_ctrl
->regs
= LBC_BASE_ADDR
;
702 /* clear event registers */
703 out_be32(&elbc_ctrl
->regs
->ltesr
, LTESR_NAND_MASK
);
704 out_be32(&elbc_ctrl
->regs
->lteatr
, 0);
706 /* Enable interrupts for any detected events */
707 out_be32(&elbc_ctrl
->regs
->lteir
, LTESR_NAND_MASK
);
709 elbc_ctrl
->read_bytes
= 0;
710 elbc_ctrl
->index
= 0;
711 elbc_ctrl
->addr
= NULL
;
714 int board_nand_init(struct nand_chip
*nand
)
716 struct fsl_elbc_mtd
*priv
;
717 uint32_t br
= 0, or = 0;
720 fsl_elbc_ctrl_init();
725 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
729 priv
->ctrl
= elbc_ctrl
;
730 priv
->vbase
= nand
->IO_ADDR_R
;
732 /* Find which chip select it is connected to. It'd be nice
733 * if we could pass more than one datum to the NAND driver...
735 for (priv
->bank
= 0; priv
->bank
< MAX_BANKS
; priv
->bank
++) {
736 phys_addr_t base_addr
= virt_to_phys(nand
->IO_ADDR_R
);
738 br
= in_be32(&elbc_ctrl
->regs
->bank
[priv
->bank
].br
);
739 or = in_be32(&elbc_ctrl
->regs
->bank
[priv
->bank
].or);
741 if ((br
& BR_V
) && (br
& BR_MSEL
) == BR_MS_FCM
&&
742 (br
& or & BR_BA
) == BR_PHYS_ADDR(base_addr
))
746 if (priv
->bank
>= MAX_BANKS
) {
747 printf("fsl_elbc_nand: address did not match any "
752 elbc_ctrl
->chips
[priv
->bank
] = priv
;
754 /* fill in nand_chip structure */
755 /* set up function call table */
756 nand
->read_byte
= fsl_elbc_read_byte
;
757 nand
->write_buf
= fsl_elbc_write_buf
;
758 nand
->read_buf
= fsl_elbc_read_buf
;
759 nand
->verify_buf
= fsl_elbc_verify_buf
;
760 nand
->select_chip
= fsl_elbc_select_chip
;
761 nand
->cmdfunc
= fsl_elbc_cmdfunc
;
762 nand
->waitfunc
= fsl_elbc_wait
;
764 /* set up nand options */
765 nand
->bbt_td
= &bbt_main_descr
;
766 nand
->bbt_md
= &bbt_mirror_descr
;
768 /* set up nand options */
769 nand
->options
= NAND_NO_READRDY
| NAND_NO_AUTOINCR
|
772 nand
->controller
= &elbc_ctrl
->controller
;
775 nand
->ecc
.read_page
= fsl_elbc_read_page
;
776 nand
->ecc
.write_page
= fsl_elbc_write_page
;
778 #ifdef CONFIG_FSL_ELBC_FMR
779 priv
->fmr
= CONFIG_FSL_ELBC_FMR
;
781 priv
->fmr
= (15 << FMR_CWTO_SHIFT
) | (2 << FMR_AL_SHIFT
);
784 * Hardware expects small page has ECCM0, large page has ECCM1
785 * when booting from NAND. Board config can override if not
789 priv
->fmr
|= FMR_ECCM
;
792 /* If CS Base Register selects full hardware ECC then use it */
793 if ((br
& BR_DECC
) == BR_DECC_CHK_GEN
) {
794 nand
->ecc
.mode
= NAND_ECC_HW
;
796 nand
->ecc
.layout
= (priv
->fmr
& FMR_ECCM
) ?
797 &fsl_elbc_oob_sp_eccm1
:
798 &fsl_elbc_oob_sp_eccm0
;
800 nand
->ecc
.size
= 512;
804 /* otherwise fall back to default software ECC */
805 nand
->ecc
.mode
= NAND_ECC_SOFT
;
808 /* Large-page-specific setup */
809 if (or & OR_FCM_PGS
) {
811 nand
->badblock_pattern
= &largepage_memorybased
;
813 /* adjust ecc setup if needed */
814 if ((br
& BR_DECC
) == BR_DECC_CHK_GEN
) {
816 nand
->ecc
.layout
= (priv
->fmr
& FMR_ECCM
) ?
817 &fsl_elbc_oob_lp_eccm1
:
818 &fsl_elbc_oob_lp_eccm0
;