drivers/mtd/nand/fsl_ifc_spl.c

   1 /*
   2  * NAND boot for Freescale Integrated Flash Controller, NAND FCM
   3  *
   4  * Copyright 2011 Freescale Semiconductor, Inc.
   5  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <fsl_ifc.h>
  13 #include <linux/mtd/rawnand.h>
  14 #ifdef CONFIG_CHAIN_OF_TRUST
  15 #include <fsl_validate.h>
  16 #endif
  17
  18 static inline int is_blank(uchar *addr, int page_size)
  19 {
  20         int i;
  21
  22         for (i = 0; i < page_size; i++) {
  23                 if (__raw_readb(&addr[i]) != 0xff)
  24                         return 0;
  25         }
  26
  27         /*
  28          * For the SPL, don't worry about uncorrectable errors
  29          * where the main area is all FFs but shouldn't be.
  30          */
  31         return 1;
  32 }
  33
  34 /* returns nonzero if entire page is blank */
  35 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  36                                  unsigned int bufnum, int page_size)
  37 {
  38         u32 reg = eccstat[bufnum / 4];
  39         int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  40
  41         if (errors == 0xf) { /* uncorrectable */
  42                 /* Blank pages fail hw ECC checks */
  43                 if (is_blank(buf, page_size))
  44                         return 1;
  45
  46                 puts("ecc error\n");
  47                 for (;;)
  48                         ;
  49         }
  50
  51         return 0;
  52 }
  53
  54 static inline struct fsl_ifc_runtime *runtime_regs_address(void)
  55 {
  56         struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
  57         int ver = 0;
  58
  59         ver = ifc_in32(&regs.gregs->ifc_rev);
  60         if (ver >= FSL_IFC_V2_0_0)
  61                 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  62         else
  63                 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  64
  65         return regs.rregs;
  66 }
  67
  68 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  69 {
  70         struct fsl_ifc_runtime *ifc = runtime_regs_address();
  71         u32 status;
  72         u32 eccstat[8];
  73         int bufperpage = page_size / 512;
  74         int bufnum_end, i;
  75
  76         bufnum *= bufperpage;
  77         bufnum_end = bufnum + bufperpage - 1;
  78
  79         do {
  80                 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  81         } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  82
  83         if (status & IFC_NAND_EVTER_STAT_FTOER) {
  84                 puts("flash time out error\n");
  85                 for (;;)
  86                         ;
  87         }
  88
  89         for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  90                 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  91
  92         for (i = bufnum; i <= bufnum_end; i++) {
  93                 if (check_read_ecc(buf, eccstat, i, page_size))
  94                         break;
  95         }
  96
  97         ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
  98 }
  99
 100 static inline int bad_block(uchar *marker, int port_size)
 101 {
 102         if (port_size == 8)
 103                 return __raw_readb(marker) != 0xff;
 104         else
 105                 return __raw_readw((u16 *)marker) != 0xffff;
 106 }
 107
 108 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 109 {
 110         struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
 111         struct fsl_ifc_runtime *ifc = NULL;
 112         uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 113         int page_size;
 114         int port_size;
 115         int pages_per_blk;
 116         int blk_size;
 117         int bad_marker = 0;
 118         int bufnum_mask, bufnum, ver = 0;
 119
 120         int csor, cspr;
 121         int pos = 0;
 122         int j = 0;
 123
 124         int sram_addr;
 125         int pg_no;
 126         uchar *dst = vdst;
 127
 128         ifc = runtime_regs_address();
 129
 130         /* Get NAND Flash configuration */
 131         csor = CONFIG_SYS_NAND_CSOR;
 132         cspr = CONFIG_SYS_NAND_CSPR;
 133
 134         port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 135
 136         if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
 137                 page_size = 8192;
 138                 bufnum_mask = 0x0;
 139         } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
 140                 page_size = 4096;
 141                 bufnum_mask = 0x1;
 142         } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
 143                 page_size = 2048;
 144                 bufnum_mask = 0x3;
 145         } else {
 146                 page_size = 512;
 147                 bufnum_mask = 0xf;
 148
 149                 if (port_size == 8)
 150                         bad_marker = 5;
 151         }
 152
 153         ver = ifc_in32(&gregs->ifc_rev);
 154         if (ver >= FSL_IFC_V2_0_0)
 155                 bufnum_mask = (bufnum_mask * 2) + 1;
 156
 157         pages_per_blk =
 158                 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
 159
 160         blk_size = pages_per_blk * page_size;
 161
 162         /* Open Full SRAM mapping for spare are access */
 163         ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
 164
 165         /* Clear Boot events */
 166         ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
 167
 168         /* Program FIR/FCR for Large/Small page */
 169         if (page_size > 512) {
 170                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 171                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 172                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 173                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 174                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 175                           (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
 176                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 177
 178                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 179                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 180                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 181         } else {
 182                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 183                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 184                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 185                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 186                           (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
 187                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 188
 189                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 190                           NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 191         }
 192
 193         /* Program FBCR = 0 for full page read */
 194         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 195
 196         /* Read and copy u-boot on SDRAM from NAND device, In parallel
 197          * check for Bad block if found skip it and read continue to
 198          * next Block
 199          */
 200         while (pos < uboot_size) {
 201                 int i = 0;
 202                 do {
 203                         pg_no = offs / page_size;
 204                         bufnum = pg_no & bufnum_mask;
 205                         sram_addr = bufnum * page_size * 2;
 206
 207                         ifc_out32(&ifc->ifc_nand.row0, pg_no);
 208                         ifc_out32(&ifc->ifc_nand.col0, 0);
 209                         /* start read */
 210                         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 211                                   IFC_NAND_SEQ_STRT_FIR_STRT);
 212
 213                         /* wait for read to complete */
 214                         nand_wait(&buf[sram_addr], bufnum, page_size);
 215
 216                         /*
 217                          * If either of the first two pages are marked bad,
 218                          * continue to the next block.
 219                          */
 220                         if (i++ < 2 &&
 221                             bad_block(&buf[sram_addr + page_size + bad_marker],
 222                                       port_size)) {
 223                                 puts("skipping\n");
 224                                 offs = (offs + blk_size) & ~(blk_size - 1);
 225                                 pos &= ~(blk_size - 1);
 226                                 break;
 227                         }
 228
 229                         for (j = 0; j < page_size; j++)
 230                                 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
 231
 232                         pos += page_size;
 233                         offs += page_size;
 234                 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
 235         }
 236
 237         return 0;
 238 }
 239
 240 /*
 241  * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
 242  * configured and available since this code loads the main U-Boot image
 243  * from NAND into SDRAM and starts from there.
 244  */
 245 void nand_boot(void)
 246 {
 247         __attribute__((noreturn)) void (*uboot)(void);
 248         /*
 249          * Load U-Boot image from NAND into RAM
 250          */
 251         nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
 252                             CONFIG_SYS_NAND_U_BOOT_SIZE,
 253                             (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 254
 255 #ifdef CONFIG_NAND_ENV_DST
 256         nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 257                             (uchar *)CONFIG_NAND_ENV_DST);
 258
 259 #ifdef CONFIG_ENV_OFFSET_REDUND
 260         nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 261                             (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 262 #endif
 263 #endif
 264         /*
 265          * Jump to U-Boot image
 266          */
 267 #ifdef CONFIG_SPL_FLUSH_IMAGE
 268         /*
 269          * Clean d-cache and invalidate i-cache, to
 270          * make sure that no stale data is executed.
 271          */
 272         flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 273 #endif
 274
 275 #ifdef CONFIG_CHAIN_OF_TRUST
 276         /*
 277          * U-Boot header is appended at end of U-boot image, so
 278          * calculate U-boot header address using U-boot header size.
 279          */
 280 #define CONFIG_U_BOOT_HDR_ADDR \
 281                 ((CONFIG_SYS_NAND_U_BOOT_START + \
 282                   CONFIG_SYS_NAND_U_BOOT_SIZE) - \
 283                  CONFIG_U_BOOT_HDR_SIZE)
 284         spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
 285                            CONFIG_SYS_NAND_U_BOOT_START);
 286         /*
 287          * In case of failure in validation, spl_validate_uboot would
 288          * not return back in case of Production environment with ITS=1.
 289          * Thus U-Boot will not start.
 290          * In Development environment (ITS=0 and SB_EN=1), the function
 291          * may return back in case of non-fatal failures.
 292          */
 293 #endif
 294
 295         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 296         uboot();
 297 }
 298
 299 #ifndef CONFIG_SPL_NAND_INIT
 300 void nand_init(void)
 301 {
 302 }
 303
 304 void nand_deselect(void)
 305 {
 306 }
 307 #endif