drivers/mtd/nand/fsl_upm.c

   1 /*
   2  * FSL UPM NAND driver
   3  *
   4  * Copyright (C) 2007 MontaVista Software, Inc.
   5  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <config.h>
  14 #include <common.h>
  15 #include <asm/io.h>
  16 #include <asm/errno.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/fsl_upm.h>
  19 #include <nand.h>
  20
  21 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  22 {
  23         clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  24 }
  25
  26 static void fsl_upm_end_pattern(struct fsl_upm *upm)
  27 {
  28         clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  29
  30         while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  31                 eieio();
  32 }
  33
  34 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  35                                 void __iomem *io_addr, u32 mar)
  36 {
  37         out_be32(upm->mar, mar);
  38         switch (width) {
  39         case 8:
  40                 out_8(io_addr, 0x0);
  41                 break;
  42         case 16:
  43                 out_be16(io_addr, 0x0);
  44                 break;
  45         case 32:
  46                 out_be32(io_addr, 0x0);
  47                 break;
  48         }
  49 }
  50
  51 static void fun_wait(struct fsl_upm_nand *fun)
  52 {
  53         if (fun->dev_ready) {
  54                 while (!fun->dev_ready(fun->chip_nr))
  55                         debug("unexpected busy state\n");
  56         } else {
  57                 /*
  58                  * If the R/B pin is not connected, like on the TQM8548,
  59                  * a short delay is necessary.
  60                  */
  61                 udelay(1);
  62         }
  63 }
  64
  65 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  66 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  67 {
  68         struct nand_chip *chip = mtd->priv;
  69         struct fsl_upm_nand *fun = chip->priv;
  70
  71         if (chip_nr >= 0) {
  72                 fun->chip_nr = chip_nr;
  73                 chip->IO_ADDR_R = chip->IO_ADDR_W =
  74                         fun->upm.io_addr + fun->chip_offset * chip_nr;
  75         } else if (chip_nr == -1) {
  76                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  77         }
  78 }
  79 #endif
  80
  81 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  82 {
  83         struct nand_chip *chip = mtd->priv;
  84         struct fsl_upm_nand *fun = chip->priv;
  85         void __iomem *io_addr;
  86         u32 mar;
  87
  88         if (!(ctrl & fun->last_ctrl)) {
  89                 fsl_upm_end_pattern(&fun->upm);
  90
  91                 if (cmd == NAND_CMD_NONE)
  92                         return;
  93
  94                 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  95         }
  96
  97         if (ctrl & NAND_CTRL_CHANGE) {
  98                 if (ctrl & NAND_ALE)
  99                         fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
 100                 else if (ctrl & NAND_CLE)
 101                         fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
 102         }
 103
 104         mar = cmd << (32 - fun->width);
 105         io_addr = fun->upm.io_addr;
 106 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 107         if (fun->chip_nr > 0) {
 108                 io_addr += fun->chip_offset * fun->chip_nr;
 109                 if (fun->upm_mar_chip_offset)
 110                         mar |= fun->upm_mar_chip_offset * fun->chip_nr;
 111         }
 112 #endif
 113         fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
 114
 115         /*
 116          * Some boards/chips needs this. At least the MPC8360E-RDK and
 117          * TQM8548 need it. Probably weird chip, because I don't see
 118          * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
 119          * here are 0-2 unexpected busy states per block read.
 120          */
 121         if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
 122                 fun_wait(fun);
 123 }
 124
 125 static u8 nand_read_byte(struct mtd_info *mtd)
 126 {
 127         struct nand_chip *chip = mtd->priv;
 128
 129         return in_8(chip->IO_ADDR_R);
 130 }
 131
 132 static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 133 {
 134         int i;
 135         struct nand_chip *chip = mtd->priv;
 136         struct fsl_upm_nand *fun = chip->priv;
 137
 138         for (i = 0; i < len; i++) {
 139                 out_8(chip->IO_ADDR_W, buf[i]);
 140                 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
 141                         fun_wait(fun);
 142         }
 143
 144         if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
 145                 fun_wait(fun);
 146 }
 147
 148 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 149 {
 150         int i;
 151         struct nand_chip *chip = mtd->priv;
 152
 153         for (i = 0; i < len; i++)
 154                 buf[i] = in_8(chip->IO_ADDR_R);
 155 }
 156
 157 static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 158 {
 159         int i;
 160         struct nand_chip *chip = mtd->priv;
 161
 162         for (i = 0; i < len; i++) {
 163                 if (buf[i] != in_8(chip->IO_ADDR_R))
 164                         return -EFAULT;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static int nand_dev_ready(struct mtd_info *mtd)
 171 {
 172         struct nand_chip *chip = mtd->priv;
 173         struct fsl_upm_nand *fun = chip->priv;
 174
 175         return fun->dev_ready(fun->chip_nr);
 176 }
 177
 178 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 179 {
 180         if (fun->width != 8 && fun->width != 16 && fun->width != 32)
 181                 return -ENOSYS;
 182
 183         fun->last_ctrl = NAND_CLE;
 184
 185         chip->priv = fun;
 186         chip->chip_delay = fun->chip_delay;
 187         chip->ecc.mode = NAND_ECC_SOFT;
 188         chip->cmd_ctrl = fun_cmd_ctrl;
 189 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 190         chip->select_chip = fun_select_chip;
 191 #endif
 192         chip->read_byte = nand_read_byte;
 193         chip->read_buf = nand_read_buf;
 194         chip->write_buf = nand_write_buf;
 195         chip->verify_buf = nand_verify_buf;
 196         if (fun->dev_ready)
 197                 chip->dev_ready = nand_dev_ready;
 198
 199         return 0;
 200 }