drivers/mtd/nand/fsl_upm.c

   1 /*
   2  * FSL UPM NAND driver
   3  *
   4  * Copyright (C) 2007 MontaVista Software, Inc.
   5  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <config.h>
  14 #include <common.h>
  15 #include <asm/io.h>
  16 #include <asm/errno.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/fsl_upm.h>
  19 #include <nand.h>
  20
  21 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  22 {
  23         clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  24 }
  25
  26 static void fsl_upm_end_pattern(struct fsl_upm *upm)
  27 {
  28         clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  29
  30         while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  31                 eieio();
  32 }
  33
  34 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  35                                 void __iomem *io_addr, u32 mar)
  36 {
  37         out_be32(upm->mar, mar);
  38         switch (width) {
  39         case 8:
  40                 out_8(io_addr, 0x0);
  41                 break;
  42         case 16:
  43                 out_be16(io_addr, 0x0);
  44                 break;
  45         case 32:
  46                 out_be32(io_addr, 0x0);
  47                 break;
  48         }
  49 }
  50
  51 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  52 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  53 {
  54         struct nand_chip *chip = mtd->priv;
  55         struct fsl_upm_nand *fun = chip->priv;
  56
  57         if (chip_nr >= 0) {
  58                 fun->chip_nr = chip_nr;
  59                 chip->IO_ADDR_R = chip->IO_ADDR_W =
  60                         fun->upm.io_addr + fun->chip_offset * chip_nr;
  61         } else if (chip_nr == -1) {
  62                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  63         }
  64 }
  65 #endif
  66
  67 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  68 {
  69         struct nand_chip *chip = mtd->priv;
  70         struct fsl_upm_nand *fun = chip->priv;
  71         void __iomem *io_addr;
  72         u32 mar;
  73
  74         if (!(ctrl & fun->last_ctrl)) {
  75                 fsl_upm_end_pattern(&fun->upm);
  76
  77                 if (cmd == NAND_CMD_NONE)
  78                         return;
  79
  80                 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  81         }
  82
  83         if (ctrl & NAND_CTRL_CHANGE) {
  84                 if (ctrl & NAND_ALE)
  85                         fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  86                 else if (ctrl & NAND_CLE)
  87                         fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  88         }
  89
  90         mar = cmd << (32 - fun->width);
  91         io_addr = fun->upm.io_addr;
  92 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  93         if (fun->chip_nr > 0) {
  94                 io_addr += fun->chip_offset * fun->chip_nr;
  95                 if (fun->upm_mar_chip_offset)
  96                         mar |= fun->upm_mar_chip_offset * fun->chip_nr;
  97         }
  98 #endif
  99         fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
 100
 101         /*
 102          * Some boards/chips needs this. At least on MPC8360E-RDK we
 103          * need it. Probably weird chip, because I don't see any need
 104          * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
 105          * 0-2 unexpected busy states per block read.
 106          */
 107         if (fun->wait_pattern) {
 108                 while (!fun->dev_ready(fun->chip_nr))
 109                         debug("unexpected busy state\n");
 110         }
 111 }
 112
 113 static u8 nand_read_byte(struct mtd_info *mtd)
 114 {
 115         struct nand_chip *chip = mtd->priv;
 116
 117         return in_8(chip->IO_ADDR_R);
 118 }
 119
 120 static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 121 {
 122         int i;
 123         struct nand_chip *chip = mtd->priv;
 124
 125         for (i = 0; i < len; i++)
 126                 out_8(chip->IO_ADDR_W, buf[i]);
 127 }
 128
 129 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 130 {
 131         int i;
 132         struct nand_chip *chip = mtd->priv;
 133
 134         for (i = 0; i < len; i++)
 135                 buf[i] = in_8(chip->IO_ADDR_R);
 136 }
 137
 138 static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 139 {
 140         int i;
 141         struct nand_chip *chip = mtd->priv;
 142
 143         for (i = 0; i < len; i++) {
 144                 if (buf[i] != in_8(chip->IO_ADDR_R))
 145                         return -EFAULT;
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int nand_dev_ready(struct mtd_info *mtd)
 152 {
 153         struct nand_chip *chip = mtd->priv;
 154         struct fsl_upm_nand *fun = chip->priv;
 155
 156         return fun->dev_ready(fun->chip_nr);
 157 }
 158
 159 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 160 {
 161         if (fun->width != 8 && fun->width != 16 && fun->width != 32)
 162                 return -ENOSYS;
 163
 164         fun->last_ctrl = NAND_CLE;
 165
 166         chip->priv = fun;
 167         chip->chip_delay = fun->chip_delay;
 168         chip->ecc.mode = NAND_ECC_SOFT;
 169         chip->cmd_ctrl = fun_cmd_ctrl;
 170 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 171         chip->select_chip = fun_select_chip;
 172 #endif
 173         chip->read_byte = nand_read_byte;
 174         chip->read_buf = nand_read_buf;
 175         chip->write_buf = nand_write_buf;
 176         chip->verify_buf = nand_verify_buf;
 177         if (fun->dev_ready)
 178                 chip->dev_ready = nand_dev_ready;
 179
 180         return 0;
 181 }