]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/nand/kirkwood_nand.c
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/kirkwood.h>
14 /* NAND Flash Soc registers */
15 struct kwnandf_registers
{
16 u32 rd_params
; /* 0x10418 */
17 u32 wr_param
; /* 0x1041c */
18 u8 pad
[0x10470 - 0x1041c - 4];
19 u32 ctrl
; /* 0x10470 */
22 static struct kwnandf_registers
*nf_reg
=
23 (struct kwnandf_registers
*)KW_NANDF_BASE
;
26 * hardware specific access to control-lines/bits
28 #define NAND_ACTCEBOOT_BIT 0x02
30 static void kw_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
33 struct nand_chip
*nc
= mtd
->priv
;
36 if (cmd
== NAND_CMD_NONE
)
40 offs
= (1 << 0); /* Commands with A[1:0] == 01 */
41 else if (ctrl
& NAND_ALE
)
42 offs
= (1 << 1); /* Addresses with A[1:0] == 10 */
46 writeb(cmd
, nc
->IO_ADDR_W
+ offs
);
49 void kw_nand_select_chip(struct mtd_info
*mtd
, int chip
)
53 data
= readl(&nf_reg
->ctrl
);
54 data
|= NAND_ACTCEBOOT_BIT
;
55 writel(data
, &nf_reg
->ctrl
);
58 int board_nand_init(struct nand_chip
*nand
)
60 nand
->options
= NAND_COPYBACK
| NAND_CACHEPRG
| NAND_NO_PADDING
;
61 #if defined(CONFIG_NAND_ECC_BCH)
62 nand
->ecc
.mode
= NAND_ECC_SOFT_BCH
;
64 nand
->ecc
.mode
= NAND_ECC_SOFT
;
66 nand
->cmd_ctrl
= kw_nand_hwcontrol
;
67 nand
->chip_delay
= 40;
68 nand
->select_chip
= kw_nand_select_chip
;