2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <asm/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if defined(CONFIG_MX6)
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
42 #define MXS_NAND_BCH_TIMEOUT 10000
44 struct mxs_nand_info
{
47 uint32_t cmd_queue_len
;
48 uint32_t data_buf_size
;
54 uint8_t marking_block_bad
;
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob
)(struct mtd_info
*mtd
,
59 loff_t from
, struct mtd_oob_ops
*ops
);
60 int (*hooked_write_oob
)(struct mtd_info
*mtd
,
61 loff_t to
, struct mtd_oob_ops
*ops
);
62 int (*hooked_block_markbad
)(struct mtd_info
*mtd
,
66 struct mxs_dma_desc
**desc
;
70 struct nand_ecclayout fake_ecc_layout
;
73 * Cache management functions
75 #ifndef CONFIG_SYS_DCACHE_OFF
76 static void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
)
78 uint32_t addr
= (uint32_t)info
->data_buf
;
80 flush_dcache_range(addr
, addr
+ info
->data_buf_size
);
83 static void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
)
85 uint32_t addr
= (uint32_t)info
->data_buf
;
87 invalidate_dcache_range(addr
, addr
+ info
->data_buf_size
);
90 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
)
92 uint32_t addr
= (uint32_t)info
->cmd_buf
;
94 flush_dcache_range(addr
, addr
+ MXS_NAND_COMMAND_BUFFER_SIZE
);
97 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
) {}
98 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
) {}
99 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
) {}
102 static struct mxs_dma_desc
*mxs_nand_get_dma_desc(struct mxs_nand_info
*info
)
104 struct mxs_dma_desc
*desc
;
106 if (info
->desc_index
>= MXS_NAND_DMA_DESCRIPTOR_COUNT
) {
107 printf("MXS NAND: Too many DMA descriptors requested\n");
111 desc
= info
->desc
[info
->desc_index
];
117 static void mxs_nand_return_dma_descs(struct mxs_nand_info
*info
)
120 struct mxs_dma_desc
*desc
;
122 for (i
= 0; i
< info
->desc_index
; i
++) {
123 desc
= info
->desc
[i
];
124 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
125 desc
->address
= (dma_addr_t
)desc
;
128 info
->desc_index
= 0;
131 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size
)
133 return page_data_size
/ MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
136 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength
)
138 return ecc_strength
* 13;
141 static uint32_t mxs_nand_aux_status_offset(void)
143 return (MXS_NAND_METADATA_SIZE
+ 0x3) & ~0x3;
146 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size
,
147 uint32_t page_oob_size
)
149 if (page_data_size
== 2048)
152 if (page_data_size
== 4096) {
153 if (page_oob_size
== 128)
156 if (page_oob_size
== 218)
159 if (page_oob_size
== 224)
166 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size
,
167 uint32_t ecc_strength
)
169 uint32_t chunk_data_size_in_bits
;
170 uint32_t chunk_ecc_size_in_bits
;
171 uint32_t chunk_total_size_in_bits
;
172 uint32_t block_mark_chunk_number
;
173 uint32_t block_mark_chunk_bit_offset
;
174 uint32_t block_mark_bit_offset
;
176 chunk_data_size_in_bits
= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
* 8;
177 chunk_ecc_size_in_bits
= mxs_nand_ecc_size_in_bits(ecc_strength
);
179 chunk_total_size_in_bits
=
180 chunk_data_size_in_bits
+ chunk_ecc_size_in_bits
;
182 /* Compute the bit offset of the block mark within the physical page. */
183 block_mark_bit_offset
= page_data_size
* 8;
185 /* Subtract the metadata bits. */
186 block_mark_bit_offset
-= MXS_NAND_METADATA_SIZE
* 8;
189 * Compute the chunk number (starting at zero) in which the block mark
192 block_mark_chunk_number
=
193 block_mark_bit_offset
/ chunk_total_size_in_bits
;
196 * Compute the bit offset of the block mark within its chunk, and
199 block_mark_chunk_bit_offset
= block_mark_bit_offset
-
200 (block_mark_chunk_number
* chunk_total_size_in_bits
);
202 if (block_mark_chunk_bit_offset
> chunk_data_size_in_bits
)
206 * Now that we know the chunk number in which the block mark appears,
207 * we can subtract all the ECC bits that appear before it.
209 block_mark_bit_offset
-=
210 block_mark_chunk_number
* chunk_ecc_size_in_bits
;
212 return block_mark_bit_offset
;
215 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info
*mtd
)
217 uint32_t ecc_strength
;
218 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
219 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) >> 3;
222 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info
*mtd
)
224 uint32_t ecc_strength
;
225 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
226 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) & 0x7;
230 * Wait for BCH complete IRQ and clear the IRQ
232 static int mxs_nand_wait_for_bch_complete(void)
234 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
235 int timeout
= MXS_NAND_BCH_TIMEOUT
;
238 ret
= mxs_wait_mask_set(&bch_regs
->hw_bch_ctrl_reg
,
239 BCH_CTRL_COMPLETE_IRQ
, timeout
);
241 writel(BCH_CTRL_COMPLETE_IRQ
, &bch_regs
->hw_bch_ctrl_clr
);
247 * This is the function that we install in the cmd_ctrl function pointer of the
248 * owning struct nand_chip. The only functions in the reference implementation
249 * that use these functions pointers are cmdfunc and select_chip.
251 * In this driver, we implement our own select_chip, so this function will only
252 * be called by the reference implementation's cmdfunc. For this reason, we can
253 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
256 static void mxs_nand_cmd_ctrl(struct mtd_info
*mtd
, int data
, unsigned int ctrl
)
258 struct nand_chip
*nand
= mtd
->priv
;
259 struct mxs_nand_info
*nand_info
= nand
->priv
;
260 struct mxs_dma_desc
*d
;
261 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
265 * If this condition is true, something is _VERY_ wrong in MTD
268 if (nand_info
->cmd_queue_len
== MXS_NAND_COMMAND_BUFFER_SIZE
) {
269 printf("MXS NAND: Command queue too long\n");
274 * Every operation begins with a command byte and a series of zero or
275 * more address bytes. These are distinguished by either the Address
276 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
277 * asserted. When MTD is ready to execute the command, it will
278 * deasert both latch enables.
280 * Rather than run a separate DMA operation for every single byte, we
281 * queue them up and run a single DMA operation for the entire series
282 * of command and data bytes.
284 if (ctrl
& (NAND_ALE
| NAND_CLE
)) {
285 if (data
!= NAND_CMD_NONE
)
286 nand_info
->cmd_buf
[nand_info
->cmd_queue_len
++] = data
;
291 * If control arrives here, MTD has deasserted both the ALE and CLE,
292 * which means it's ready to run an operation. Check if we have any
295 if (nand_info
->cmd_queue_len
== 0)
298 /* Compile the DMA descriptor -- a descriptor that sends command. */
299 d
= mxs_nand_get_dma_desc(nand_info
);
301 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
302 MXS_DMA_DESC_CHAIN
| MXS_DMA_DESC_DEC_SEM
|
303 MXS_DMA_DESC_WAIT4END
| (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
304 (nand_info
->cmd_queue_len
<< MXS_DMA_DESC_BYTES_OFFSET
);
306 d
->cmd
.address
= (dma_addr_t
)nand_info
->cmd_buf
;
308 d
->cmd
.pio_words
[0] =
309 GPMI_CTRL0_COMMAND_MODE_WRITE
|
310 GPMI_CTRL0_WORD_LENGTH
|
311 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
312 GPMI_CTRL0_ADDRESS_NAND_CLE
|
313 GPMI_CTRL0_ADDRESS_INCREMENT
|
314 nand_info
->cmd_queue_len
;
316 mxs_dma_desc_append(channel
, d
);
319 mxs_nand_flush_cmd_buf(nand_info
);
321 /* Execute the DMA chain. */
322 ret
= mxs_dma_go(channel
);
324 printf("MXS NAND: Error sending command\n");
326 mxs_nand_return_dma_descs(nand_info
);
328 /* Reset the command queue. */
329 nand_info
->cmd_queue_len
= 0;
333 * Test if the NAND flash is ready.
335 static int mxs_nand_device_ready(struct mtd_info
*mtd
)
337 struct nand_chip
*chip
= mtd
->priv
;
338 struct mxs_nand_info
*nand_info
= chip
->priv
;
339 struct mxs_gpmi_regs
*gpmi_regs
=
340 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
343 tmp
= readl(&gpmi_regs
->hw_gpmi_stat
);
344 tmp
>>= (GPMI_STAT_READY_BUSY_OFFSET
+ nand_info
->cur_chip
);
350 * Select the NAND chip.
352 static void mxs_nand_select_chip(struct mtd_info
*mtd
, int chip
)
354 struct nand_chip
*nand
= mtd
->priv
;
355 struct mxs_nand_info
*nand_info
= nand
->priv
;
357 nand_info
->cur_chip
= chip
;
361 * Handle block mark swapping.
363 * Note that, when this function is called, it doesn't know whether it's
364 * swapping the block mark, or swapping it *back* -- but it doesn't matter
365 * because the the operation is the same.
367 static void mxs_nand_swap_block_mark(struct mtd_info
*mtd
,
368 uint8_t *data_buf
, uint8_t *oob_buf
)
376 bit_offset
= mxs_nand_mark_bit_offset(mtd
);
377 buf_offset
= mxs_nand_mark_byte_offset(mtd
);
380 * Get the byte from the data area that overlays the block mark. Since
381 * the ECC engine applies its own view to the bits in the page, the
382 * physical block mark won't (in general) appear on a byte boundary in
385 src
= data_buf
[buf_offset
] >> bit_offset
;
386 src
|= data_buf
[buf_offset
+ 1] << (8 - bit_offset
);
392 data_buf
[buf_offset
] &= ~(0xff << bit_offset
);
393 data_buf
[buf_offset
+ 1] &= 0xff << bit_offset
;
395 data_buf
[buf_offset
] |= dst
<< bit_offset
;
396 data_buf
[buf_offset
+ 1] |= dst
>> (8 - bit_offset
);
400 * Read data from NAND.
402 static void mxs_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int length
)
404 struct nand_chip
*nand
= mtd
->priv
;
405 struct mxs_nand_info
*nand_info
= nand
->priv
;
406 struct mxs_dma_desc
*d
;
407 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
410 if (length
> NAND_MAX_PAGESIZE
) {
411 printf("MXS NAND: DMA buffer too big\n");
416 printf("MXS NAND: DMA buffer is NULL\n");
420 /* Compile the DMA descriptor - a descriptor that reads data. */
421 d
= mxs_nand_get_dma_desc(nand_info
);
423 MXS_DMA_DESC_COMMAND_DMA_WRITE
| MXS_DMA_DESC_IRQ
|
424 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
425 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
426 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
428 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
430 d
->cmd
.pio_words
[0] =
431 GPMI_CTRL0_COMMAND_MODE_READ
|
432 GPMI_CTRL0_WORD_LENGTH
|
433 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
434 GPMI_CTRL0_ADDRESS_NAND_DATA
|
437 mxs_dma_desc_append(channel
, d
);
440 * A DMA descriptor that waits for the command to end and the chip to
443 * I think we actually should *not* be waiting for the chip to become
444 * ready because, after all, we don't care. I think the original code
445 * did that and no one has re-thought it yet.
447 d
= mxs_nand_get_dma_desc(nand_info
);
449 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
450 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_DEC_SEM
|
451 MXS_DMA_DESC_WAIT4END
| (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
455 d
->cmd
.pio_words
[0] =
456 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
457 GPMI_CTRL0_WORD_LENGTH
|
458 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
459 GPMI_CTRL0_ADDRESS_NAND_DATA
;
461 mxs_dma_desc_append(channel
, d
);
463 /* Execute the DMA chain. */
464 ret
= mxs_dma_go(channel
);
466 printf("MXS NAND: DMA read error\n");
470 /* Invalidate caches */
471 mxs_nand_inval_data_buf(nand_info
);
473 memcpy(buf
, nand_info
->data_buf
, length
);
476 mxs_nand_return_dma_descs(nand_info
);
480 * Write data to NAND.
482 static void mxs_nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
485 struct nand_chip
*nand
= mtd
->priv
;
486 struct mxs_nand_info
*nand_info
= nand
->priv
;
487 struct mxs_dma_desc
*d
;
488 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
491 if (length
> NAND_MAX_PAGESIZE
) {
492 printf("MXS NAND: DMA buffer too big\n");
497 printf("MXS NAND: DMA buffer is NULL\n");
501 memcpy(nand_info
->data_buf
, buf
, length
);
503 /* Compile the DMA descriptor - a descriptor that writes data. */
504 d
= mxs_nand_get_dma_desc(nand_info
);
506 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
507 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
508 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
509 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
511 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
513 d
->cmd
.pio_words
[0] =
514 GPMI_CTRL0_COMMAND_MODE_WRITE
|
515 GPMI_CTRL0_WORD_LENGTH
|
516 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
517 GPMI_CTRL0_ADDRESS_NAND_DATA
|
520 mxs_dma_desc_append(channel
, d
);
523 mxs_nand_flush_data_buf(nand_info
);
525 /* Execute the DMA chain. */
526 ret
= mxs_dma_go(channel
);
528 printf("MXS NAND: DMA write error\n");
530 mxs_nand_return_dma_descs(nand_info
);
534 * Read a single byte from NAND.
536 static uint8_t mxs_nand_read_byte(struct mtd_info
*mtd
)
539 mxs_nand_read_buf(mtd
, &buf
, 1);
544 * Read a page from NAND.
546 static int mxs_nand_ecc_read_page(struct mtd_info
*mtd
, struct nand_chip
*nand
,
547 uint8_t *buf
, int oob_required
,
550 struct mxs_nand_info
*nand_info
= nand
->priv
;
551 struct mxs_dma_desc
*d
;
552 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
553 uint32_t corrected
= 0, failed
= 0;
557 /* Compile the DMA descriptor - wait for ready. */
558 d
= mxs_nand_get_dma_desc(nand_info
);
560 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
561 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
562 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
566 d
->cmd
.pio_words
[0] =
567 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
568 GPMI_CTRL0_WORD_LENGTH
|
569 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
570 GPMI_CTRL0_ADDRESS_NAND_DATA
;
572 mxs_dma_desc_append(channel
, d
);
574 /* Compile the DMA descriptor - enable the BCH block and read. */
575 d
= mxs_nand_get_dma_desc(nand_info
);
577 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
578 MXS_DMA_DESC_WAIT4END
| (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
582 d
->cmd
.pio_words
[0] =
583 GPMI_CTRL0_COMMAND_MODE_READ
|
584 GPMI_CTRL0_WORD_LENGTH
|
585 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
586 GPMI_CTRL0_ADDRESS_NAND_DATA
|
587 (mtd
->writesize
+ mtd
->oobsize
);
588 d
->cmd
.pio_words
[1] = 0;
589 d
->cmd
.pio_words
[2] =
590 GPMI_ECCCTRL_ENABLE_ECC
|
591 GPMI_ECCCTRL_ECC_CMD_DECODE
|
592 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
593 d
->cmd
.pio_words
[3] = mtd
->writesize
+ mtd
->oobsize
;
594 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
595 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
597 mxs_dma_desc_append(channel
, d
);
599 /* Compile the DMA descriptor - disable the BCH block. */
600 d
= mxs_nand_get_dma_desc(nand_info
);
602 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
603 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
604 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
608 d
->cmd
.pio_words
[0] =
609 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
610 GPMI_CTRL0_WORD_LENGTH
|
611 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
612 GPMI_CTRL0_ADDRESS_NAND_DATA
|
613 (mtd
->writesize
+ mtd
->oobsize
);
614 d
->cmd
.pio_words
[1] = 0;
615 d
->cmd
.pio_words
[2] = 0;
617 mxs_dma_desc_append(channel
, d
);
619 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
620 d
= mxs_nand_get_dma_desc(nand_info
);
622 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
623 MXS_DMA_DESC_DEC_SEM
;
627 mxs_dma_desc_append(channel
, d
);
629 /* Execute the DMA chain. */
630 ret
= mxs_dma_go(channel
);
632 printf("MXS NAND: DMA read error\n");
636 ret
= mxs_nand_wait_for_bch_complete();
638 printf("MXS NAND: BCH read timeout\n");
642 /* Invalidate caches */
643 mxs_nand_inval_data_buf(nand_info
);
645 /* Read DMA completed, now do the mark swapping. */
646 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
648 /* Loop over status bytes, accumulating ECC status. */
649 status
= nand_info
->oob_buf
+ mxs_nand_aux_status_offset();
650 for (i
= 0; i
< mxs_nand_ecc_chunk_cnt(mtd
->writesize
); i
++) {
651 if (status
[i
] == 0x00)
654 if (status
[i
] == 0xff)
657 if (status
[i
] == 0xfe) {
662 corrected
+= status
[i
];
665 /* Propagate ECC status to the owning MTD. */
666 mtd
->ecc_stats
.failed
+= failed
;
667 mtd
->ecc_stats
.corrected
+= corrected
;
670 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
671 * details about our policy for delivering the OOB.
673 * We fill the caller's buffer with set bits, and then copy the block
674 * mark to the caller's buffer. Note that, if block mark swapping was
675 * necessary, it has already been done, so we can rely on the first
676 * byte of the auxiliary buffer to contain the block mark.
678 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
680 nand
->oob_poi
[0] = nand_info
->oob_buf
[0];
682 memcpy(buf
, nand_info
->data_buf
, mtd
->writesize
);
685 mxs_nand_return_dma_descs(nand_info
);
691 * Write a page to NAND.
693 static int mxs_nand_ecc_write_page(struct mtd_info
*mtd
,
694 struct nand_chip
*nand
, const uint8_t *buf
,
697 struct mxs_nand_info
*nand_info
= nand
->priv
;
698 struct mxs_dma_desc
*d
;
699 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
702 memcpy(nand_info
->data_buf
, buf
, mtd
->writesize
);
703 memcpy(nand_info
->oob_buf
, nand
->oob_poi
, mtd
->oobsize
);
705 /* Handle block mark swapping. */
706 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
708 /* Compile the DMA descriptor - write data. */
709 d
= mxs_nand_get_dma_desc(nand_info
);
711 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
712 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
713 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
717 d
->cmd
.pio_words
[0] =
718 GPMI_CTRL0_COMMAND_MODE_WRITE
|
719 GPMI_CTRL0_WORD_LENGTH
|
720 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
721 GPMI_CTRL0_ADDRESS_NAND_DATA
;
722 d
->cmd
.pio_words
[1] = 0;
723 d
->cmd
.pio_words
[2] =
724 GPMI_ECCCTRL_ENABLE_ECC
|
725 GPMI_ECCCTRL_ECC_CMD_ENCODE
|
726 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
727 d
->cmd
.pio_words
[3] = (mtd
->writesize
+ mtd
->oobsize
);
728 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
729 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
731 mxs_dma_desc_append(channel
, d
);
734 mxs_nand_flush_data_buf(nand_info
);
736 /* Execute the DMA chain. */
737 ret
= mxs_dma_go(channel
);
739 printf("MXS NAND: DMA write error\n");
743 ret
= mxs_nand_wait_for_bch_complete();
745 printf("MXS NAND: BCH write timeout\n");
750 mxs_nand_return_dma_descs(nand_info
);
755 * Read OOB from NAND.
757 * This function is a veneer that replaces the function originally installed by
758 * the NAND Flash MTD code.
760 static int mxs_nand_hook_read_oob(struct mtd_info
*mtd
, loff_t from
,
761 struct mtd_oob_ops
*ops
)
763 struct nand_chip
*chip
= mtd
->priv
;
764 struct mxs_nand_info
*nand_info
= chip
->priv
;
767 if (ops
->mode
== MTD_OPS_RAW
)
768 nand_info
->raw_oob_mode
= 1;
770 nand_info
->raw_oob_mode
= 0;
772 ret
= nand_info
->hooked_read_oob(mtd
, from
, ops
);
774 nand_info
->raw_oob_mode
= 0;
782 * This function is a veneer that replaces the function originally installed by
783 * the NAND Flash MTD code.
785 static int mxs_nand_hook_write_oob(struct mtd_info
*mtd
, loff_t to
,
786 struct mtd_oob_ops
*ops
)
788 struct nand_chip
*chip
= mtd
->priv
;
789 struct mxs_nand_info
*nand_info
= chip
->priv
;
792 if (ops
->mode
== MTD_OPS_RAW
)
793 nand_info
->raw_oob_mode
= 1;
795 nand_info
->raw_oob_mode
= 0;
797 ret
= nand_info
->hooked_write_oob(mtd
, to
, ops
);
799 nand_info
->raw_oob_mode
= 0;
805 * Mark a block bad in NAND.
807 * This function is a veneer that replaces the function originally installed by
808 * the NAND Flash MTD code.
810 static int mxs_nand_hook_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
812 struct nand_chip
*chip
= mtd
->priv
;
813 struct mxs_nand_info
*nand_info
= chip
->priv
;
816 nand_info
->marking_block_bad
= 1;
818 ret
= nand_info
->hooked_block_markbad(mtd
, ofs
);
820 nand_info
->marking_block_bad
= 0;
826 * There are several places in this driver where we have to handle the OOB and
827 * block marks. This is the function where things are the most complicated, so
828 * this is where we try to explain it all. All the other places refer back to
831 * These are the rules, in order of decreasing importance:
833 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
834 * write operations take measures to protect it.
836 * 2) In read operations, the first byte of the OOB we return must reflect the
837 * true state of the block mark, no matter where that block mark appears in
840 * 3) ECC-based read operations return an OOB full of set bits (since we never
841 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
844 * 4) "Raw" read operations return a direct view of the physical bytes in the
845 * page, using the conventional definition of which bytes are data and which
846 * are OOB. This gives the caller a way to see the actual, physical bytes
847 * in the page, without the distortions applied by our ECC engine.
849 * What we do for this specific read operation depends on whether we're doing
850 * "raw" read, or an ECC-based read.
852 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
853 * easy. When reading a page, for example, the NAND Flash MTD code calls our
854 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
855 * ECC-based or raw view of the page is implicit in which function it calls
856 * (there is a similar pair of ECC-based/raw functions for writing).
858 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
859 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
860 * caller wants an ECC-based or raw view of the page is not propagated down to
863 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
864 * ecc.read_oob and ecc.write_oob function pointers in the owning
865 * struct mtd_info with our own functions. These hook functions set the
866 * raw_oob_mode field so that, when control finally arrives here, we'll know
869 static int mxs_nand_ecc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
872 struct mxs_nand_info
*nand_info
= nand
->priv
;
875 * First, fill in the OOB buffer. If we're doing a raw read, we need to
876 * get the bytes from the physical page. If we're not doing a raw read,
877 * we need to fill the buffer with set bits.
879 if (nand_info
->raw_oob_mode
) {
881 * If control arrives here, we're doing a "raw" read. Send the
882 * command to read the conventional OOB and read it.
884 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
885 nand
->read_buf(mtd
, nand
->oob_poi
, mtd
->oobsize
);
888 * If control arrives here, we're not doing a "raw" read. Fill
889 * the OOB buffer with set bits and correct the block mark.
891 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
893 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
894 mxs_nand_read_buf(mtd
, nand
->oob_poi
, 1);
902 * Write OOB data to NAND.
904 static int mxs_nand_ecc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
907 struct mxs_nand_info
*nand_info
= nand
->priv
;
908 uint8_t block_mark
= 0;
911 * There are fundamental incompatibilities between the i.MX GPMI NFC and
912 * the NAND Flash MTD model that make it essentially impossible to write
913 * the out-of-band bytes.
915 * We permit *ONE* exception. If the *intent* of writing the OOB is to
916 * mark a block bad, we can do that.
919 if (!nand_info
->marking_block_bad
) {
920 printf("NXS NAND: Writing OOB isn't supported\n");
924 /* Write the block mark. */
925 nand
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
926 nand
->write_buf(mtd
, &block_mark
, 1);
927 nand
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
929 /* Check if it worked. */
930 if (nand
->waitfunc(mtd
, nand
) & NAND_STATUS_FAIL
)
937 * Claims all blocks are good.
939 * In principle, this function is *only* called when the NAND Flash MTD system
940 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
941 * the driver for bad block information.
943 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
944 * this function is *only* called when we take it away.
946 * Thus, this function is only called when we want *all* blocks to look good,
947 * so it *always* return success.
949 static int mxs_nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
955 * Nominally, the purpose of this function is to look for or create the bad
956 * block table. In fact, since the we call this function at the very end of
957 * the initialization process started by nand_scan(), and we doesn't have a
958 * more formal mechanism, we "hook" this function to continue init process.
960 * At this point, the physical NAND Flash chips have been identified and
961 * counted, so we know the physical geometry. This enables us to make some
962 * important configuration decisions.
964 * The return value of this function propogates directly back to this driver's
965 * call to nand_scan(). Anything other than zero will cause this driver to
966 * tear everything down and declare failure.
968 static int mxs_nand_scan_bbt(struct mtd_info
*mtd
)
970 struct nand_chip
*nand
= mtd
->priv
;
971 struct mxs_nand_info
*nand_info
= nand
->priv
;
972 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
975 /* Configure BCH and set NFC geometry */
976 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
978 /* Configure layout 0 */
979 tmp
= (mxs_nand_ecc_chunk_cnt(mtd
->writesize
) - 1)
980 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET
;
981 tmp
|= MXS_NAND_METADATA_SIZE
<< BCH_FLASHLAYOUT0_META_SIZE_OFFSET
;
982 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
983 << BCH_FLASHLAYOUT0_ECC0_OFFSET
;
984 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
985 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
986 writel(tmp
, &bch_regs
->hw_bch_flash0layout0
);
988 tmp
= (mtd
->writesize
+ mtd
->oobsize
)
989 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET
;
990 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
991 << BCH_FLASHLAYOUT1_ECCN_OFFSET
;
992 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
993 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
994 writel(tmp
, &bch_regs
->hw_bch_flash0layout1
);
996 /* Set *all* chip selects to use layout 0 */
997 writel(0, &bch_regs
->hw_bch_layoutselect
);
999 /* Enable BCH complete interrupt */
1000 writel(BCH_CTRL_COMPLETE_IRQ_EN
, &bch_regs
->hw_bch_ctrl_set
);
1002 /* Hook some operations at the MTD level. */
1003 if (mtd
->_read_oob
!= mxs_nand_hook_read_oob
) {
1004 nand_info
->hooked_read_oob
= mtd
->_read_oob
;
1005 mtd
->_read_oob
= mxs_nand_hook_read_oob
;
1008 if (mtd
->_write_oob
!= mxs_nand_hook_write_oob
) {
1009 nand_info
->hooked_write_oob
= mtd
->_write_oob
;
1010 mtd
->_write_oob
= mxs_nand_hook_write_oob
;
1013 if (mtd
->_block_markbad
!= mxs_nand_hook_block_markbad
) {
1014 nand_info
->hooked_block_markbad
= mtd
->_block_markbad
;
1015 mtd
->_block_markbad
= mxs_nand_hook_block_markbad
;
1018 /* We use the reference implementation for bad block management. */
1019 return nand_default_bbt(mtd
);
1023 * Allocate DMA buffers
1025 int mxs_nand_alloc_buffers(struct mxs_nand_info
*nand_info
)
1028 const int size
= NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
;
1030 nand_info
->data_buf_size
= roundup(size
, MXS_DMA_ALIGNMENT
);
1033 buf
= memalign(MXS_DMA_ALIGNMENT
, nand_info
->data_buf_size
);
1035 printf("MXS NAND: Error allocating DMA buffers\n");
1039 memset(buf
, 0, nand_info
->data_buf_size
);
1041 nand_info
->data_buf
= buf
;
1042 nand_info
->oob_buf
= buf
+ NAND_MAX_PAGESIZE
;
1043 /* Command buffers */
1044 nand_info
->cmd_buf
= memalign(MXS_DMA_ALIGNMENT
,
1045 MXS_NAND_COMMAND_BUFFER_SIZE
);
1046 if (!nand_info
->cmd_buf
) {
1048 printf("MXS NAND: Error allocating command buffers\n");
1051 memset(nand_info
->cmd_buf
, 0, MXS_NAND_COMMAND_BUFFER_SIZE
);
1052 nand_info
->cmd_queue_len
= 0;
1058 * Initializes the NFC hardware.
1060 int mxs_nand_init(struct mxs_nand_info
*info
)
1062 struct mxs_gpmi_regs
*gpmi_regs
=
1063 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
1064 struct mxs_bch_regs
*bch_regs
=
1065 (struct mxs_bch_regs
*)MXS_BCH_BASE
;
1068 info
->desc
= malloc(sizeof(struct mxs_dma_desc
*) *
1069 MXS_NAND_DMA_DESCRIPTOR_COUNT
);
1073 /* Allocate the DMA descriptors. */
1074 for (i
= 0; i
< MXS_NAND_DMA_DESCRIPTOR_COUNT
; i
++) {
1075 info
->desc
[i
] = mxs_dma_desc_alloc();
1080 /* Init the DMA controller. */
1081 for (j
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
;
1082 j
<= MXS_DMA_CHANNEL_AHB_APBH_GPMI7
; j
++) {
1083 if (mxs_dma_init_channel(j
))
1087 /* Reset the GPMI block. */
1088 mxs_reset_block(&gpmi_regs
->hw_gpmi_ctrl0_reg
);
1089 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
1092 * Choose NAND mode, set IRQ polarity, disable write protection and
1095 clrsetbits_le32(&gpmi_regs
->hw_gpmi_ctrl1
,
1096 GPMI_CTRL1_GPMI_MODE
,
1097 GPMI_CTRL1_ATA_IRQRDY_POLARITY
| GPMI_CTRL1_DEV_RESET
|
1098 GPMI_CTRL1_BCH_MODE
);
1103 for (--j
; j
>= 0; j
--)
1108 for (--i
; i
>= 0; i
--)
1109 mxs_dma_desc_free(info
->desc
[i
]);
1110 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1115 * This function is called during the driver binding process.
1117 * @param pdev the device structure used to store device specific
1118 * information that is used by the suspend, resume and
1121 * @return The function always returns 0.
1123 int board_nand_init(struct nand_chip
*nand
)
1125 struct mxs_nand_info
*nand_info
;
1128 nand_info
= malloc(sizeof(struct mxs_nand_info
));
1130 printf("MXS NAND: Failed to allocate private data\n");
1133 memset(nand_info
, 0, sizeof(struct mxs_nand_info
));
1135 err
= mxs_nand_alloc_buffers(nand_info
);
1139 err
= mxs_nand_init(nand_info
);
1143 memset(&fake_ecc_layout
, 0, sizeof(fake_ecc_layout
));
1145 nand
->priv
= nand_info
;
1146 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1148 nand
->cmd_ctrl
= mxs_nand_cmd_ctrl
;
1150 nand
->dev_ready
= mxs_nand_device_ready
;
1151 nand
->select_chip
= mxs_nand_select_chip
;
1152 nand
->block_bad
= mxs_nand_block_bad
;
1153 nand
->scan_bbt
= mxs_nand_scan_bbt
;
1155 nand
->read_byte
= mxs_nand_read_byte
;
1157 nand
->read_buf
= mxs_nand_read_buf
;
1158 nand
->write_buf
= mxs_nand_write_buf
;
1160 nand
->ecc
.read_page
= mxs_nand_ecc_read_page
;
1161 nand
->ecc
.write_page
= mxs_nand_ecc_write_page
;
1162 nand
->ecc
.read_oob
= mxs_nand_ecc_read_oob
;
1163 nand
->ecc
.write_oob
= mxs_nand_ecc_write_oob
;
1165 nand
->ecc
.layout
= &fake_ecc_layout
;
1166 nand
->ecc
.mode
= NAND_ECC_HW
;
1167 nand
->ecc
.bytes
= 9;
1168 nand
->ecc
.size
= 512;
1169 nand
->ecc
.strength
= 8;
1174 free(nand_info
->data_buf
);
1175 free(nand_info
->cmd_buf
);