3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <asm/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8
= {
60 static struct nand_ecclayout nand_oob_16
= {
62 .eccpos
= {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64
= {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128
= {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
95 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
96 struct mtd_oob_ops
*ops
);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger
);
104 static int check_offs_len(struct mtd_info
*mtd
,
105 loff_t ofs
, uint64_t len
)
107 struct nand_chip
*chip
= mtd_to_nand(mtd
);
110 /* Start address must align on block boundary */
111 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__
);
116 /* Length must align on block boundary */
117 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__
);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info
*mtd
)
133 struct nand_chip
*chip
= mtd_to_nand(mtd
);
135 /* De-select the NAND device */
136 chip
->select_chip(mtd
, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info
*mtd
)
147 struct nand_chip
*chip
= mtd_to_nand(mtd
);
148 return readb(chip
->IO_ADDR_R
);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
160 struct nand_chip
*chip
= mtd_to_nand(mtd
);
161 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16
nand_read_word(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd_to_nand(mtd
);
173 return readw(chip
->IO_ADDR_R
);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
185 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
208 struct nand_chip
*chip
= mtd_to_nand(mtd
);
210 chip
->write_buf(mtd
, &byte
, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
222 struct nand_chip
*chip
= mtd_to_nand(mtd
);
223 uint16_t word
= byte
;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 #if !defined(CONFIG_BLACKFIN)
245 static void iowrite8_rep(void *addr
, const uint8_t *buf
, int len
)
249 for (i
= 0; i
< len
; i
++)
250 writeb(buf
[i
], addr
);
252 static void ioread8_rep(void *addr
, uint8_t *buf
, int len
)
256 for (i
= 0; i
< len
; i
++)
257 buf
[i
] = readb(addr
);
260 static void ioread16_rep(void *addr
, void *buf
, int len
)
263 u16
*p
= (u16
*) buf
;
265 for (i
= 0; i
< len
; i
++)
269 static void iowrite16_rep(void *addr
, void *buf
, int len
)
272 u16
*p
= (u16
*) buf
;
274 for (i
= 0; i
< len
; i
++)
280 * nand_write_buf - [DEFAULT] write buffer to chip
281 * @mtd: MTD device structure
283 * @len: number of bytes to write
285 * Default write function for 8bit buswidth.
287 void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
289 struct nand_chip
*chip
= mtd_to_nand(mtd
);
291 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
295 * nand_read_buf - [DEFAULT] read chip data into buffer
296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
300 * Default read function for 8bit buswidth.
302 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
304 struct nand_chip
*chip
= mtd_to_nand(mtd
);
306 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
310 * nand_write_buf16 - [DEFAULT] write buffer to chip
311 * @mtd: MTD device structure
313 * @len: number of bytes to write
315 * Default write function for 16bit buswidth.
317 void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
319 struct nand_chip
*chip
= mtd_to_nand(mtd
);
320 u16
*p
= (u16
*) buf
;
322 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
326 * nand_read_buf16 - [DEFAULT] read chip data into buffer
327 * @mtd: MTD device structure
328 * @buf: buffer to store date
329 * @len: number of bytes to read
331 * Default read function for 16bit buswidth.
333 void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
335 struct nand_chip
*chip
= mtd_to_nand(mtd
);
336 u16
*p
= (u16
*) buf
;
338 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
342 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
343 * @mtd: MTD device structure
344 * @ofs: offset from device start
346 * Check, if the block is bad.
348 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
350 int page
, res
= 0, i
= 0;
351 struct nand_chip
*chip
= mtd_to_nand(mtd
);
354 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
355 ofs
+= mtd
->erasesize
- mtd
->writesize
;
357 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
360 if (chip
->options
& NAND_BUSWIDTH_16
) {
361 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
362 chip
->badblockpos
& 0xFE, page
);
363 bad
= cpu_to_le16(chip
->read_word(mtd
));
364 if (chip
->badblockpos
& 0x1)
369 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
371 bad
= chip
->read_byte(mtd
);
374 if (likely(chip
->badblockbits
== 8))
377 res
= hweight8(bad
) < chip
->badblockbits
;
378 ofs
+= mtd
->writesize
;
379 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
381 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
387 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
388 * @mtd: MTD device structure
389 * @ofs: offset from device start
391 * This is the default implementation, which can be overridden by a hardware
392 * specific driver. It provides the details for writing a bad block marker to a
395 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
397 struct nand_chip
*chip
= mtd_to_nand(mtd
);
398 struct mtd_oob_ops ops
;
399 uint8_t buf
[2] = { 0, 0 };
400 int ret
= 0, res
, i
= 0;
402 memset(&ops
, 0, sizeof(ops
));
404 ops
.ooboffs
= chip
->badblockpos
;
405 if (chip
->options
& NAND_BUSWIDTH_16
) {
406 ops
.ooboffs
&= ~0x01;
407 ops
.len
= ops
.ooblen
= 2;
409 ops
.len
= ops
.ooblen
= 1;
411 ops
.mode
= MTD_OPS_PLACE_OOB
;
413 /* Write to first/last page(s) if necessary */
414 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
415 ofs
+= mtd
->erasesize
- mtd
->writesize
;
417 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
422 ofs
+= mtd
->writesize
;
423 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
429 * nand_block_markbad_lowlevel - mark a block bad
430 * @mtd: MTD device structure
431 * @ofs: offset from device start
433 * This function performs the generic NAND bad block marking steps (i.e., bad
434 * block table(s) and/or marker(s)). We only allow the hardware driver to
435 * specify how to write bad block markers to OOB (chip->block_markbad).
437 * We try operations in the following order:
438 * (1) erase the affected block, to allow OOB marker to be written cleanly
439 * (2) write bad block marker to OOB area of affected block (unless flag
440 * NAND_BBT_NO_OOB_BBM is present)
442 * Note that we retain the first error encountered in (2) or (3), finish the
443 * procedures, and dump the error in the end.
445 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
447 struct nand_chip
*chip
= mtd_to_nand(mtd
);
450 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
451 struct erase_info einfo
;
453 /* Attempt erase before marking OOB */
454 memset(&einfo
, 0, sizeof(einfo
));
457 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
458 nand_erase_nand(mtd
, &einfo
, 0);
460 /* Write bad block marker to OOB */
461 nand_get_device(mtd
, FL_WRITING
);
462 ret
= chip
->block_markbad(mtd
, ofs
);
463 nand_release_device(mtd
);
466 /* Mark block bad in BBT */
468 res
= nand_markbad_bbt(mtd
, ofs
);
474 mtd
->ecc_stats
.badblocks
++;
480 * nand_check_wp - [GENERIC] check if the chip is write protected
481 * @mtd: MTD device structure
483 * Check, if the device is write protected. The function expects, that the
484 * device is already selected.
486 static int nand_check_wp(struct mtd_info
*mtd
)
488 struct nand_chip
*chip
= mtd_to_nand(mtd
);
490 /* Broken xD cards report WP despite being writable */
491 if (chip
->options
& NAND_BROKEN_XD
)
494 /* Check the WP bit */
495 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
496 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
500 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
501 * @mtd: MTD device structure
502 * @ofs: offset from device start
504 * Check if the block is marked as reserved.
506 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
508 struct nand_chip
*chip
= mtd_to_nand(mtd
);
512 /* Return info from the table */
513 return nand_isreserved_bbt(mtd
, ofs
);
517 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
518 * @mtd: MTD device structure
519 * @ofs: offset from device start
520 * @allowbbt: 1, if its allowed to access the bbt area
522 * Check, if the block is bad. Either by reading the bad block table or
523 * calling of the scan function.
525 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
527 struct nand_chip
*chip
= mtd_to_nand(mtd
);
529 if (!(chip
->options
& NAND_SKIP_BBTSCAN
) &&
530 !(chip
->options
& NAND_BBT_SCANNED
)) {
531 chip
->options
|= NAND_BBT_SCANNED
;
536 return chip
->block_bad(mtd
, ofs
);
538 /* Return info from the table */
539 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
543 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
544 * @mtd: MTD device structure
546 * Wait for the ready pin after a command, and warn if a timeout occurs.
548 void nand_wait_ready(struct mtd_info
*mtd
)
550 struct nand_chip
*chip
= mtd_to_nand(mtd
);
551 u32 timeo
= (CONFIG_SYS_HZ
* 400) / 1000;
554 time_start
= get_timer(0);
555 /* Wait until command is processed or timeout occurs */
556 while (get_timer(time_start
) < timeo
) {
558 if (chip
->dev_ready(mtd
))
562 if (!chip
->dev_ready(mtd
))
563 pr_warn("timeout while waiting for chip to become ready\n");
565 EXPORT_SYMBOL_GPL(nand_wait_ready
);
568 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
569 * @mtd: MTD device structure
570 * @timeo: Timeout in ms
572 * Wait for status ready (i.e. command done) or timeout.
574 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
576 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
579 timeo
= (CONFIG_SYS_HZ
* timeo
) / 1000;
580 time_start
= get_timer(0);
581 while (get_timer(time_start
) < timeo
) {
582 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
589 * nand_command - [DEFAULT] Send command to NAND device
590 * @mtd: MTD device structure
591 * @command: the command to be sent
592 * @column: the column address for this command, -1 if none
593 * @page_addr: the page address for this command, -1 if none
595 * Send command to NAND device. This function is used for small page devices
596 * (512 Bytes per page).
598 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
599 int column
, int page_addr
)
601 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
602 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
604 /* Write out the command to the device */
605 if (command
== NAND_CMD_SEQIN
) {
608 if (column
>= mtd
->writesize
) {
610 column
-= mtd
->writesize
;
611 readcmd
= NAND_CMD_READOOB
;
612 } else if (column
< 256) {
613 /* First 256 bytes --> READ0 */
614 readcmd
= NAND_CMD_READ0
;
617 readcmd
= NAND_CMD_READ1
;
619 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
620 ctrl
&= ~NAND_CTRL_CHANGE
;
622 chip
->cmd_ctrl(mtd
, command
, ctrl
);
624 /* Address cycle, when necessary */
625 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
626 /* Serially input address */
628 /* Adjust columns for 16 bit buswidth */
629 if (chip
->options
& NAND_BUSWIDTH_16
&&
630 !nand_opcode_8bits(command
))
632 chip
->cmd_ctrl(mtd
, column
, ctrl
);
633 ctrl
&= ~NAND_CTRL_CHANGE
;
635 if (page_addr
!= -1) {
636 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
637 ctrl
&= ~NAND_CTRL_CHANGE
;
638 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
639 /* One more address cycle for devices > 32MiB */
640 if (chip
->chipsize
> (32 << 20))
641 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
643 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
646 * Program and erase have their own busy handlers status and sequential
651 case NAND_CMD_PAGEPROG
:
652 case NAND_CMD_ERASE1
:
653 case NAND_CMD_ERASE2
:
655 case NAND_CMD_STATUS
:
661 udelay(chip
->chip_delay
);
662 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
663 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
665 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
666 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
667 nand_wait_status_ready(mtd
, 250);
670 /* This applies to read commands */
673 * If we don't have access to the busy pin, we apply the given
676 if (!chip
->dev_ready
) {
677 udelay(chip
->chip_delay
);
682 * Apply this short delay always to ensure that we do wait tWB in
683 * any case on any machine.
687 nand_wait_ready(mtd
);
691 * nand_command_lp - [DEFAULT] Send command to NAND large page device
692 * @mtd: MTD device structure
693 * @command: the command to be sent
694 * @column: the column address for this command, -1 if none
695 * @page_addr: the page address for this command, -1 if none
697 * Send command to NAND device. This is the version for the new large page
698 * devices. We don't have the separate regions as we have in the small page
699 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
701 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
702 int column
, int page_addr
)
704 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
706 /* Emulate NAND_CMD_READOOB */
707 if (command
== NAND_CMD_READOOB
) {
708 column
+= mtd
->writesize
;
709 command
= NAND_CMD_READ0
;
712 /* Command latch cycle */
713 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
715 if (column
!= -1 || page_addr
!= -1) {
716 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
718 /* Serially input address */
720 /* Adjust columns for 16 bit buswidth */
721 if (chip
->options
& NAND_BUSWIDTH_16
&&
722 !nand_opcode_8bits(command
))
724 chip
->cmd_ctrl(mtd
, column
, ctrl
);
725 ctrl
&= ~NAND_CTRL_CHANGE
;
726 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
728 if (page_addr
!= -1) {
729 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
730 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
731 NAND_NCE
| NAND_ALE
);
732 /* One more address cycle for devices > 128MiB */
733 if (chip
->chipsize
> (128 << 20))
734 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
735 NAND_NCE
| NAND_ALE
);
738 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
741 * Program and erase have their own busy handlers status, sequential
742 * in and status need no delay.
746 case NAND_CMD_CACHEDPROG
:
747 case NAND_CMD_PAGEPROG
:
748 case NAND_CMD_ERASE1
:
749 case NAND_CMD_ERASE2
:
752 case NAND_CMD_STATUS
:
758 udelay(chip
->chip_delay
);
759 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
760 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
761 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
762 NAND_NCE
| NAND_CTRL_CHANGE
);
763 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
764 nand_wait_status_ready(mtd
, 250);
767 case NAND_CMD_RNDOUT
:
768 /* No ready / busy check necessary */
769 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
770 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
771 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
772 NAND_NCE
| NAND_CTRL_CHANGE
);
776 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
777 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
778 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
779 NAND_NCE
| NAND_CTRL_CHANGE
);
781 /* This applies to read commands */
784 * If we don't have access to the busy pin, we apply the given
787 if (!chip
->dev_ready
) {
788 udelay(chip
->chip_delay
);
794 * Apply this short delay always to ensure that we do wait tWB in
795 * any case on any machine.
799 nand_wait_ready(mtd
);
803 * panic_nand_get_device - [GENERIC] Get chip for selected access
804 * @chip: the nand chip descriptor
805 * @mtd: MTD device structure
806 * @new_state: the state which is requested
808 * Used when in panic, no locks are taken.
810 static void panic_nand_get_device(struct nand_chip
*chip
,
811 struct mtd_info
*mtd
, int new_state
)
813 /* Hardware controller shared among independent devices */
814 chip
->controller
->active
= chip
;
815 chip
->state
= new_state
;
819 * nand_get_device - [GENERIC] Get chip for selected access
820 * @mtd: MTD device structure
821 * @new_state: the state which is requested
823 * Get the device and lock it for exclusive access
826 nand_get_device(struct mtd_info
*mtd
, int new_state
)
828 struct nand_chip
*chip
= mtd_to_nand(mtd
);
829 chip
->state
= new_state
;
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
843 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
847 for (i
= 0; i
< timeo
; i
++) {
848 if (chip
->dev_ready
) {
849 if (chip
->dev_ready(mtd
))
852 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
864 * Wait for command done. This applies to erase and program only.
866 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
869 unsigned long timeo
= 400;
871 led_trigger_event(nand_led_trigger
, LED_FULL
);
874 * Apply this short delay always to ensure that we do wait tWB in any
875 * case on any machine.
879 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
881 u32 timer
= (CONFIG_SYS_HZ
* timeo
) / 1000;
884 time_start
= get_timer(0);
885 while (get_timer(time_start
) < timer
) {
886 if (chip
->dev_ready
) {
887 if (chip
->dev_ready(mtd
))
890 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
894 led_trigger_event(nand_led_trigger
, LED_OFF
);
896 status
= (int)chip
->read_byte(mtd
);
897 /* This can happen if in case of timeout or buggy dev_ready */
898 WARN_ON(!(status
& NAND_STATUS_READY
));
902 #define BITS_PER_BYTE 8
905 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
906 * @buf: buffer to test
907 * @len: buffer length
908 * @bitflips_threshold: maximum number of bitflips
910 * Check if a buffer contains only 0xff, which means the underlying region
911 * has been erased and is ready to be programmed.
912 * The bitflips_threshold specify the maximum number of bitflips before
913 * considering the region is not erased.
914 * Note: The logic of this function has been extracted from the memweight
915 * implementation, except that nand_check_erased_buf function exit before
916 * testing the whole buffer if the number of bitflips exceed the
917 * bitflips_threshold value.
919 * Returns a positive number of bitflips less than or equal to
920 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
923 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
925 const unsigned char *bitmap
= buf
;
929 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
931 weight
= hweight8(*bitmap
);
932 bitflips
+= BITS_PER_BYTE
- weight
;
933 if (unlikely(bitflips
> bitflips_threshold
))
937 for (; len
>= 4; len
-= 4, bitmap
+= 4) {
938 weight
= hweight32(*((u32
*)bitmap
));
939 bitflips
+= 32 - weight
;
940 if (unlikely(bitflips
> bitflips_threshold
))
944 for (; len
> 0; len
--, bitmap
++) {
945 weight
= hweight8(*bitmap
);
946 bitflips
+= BITS_PER_BYTE
- weight
;
947 if (unlikely(bitflips
> bitflips_threshold
))
955 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
957 * @data: data buffer to test
958 * @datalen: data length
960 * @ecclen: ECC length
961 * @extraoob: extra OOB buffer
962 * @extraooblen: extra OOB length
963 * @bitflips_threshold: maximum number of bitflips
965 * Check if a data buffer and its associated ECC and OOB data contains only
966 * 0xff pattern, which means the underlying region has been erased and is
967 * ready to be programmed.
968 * The bitflips_threshold specify the maximum number of bitflips before
969 * considering the region as not erased.
972 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
973 * different from the NAND page size. When fixing bitflips, ECC engines will
974 * report the number of errors per chunk, and the NAND core infrastructure
975 * expect you to return the maximum number of bitflips for the whole page.
976 * This is why you should always use this function on a single chunk and
977 * not on the whole page. After checking each chunk you should update your
978 * max_bitflips value accordingly.
979 * 2/ When checking for bitflips in erased pages you should not only check
980 * the payload data but also their associated ECC data, because a user might
981 * have programmed almost all bits to 1 but a few. In this case, we
982 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
984 * 3/ The extraoob argument is optional, and should be used if some of your OOB
985 * data are protected by the ECC engine.
986 * It could also be used if you support subpages and want to attach some
987 * extra OOB data to an ECC chunk.
989 * Returns a positive number of bitflips less than or equal to
990 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
991 * threshold. In case of success, the passed buffers are filled with 0xff.
993 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
994 void *ecc
, int ecclen
,
995 void *extraoob
, int extraooblen
,
996 int bitflips_threshold
)
998 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1000 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1001 bitflips_threshold
);
1002 if (data_bitflips
< 0)
1003 return data_bitflips
;
1005 bitflips_threshold
-= data_bitflips
;
1007 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1008 if (ecc_bitflips
< 0)
1009 return ecc_bitflips
;
1011 bitflips_threshold
-= ecc_bitflips
;
1013 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1014 bitflips_threshold
);
1015 if (extraoob_bitflips
< 0)
1016 return extraoob_bitflips
;
1019 memset(data
, 0xff, datalen
);
1022 memset(ecc
, 0xff, ecclen
);
1024 if (extraoob_bitflips
)
1025 memset(extraoob
, 0xff, extraooblen
);
1027 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1029 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1032 * nand_read_page_raw - [INTERN] read raw page data without ecc
1033 * @mtd: mtd info structure
1034 * @chip: nand chip info structure
1035 * @buf: buffer to store read data
1036 * @oob_required: caller requires OOB data read to chip->oob_poi
1037 * @page: page number to read
1039 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1041 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1042 uint8_t *buf
, int oob_required
, int page
)
1044 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1046 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1051 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1052 * @mtd: mtd info structure
1053 * @chip: nand chip info structure
1054 * @buf: buffer to store read data
1055 * @oob_required: caller requires OOB data read to chip->oob_poi
1056 * @page: page number to read
1058 * We need a special oob layout and handling even when OOB isn't used.
1060 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1061 struct nand_chip
*chip
, uint8_t *buf
,
1062 int oob_required
, int page
)
1064 int eccsize
= chip
->ecc
.size
;
1065 int eccbytes
= chip
->ecc
.bytes
;
1066 uint8_t *oob
= chip
->oob_poi
;
1069 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1070 chip
->read_buf(mtd
, buf
, eccsize
);
1073 if (chip
->ecc
.prepad
) {
1074 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1075 oob
+= chip
->ecc
.prepad
;
1078 chip
->read_buf(mtd
, oob
, eccbytes
);
1081 if (chip
->ecc
.postpad
) {
1082 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1083 oob
+= chip
->ecc
.postpad
;
1087 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1089 chip
->read_buf(mtd
, oob
, size
);
1095 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1096 * @mtd: mtd info structure
1097 * @chip: nand chip info structure
1098 * @buf: buffer to store read data
1099 * @oob_required: caller requires OOB data read to chip->oob_poi
1100 * @page: page number to read
1102 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1103 uint8_t *buf
, int oob_required
, int page
)
1105 int i
, eccsize
= chip
->ecc
.size
;
1106 int eccbytes
= chip
->ecc
.bytes
;
1107 int eccsteps
= chip
->ecc
.steps
;
1109 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1110 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1111 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1112 unsigned int max_bitflips
= 0;
1114 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1116 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1117 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1119 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1120 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1122 eccsteps
= chip
->ecc
.steps
;
1125 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1128 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1130 mtd
->ecc_stats
.failed
++;
1132 mtd
->ecc_stats
.corrected
+= stat
;
1133 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1136 return max_bitflips
;
1140 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1141 * @mtd: mtd info structure
1142 * @chip: nand chip info structure
1143 * @data_offs: offset of requested data within the page
1144 * @readlen: data length
1145 * @bufpoi: buffer to store read data
1146 * @page: page number to read
1148 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1149 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1152 int start_step
, end_step
, num_steps
;
1153 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1155 int data_col_addr
, i
, gaps
= 0;
1156 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1157 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1159 unsigned int max_bitflips
= 0;
1161 /* Column address within the page aligned to ECC size (256bytes) */
1162 start_step
= data_offs
/ chip
->ecc
.size
;
1163 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1164 num_steps
= end_step
- start_step
+ 1;
1165 index
= start_step
* chip
->ecc
.bytes
;
1167 /* Data size aligned to ECC ecc.size */
1168 datafrag_len
= num_steps
* chip
->ecc
.size
;
1169 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1171 data_col_addr
= start_step
* chip
->ecc
.size
;
1172 /* If we read not a page aligned data */
1173 if (data_col_addr
!= 0)
1174 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1176 p
= bufpoi
+ data_col_addr
;
1177 chip
->read_buf(mtd
, p
, datafrag_len
);
1180 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1181 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1184 * The performance is faster if we position offsets according to
1185 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1187 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1188 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1194 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1195 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1198 * Send the command to read the particular ECC bytes take care
1199 * about buswidth alignment in read_buf.
1201 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1202 aligned_len
= eccfrag_len
;
1203 if (eccpos
[index
] & (busw
- 1))
1205 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1208 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1209 mtd
->writesize
+ aligned_pos
, -1);
1210 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1213 for (i
= 0; i
< eccfrag_len
; i
++)
1214 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1216 p
= bufpoi
+ data_col_addr
;
1217 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1220 stat
= chip
->ecc
.correct(mtd
, p
,
1221 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1222 if (stat
== -EBADMSG
&&
1223 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1224 /* check for empty pages with bitflips */
1225 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1226 &chip
->buffers
->ecccode
[i
],
1229 chip
->ecc
.strength
);
1233 mtd
->ecc_stats
.failed
++;
1235 mtd
->ecc_stats
.corrected
+= stat
;
1236 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1239 return max_bitflips
;
1243 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1244 * @mtd: mtd info structure
1245 * @chip: nand chip info structure
1246 * @buf: buffer to store read data
1247 * @oob_required: caller requires OOB data read to chip->oob_poi
1248 * @page: page number to read
1250 * Not for syndrome calculating ECC controllers which need a special oob layout.
1252 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1253 uint8_t *buf
, int oob_required
, int page
)
1255 int i
, eccsize
= chip
->ecc
.size
;
1256 int eccbytes
= chip
->ecc
.bytes
;
1257 int eccsteps
= chip
->ecc
.steps
;
1259 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1260 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1261 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1262 unsigned int max_bitflips
= 0;
1264 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1265 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1266 chip
->read_buf(mtd
, p
, eccsize
);
1267 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1269 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1271 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1272 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1274 eccsteps
= chip
->ecc
.steps
;
1277 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1280 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1281 if (stat
== -EBADMSG
&&
1282 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1283 /* check for empty pages with bitflips */
1284 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1285 &ecc_code
[i
], eccbytes
,
1287 chip
->ecc
.strength
);
1291 mtd
->ecc_stats
.failed
++;
1293 mtd
->ecc_stats
.corrected
+= stat
;
1294 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1297 return max_bitflips
;
1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1305 * @oob_required: caller requires OOB data read to chip->oob_poi
1306 * @page: page number to read
1308 * Hardware ECC for large page chips, require OOB to be read first. For this
1309 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1310 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1311 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1312 * the data area, by overwriting the NAND manufacturer bad block markings.
1314 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1315 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1317 int i
, eccsize
= chip
->ecc
.size
;
1318 int eccbytes
= chip
->ecc
.bytes
;
1319 int eccsteps
= chip
->ecc
.steps
;
1321 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1322 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1323 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1324 unsigned int max_bitflips
= 0;
1326 /* Read the OOB area first */
1327 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1328 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1329 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1331 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1332 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1334 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1337 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1338 chip
->read_buf(mtd
, p
, eccsize
);
1339 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1341 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1342 if (stat
== -EBADMSG
&&
1343 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1344 /* check for empty pages with bitflips */
1345 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1346 &ecc_code
[i
], eccbytes
,
1348 chip
->ecc
.strength
);
1352 mtd
->ecc_stats
.failed
++;
1354 mtd
->ecc_stats
.corrected
+= stat
;
1355 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1358 return max_bitflips
;
1362 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1363 * @mtd: mtd info structure
1364 * @chip: nand chip info structure
1365 * @buf: buffer to store read data
1366 * @oob_required: caller requires OOB data read to chip->oob_poi
1367 * @page: page number to read
1369 * The hw generator calculates the error syndrome automatically. Therefore we
1370 * need a special oob layout and handling.
1372 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1373 uint8_t *buf
, int oob_required
, int page
)
1375 int i
, eccsize
= chip
->ecc
.size
;
1376 int eccbytes
= chip
->ecc
.bytes
;
1377 int eccsteps
= chip
->ecc
.steps
;
1378 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1380 uint8_t *oob
= chip
->oob_poi
;
1381 unsigned int max_bitflips
= 0;
1383 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1386 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1387 chip
->read_buf(mtd
, p
, eccsize
);
1389 if (chip
->ecc
.prepad
) {
1390 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1391 oob
+= chip
->ecc
.prepad
;
1394 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1395 chip
->read_buf(mtd
, oob
, eccbytes
);
1396 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1400 if (chip
->ecc
.postpad
) {
1401 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1402 oob
+= chip
->ecc
.postpad
;
1405 if (stat
== -EBADMSG
&&
1406 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1407 /* check for empty pages with bitflips */
1408 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1412 chip
->ecc
.strength
);
1416 mtd
->ecc_stats
.failed
++;
1418 mtd
->ecc_stats
.corrected
+= stat
;
1419 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1423 /* Calculate remaining oob bytes */
1424 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1426 chip
->read_buf(mtd
, oob
, i
);
1428 return max_bitflips
;
1432 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1433 * @chip: nand chip structure
1434 * @oob: oob destination address
1435 * @ops: oob ops structure
1436 * @len: size of oob to transfer
1438 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1439 struct mtd_oob_ops
*ops
, size_t len
)
1441 switch (ops
->mode
) {
1443 case MTD_OPS_PLACE_OOB
:
1445 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1448 case MTD_OPS_AUTO_OOB
: {
1449 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1450 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1453 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1454 /* Read request not from offset 0? */
1455 if (unlikely(roffs
)) {
1456 if (roffs
>= free
->length
) {
1457 roffs
-= free
->length
;
1460 boffs
= free
->offset
+ roffs
;
1461 bytes
= min_t(size_t, len
,
1462 (free
->length
- roffs
));
1465 bytes
= min_t(size_t, len
, free
->length
);
1466 boffs
= free
->offset
;
1468 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1480 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1481 * @mtd: MTD device structure
1482 * @retry_mode: the retry mode to use
1484 * Some vendors supply a special command to shift the Vt threshold, to be used
1485 * when there are too many bitflips in a page (i.e., ECC error). After setting
1486 * a new threshold, the host should retry reading the page.
1488 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1490 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1492 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1494 if (retry_mode
>= chip
->read_retries
)
1497 if (!chip
->setup_read_retry
)
1500 return chip
->setup_read_retry(mtd
, retry_mode
);
1504 * nand_do_read_ops - [INTERN] Read data with ECC
1505 * @mtd: MTD device structure
1506 * @from: offset to read from
1507 * @ops: oob ops structure
1509 * Internal function. Called with chip held.
1511 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1512 struct mtd_oob_ops
*ops
)
1514 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1515 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1517 uint32_t readlen
= ops
->len
;
1518 uint32_t oobreadlen
= ops
->ooblen
;
1519 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1521 uint8_t *bufpoi
, *oob
, *buf
;
1523 unsigned int max_bitflips
= 0;
1525 bool ecc_fail
= false;
1527 chipnr
= (int)(from
>> chip
->chip_shift
);
1528 chip
->select_chip(mtd
, chipnr
);
1530 realpage
= (int)(from
>> chip
->page_shift
);
1531 page
= realpage
& chip
->pagemask
;
1533 col
= (int)(from
& (mtd
->writesize
- 1));
1537 oob_required
= oob
? 1 : 0;
1540 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1543 bytes
= min(mtd
->writesize
- col
, readlen
);
1544 aligned
= (bytes
== mtd
->writesize
);
1551 /* Is the current page in the buffer? */
1552 if (realpage
!= chip
->pagebuf
|| oob
) {
1553 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1555 if (use_bufpoi
&& aligned
)
1556 pr_debug("%s: using read bounce buffer for buf@%p\n",
1560 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1563 * Now read the page into the buffer. Absent an error,
1564 * the read methods return max bitflips per ecc step.
1566 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1567 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1570 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1572 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1576 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1577 oob_required
, page
);
1580 /* Invalidate page cache */
1585 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1587 /* Transfer not aligned data */
1589 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1590 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1591 (ops
->mode
!= MTD_OPS_RAW
)) {
1592 chip
->pagebuf
= realpage
;
1593 chip
->pagebuf_bitflips
= ret
;
1595 /* Invalidate page cache */
1598 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1601 if (unlikely(oob
)) {
1602 int toread
= min(oobreadlen
, max_oobsize
);
1605 oob
= nand_transfer_oob(chip
,
1607 oobreadlen
-= toread
;
1611 if (chip
->options
& NAND_NEED_READRDY
) {
1612 /* Apply delay or wait for ready/busy pin */
1613 if (!chip
->dev_ready
)
1614 udelay(chip
->chip_delay
);
1616 nand_wait_ready(mtd
);
1619 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1620 if (retry_mode
+ 1 < chip
->read_retries
) {
1622 ret
= nand_setup_read_retry(mtd
,
1627 /* Reset failures; retry */
1628 mtd
->ecc_stats
.failed
= ecc_failures
;
1631 /* No more retry modes; real failure */
1638 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1640 max_bitflips
= max_t(unsigned int, max_bitflips
,
1641 chip
->pagebuf_bitflips
);
1646 /* Reset to retry mode 0 */
1648 ret
= nand_setup_read_retry(mtd
, 0);
1657 /* For subsequent reads align to page boundary */
1659 /* Increment page address */
1662 page
= realpage
& chip
->pagemask
;
1663 /* Check, if we cross a chip boundary */
1666 chip
->select_chip(mtd
, -1);
1667 chip
->select_chip(mtd
, chipnr
);
1670 chip
->select_chip(mtd
, -1);
1672 ops
->retlen
= ops
->len
- (size_t) readlen
;
1674 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1682 return max_bitflips
;
1686 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1687 * @mtd: MTD device structure
1688 * @from: offset to read from
1689 * @len: number of bytes to read
1690 * @retlen: pointer to variable to store the number of read bytes
1691 * @buf: the databuffer to put data
1693 * Get hold of the chip and call nand_do_read.
1695 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1696 size_t *retlen
, uint8_t *buf
)
1698 struct mtd_oob_ops ops
;
1701 nand_get_device(mtd
, FL_READING
);
1702 memset(&ops
, 0, sizeof(ops
));
1705 ops
.mode
= MTD_OPS_PLACE_OOB
;
1706 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1707 *retlen
= ops
.retlen
;
1708 nand_release_device(mtd
);
1713 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1714 * @mtd: mtd info structure
1715 * @chip: nand chip info structure
1716 * @page: page number to read
1718 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1721 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1722 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1727 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1729 * @mtd: mtd info structure
1730 * @chip: nand chip info structure
1731 * @page: page number to read
1733 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1736 int length
= mtd
->oobsize
;
1737 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1738 int eccsize
= chip
->ecc
.size
;
1739 uint8_t *bufpoi
= chip
->oob_poi
;
1740 int i
, toread
, sndrnd
= 0, pos
;
1742 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1743 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1745 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1746 if (mtd
->writesize
> 512)
1747 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1749 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1752 toread
= min_t(int, length
, chunk
);
1753 chip
->read_buf(mtd
, bufpoi
, toread
);
1758 chip
->read_buf(mtd
, bufpoi
, length
);
1764 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1765 * @mtd: mtd info structure
1766 * @chip: nand chip info structure
1767 * @page: page number to write
1769 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1773 const uint8_t *buf
= chip
->oob_poi
;
1774 int length
= mtd
->oobsize
;
1776 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1777 chip
->write_buf(mtd
, buf
, length
);
1778 /* Send command to program the OOB data */
1779 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1781 status
= chip
->waitfunc(mtd
, chip
);
1783 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1787 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1788 * with syndrome - only for large page flash
1789 * @mtd: mtd info structure
1790 * @chip: nand chip info structure
1791 * @page: page number to write
1793 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1794 struct nand_chip
*chip
, int page
)
1796 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1797 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1798 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1799 const uint8_t *bufpoi
= chip
->oob_poi
;
1802 * data-ecc-data-ecc ... ecc-oob
1804 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1806 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1807 pos
= steps
* (eccsize
+ chunk
);
1812 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1813 for (i
= 0; i
< steps
; i
++) {
1815 if (mtd
->writesize
<= 512) {
1816 uint32_t fill
= 0xFFFFFFFF;
1820 int num
= min_t(int, len
, 4);
1821 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1826 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1827 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1831 len
= min_t(int, length
, chunk
);
1832 chip
->write_buf(mtd
, bufpoi
, len
);
1837 chip
->write_buf(mtd
, bufpoi
, length
);
1839 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1840 status
= chip
->waitfunc(mtd
, chip
);
1842 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1846 * nand_do_read_oob - [INTERN] NAND read out-of-band
1847 * @mtd: MTD device structure
1848 * @from: offset to read from
1849 * @ops: oob operations description structure
1851 * NAND read out-of-band data from the spare area.
1853 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1854 struct mtd_oob_ops
*ops
)
1856 int page
, realpage
, chipnr
;
1857 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1858 struct mtd_ecc_stats stats
;
1859 int readlen
= ops
->ooblen
;
1861 uint8_t *buf
= ops
->oobbuf
;
1864 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1865 __func__
, (unsigned long long)from
, readlen
);
1867 stats
= mtd
->ecc_stats
;
1869 len
= mtd_oobavail(mtd
, ops
);
1871 if (unlikely(ops
->ooboffs
>= len
)) {
1872 pr_debug("%s: attempt to start read outside oob\n",
1877 /* Do not allow reads past end of device */
1878 if (unlikely(from
>= mtd
->size
||
1879 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1880 (from
>> chip
->page_shift
)) * len
)) {
1881 pr_debug("%s: attempt to read beyond end of device\n",
1886 chipnr
= (int)(from
>> chip
->chip_shift
);
1887 chip
->select_chip(mtd
, chipnr
);
1889 /* Shift to get page */
1890 realpage
= (int)(from
>> chip
->page_shift
);
1891 page
= realpage
& chip
->pagemask
;
1896 if (ops
->mode
== MTD_OPS_RAW
)
1897 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
1899 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
1904 len
= min(len
, readlen
);
1905 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1907 if (chip
->options
& NAND_NEED_READRDY
) {
1908 /* Apply delay or wait for ready/busy pin */
1909 if (!chip
->dev_ready
)
1910 udelay(chip
->chip_delay
);
1912 nand_wait_ready(mtd
);
1919 /* Increment page address */
1922 page
= realpage
& chip
->pagemask
;
1923 /* Check, if we cross a chip boundary */
1926 chip
->select_chip(mtd
, -1);
1927 chip
->select_chip(mtd
, chipnr
);
1930 chip
->select_chip(mtd
, -1);
1932 ops
->oobretlen
= ops
->ooblen
- readlen
;
1937 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1940 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1944 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1945 * @mtd: MTD device structure
1946 * @from: offset to read from
1947 * @ops: oob operation description structure
1949 * NAND read data and/or out-of-band data.
1951 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1952 struct mtd_oob_ops
*ops
)
1954 int ret
= -ENOTSUPP
;
1958 /* Do not allow reads past end of device */
1959 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1960 pr_debug("%s: attempt to read beyond end of device\n",
1965 nand_get_device(mtd
, FL_READING
);
1967 switch (ops
->mode
) {
1968 case MTD_OPS_PLACE_OOB
:
1969 case MTD_OPS_AUTO_OOB
:
1978 ret
= nand_do_read_oob(mtd
, from
, ops
);
1980 ret
= nand_do_read_ops(mtd
, from
, ops
);
1983 nand_release_device(mtd
);
1989 * nand_write_page_raw - [INTERN] raw page write function
1990 * @mtd: mtd info structure
1991 * @chip: nand chip info structure
1993 * @oob_required: must write chip->oob_poi to OOB
1994 * @page: page number to write
1996 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1998 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1999 const uint8_t *buf
, int oob_required
, int page
)
2001 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2003 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2009 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2010 * @mtd: mtd info structure
2011 * @chip: nand chip info structure
2013 * @oob_required: must write chip->oob_poi to OOB
2014 * @page: page number to write
2016 * We need a special oob layout and handling even when ECC isn't checked.
2018 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2019 struct nand_chip
*chip
,
2020 const uint8_t *buf
, int oob_required
,
2023 int eccsize
= chip
->ecc
.size
;
2024 int eccbytes
= chip
->ecc
.bytes
;
2025 uint8_t *oob
= chip
->oob_poi
;
2028 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2029 chip
->write_buf(mtd
, buf
, eccsize
);
2032 if (chip
->ecc
.prepad
) {
2033 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2034 oob
+= chip
->ecc
.prepad
;
2037 chip
->write_buf(mtd
, oob
, eccbytes
);
2040 if (chip
->ecc
.postpad
) {
2041 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2042 oob
+= chip
->ecc
.postpad
;
2046 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2048 chip
->write_buf(mtd
, oob
, size
);
2053 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2054 * @mtd: mtd info structure
2055 * @chip: nand chip info structure
2057 * @oob_required: must write chip->oob_poi to OOB
2058 * @page: page number to write
2060 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2061 const uint8_t *buf
, int oob_required
,
2064 int i
, eccsize
= chip
->ecc
.size
;
2065 int eccbytes
= chip
->ecc
.bytes
;
2066 int eccsteps
= chip
->ecc
.steps
;
2067 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2068 const uint8_t *p
= buf
;
2069 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2071 /* Software ECC calculation */
2072 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2073 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2075 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2076 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2078 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2082 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2083 * @mtd: mtd info structure
2084 * @chip: nand chip info structure
2086 * @oob_required: must write chip->oob_poi to OOB
2087 * @page: page number to write
2089 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2090 const uint8_t *buf
, int oob_required
,
2093 int i
, eccsize
= chip
->ecc
.size
;
2094 int eccbytes
= chip
->ecc
.bytes
;
2095 int eccsteps
= chip
->ecc
.steps
;
2096 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2097 const uint8_t *p
= buf
;
2098 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2100 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2101 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2102 chip
->write_buf(mtd
, p
, eccsize
);
2103 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2106 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2107 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2109 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2116 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2117 * @mtd: mtd info structure
2118 * @chip: nand chip info structure
2119 * @offset: column address of subpage within the page
2120 * @data_len: data length
2122 * @oob_required: must write chip->oob_poi to OOB
2123 * @page: page number to write
2125 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2126 struct nand_chip
*chip
, uint32_t offset
,
2127 uint32_t data_len
, const uint8_t *buf
,
2128 int oob_required
, int page
)
2130 uint8_t *oob_buf
= chip
->oob_poi
;
2131 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2132 int ecc_size
= chip
->ecc
.size
;
2133 int ecc_bytes
= chip
->ecc
.bytes
;
2134 int ecc_steps
= chip
->ecc
.steps
;
2135 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2136 uint32_t start_step
= offset
/ ecc_size
;
2137 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2138 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2141 for (step
= 0; step
< ecc_steps
; step
++) {
2142 /* configure controller for WRITE access */
2143 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2145 /* write data (untouched subpages already masked by 0xFF) */
2146 chip
->write_buf(mtd
, buf
, ecc_size
);
2148 /* mask ECC of un-touched subpages by padding 0xFF */
2149 if ((step
< start_step
) || (step
> end_step
))
2150 memset(ecc_calc
, 0xff, ecc_bytes
);
2152 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2154 /* mask OOB of un-touched subpages by padding 0xFF */
2155 /* if oob_required, preserve OOB metadata of written subpage */
2156 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2157 memset(oob_buf
, 0xff, oob_bytes
);
2160 ecc_calc
+= ecc_bytes
;
2161 oob_buf
+= oob_bytes
;
2164 /* copy calculated ECC for whole page to chip->buffer->oob */
2165 /* this include masked-value(0xFF) for unwritten subpages */
2166 ecc_calc
= chip
->buffers
->ecccalc
;
2167 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2168 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2170 /* write OOB buffer to NAND device */
2171 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2178 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2179 * @mtd: mtd info structure
2180 * @chip: nand chip info structure
2182 * @oob_required: must write chip->oob_poi to OOB
2183 * @page: page number to write
2185 * The hw generator calculates the error syndrome automatically. Therefore we
2186 * need a special oob layout and handling.
2188 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2189 struct nand_chip
*chip
,
2190 const uint8_t *buf
, int oob_required
,
2193 int i
, eccsize
= chip
->ecc
.size
;
2194 int eccbytes
= chip
->ecc
.bytes
;
2195 int eccsteps
= chip
->ecc
.steps
;
2196 const uint8_t *p
= buf
;
2197 uint8_t *oob
= chip
->oob_poi
;
2199 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2201 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2202 chip
->write_buf(mtd
, p
, eccsize
);
2204 if (chip
->ecc
.prepad
) {
2205 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2206 oob
+= chip
->ecc
.prepad
;
2209 chip
->ecc
.calculate(mtd
, p
, oob
);
2210 chip
->write_buf(mtd
, oob
, eccbytes
);
2213 if (chip
->ecc
.postpad
) {
2214 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2215 oob
+= chip
->ecc
.postpad
;
2219 /* Calculate remaining oob bytes */
2220 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2222 chip
->write_buf(mtd
, oob
, i
);
2228 * nand_write_page - [REPLACEABLE] write one page
2229 * @mtd: MTD device structure
2230 * @chip: NAND chip descriptor
2231 * @offset: address offset within the page
2232 * @data_len: length of actual data to be written
2233 * @buf: the data to write
2234 * @oob_required: must write chip->oob_poi to OOB
2235 * @page: page number to write
2236 * @cached: cached programming
2237 * @raw: use _raw version of write_page
2239 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2240 uint32_t offset
, int data_len
, const uint8_t *buf
,
2241 int oob_required
, int page
, int cached
, int raw
)
2243 int status
, subpage
;
2245 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2246 chip
->ecc
.write_subpage
)
2247 subpage
= offset
|| (data_len
< mtd
->writesize
);
2251 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2254 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2255 oob_required
, page
);
2257 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2258 buf
, oob_required
, page
);
2260 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2267 * Cached progamming disabled for now. Not sure if it's worth the
2268 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2272 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2274 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2275 status
= chip
->waitfunc(mtd
, chip
);
2277 * See if operation failed and additional status checks are
2280 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2281 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2284 if (status
& NAND_STATUS_FAIL
)
2287 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2288 status
= chip
->waitfunc(mtd
, chip
);
2295 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2296 * @mtd: MTD device structure
2297 * @oob: oob data buffer
2298 * @len: oob data write length
2299 * @ops: oob ops structure
2301 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2302 struct mtd_oob_ops
*ops
)
2304 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2307 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2308 * data from a previous OOB read.
2310 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2312 switch (ops
->mode
) {
2314 case MTD_OPS_PLACE_OOB
:
2316 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2319 case MTD_OPS_AUTO_OOB
: {
2320 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2321 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2324 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2325 /* Write request not from offset 0? */
2326 if (unlikely(woffs
)) {
2327 if (woffs
>= free
->length
) {
2328 woffs
-= free
->length
;
2331 boffs
= free
->offset
+ woffs
;
2332 bytes
= min_t(size_t, len
,
2333 (free
->length
- woffs
));
2336 bytes
= min_t(size_t, len
, free
->length
);
2337 boffs
= free
->offset
;
2339 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2350 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2353 * nand_do_write_ops - [INTERN] NAND write with ECC
2354 * @mtd: MTD device structure
2355 * @to: offset to write to
2356 * @ops: oob operations description structure
2358 * NAND write with ECC.
2360 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2361 struct mtd_oob_ops
*ops
)
2363 int chipnr
, realpage
, page
, blockmask
, column
;
2364 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2365 uint32_t writelen
= ops
->len
;
2367 uint32_t oobwritelen
= ops
->ooblen
;
2368 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2370 uint8_t *oob
= ops
->oobbuf
;
2371 uint8_t *buf
= ops
->datbuf
;
2373 int oob_required
= oob
? 1 : 0;
2379 /* Reject writes, which are not page aligned */
2380 if (NOTALIGNED(to
)) {
2381 pr_notice("%s: attempt to write non page aligned data\n",
2386 column
= to
& (mtd
->writesize
- 1);
2388 chipnr
= (int)(to
>> chip
->chip_shift
);
2389 chip
->select_chip(mtd
, chipnr
);
2391 /* Check, if it is write protected */
2392 if (nand_check_wp(mtd
)) {
2397 realpage
= (int)(to
>> chip
->page_shift
);
2398 page
= realpage
& chip
->pagemask
;
2399 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2401 /* Invalidate the page cache, when we write to the cached page */
2402 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2403 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2406 /* Don't allow multipage oob writes with offset */
2407 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2413 int bytes
= mtd
->writesize
;
2414 int cached
= writelen
> bytes
&& page
!= blockmask
;
2415 uint8_t *wbuf
= buf
;
2417 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2425 /* Partial page write?, or need to use bounce buffer */
2427 pr_debug("%s: using write bounce buffer for buf@%p\n",
2431 bytes
= min_t(int, bytes
- column
, writelen
);
2433 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2434 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2435 wbuf
= chip
->buffers
->databuf
;
2438 if (unlikely(oob
)) {
2439 size_t len
= min(oobwritelen
, oobmaxlen
);
2440 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2443 /* We still need to erase leftover OOB data */
2444 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2446 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2447 oob_required
, page
, cached
,
2448 (ops
->mode
== MTD_OPS_RAW
));
2460 page
= realpage
& chip
->pagemask
;
2461 /* Check, if we cross a chip boundary */
2464 chip
->select_chip(mtd
, -1);
2465 chip
->select_chip(mtd
, chipnr
);
2469 ops
->retlen
= ops
->len
- writelen
;
2471 ops
->oobretlen
= ops
->ooblen
;
2474 chip
->select_chip(mtd
, -1);
2479 * panic_nand_write - [MTD Interface] NAND write with ECC
2480 * @mtd: MTD device structure
2481 * @to: offset to write to
2482 * @len: number of bytes to write
2483 * @retlen: pointer to variable to store the number of written bytes
2484 * @buf: the data to write
2486 * NAND write with ECC. Used when performing writes in interrupt context, this
2487 * may for example be called by mtdoops when writing an oops while in panic.
2489 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2490 size_t *retlen
, const uint8_t *buf
)
2492 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2493 struct mtd_oob_ops ops
;
2496 /* Wait for the device to get ready */
2497 panic_nand_wait(mtd
, chip
, 400);
2499 /* Grab the device */
2500 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2502 memset(&ops
, 0, sizeof(ops
));
2504 ops
.datbuf
= (uint8_t *)buf
;
2505 ops
.mode
= MTD_OPS_PLACE_OOB
;
2507 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2509 *retlen
= ops
.retlen
;
2514 * nand_write - [MTD Interface] NAND write with ECC
2515 * @mtd: MTD device structure
2516 * @to: offset to write to
2517 * @len: number of bytes to write
2518 * @retlen: pointer to variable to store the number of written bytes
2519 * @buf: the data to write
2521 * NAND write with ECC.
2523 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2524 size_t *retlen
, const uint8_t *buf
)
2526 struct mtd_oob_ops ops
;
2529 nand_get_device(mtd
, FL_WRITING
);
2530 memset(&ops
, 0, sizeof(ops
));
2532 ops
.datbuf
= (uint8_t *)buf
;
2533 ops
.mode
= MTD_OPS_PLACE_OOB
;
2534 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2535 *retlen
= ops
.retlen
;
2536 nand_release_device(mtd
);
2541 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2542 * @mtd: MTD device structure
2543 * @to: offset to write to
2544 * @ops: oob operation description structure
2546 * NAND write out-of-band.
2548 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2549 struct mtd_oob_ops
*ops
)
2551 int chipnr
, page
, status
, len
;
2552 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2554 pr_debug("%s: to = 0x%08x, len = %i\n",
2555 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2557 len
= mtd_oobavail(mtd
, ops
);
2559 /* Do not allow write past end of page */
2560 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2561 pr_debug("%s: attempt to write past end of page\n",
2566 if (unlikely(ops
->ooboffs
>= len
)) {
2567 pr_debug("%s: attempt to start write outside oob\n",
2572 /* Do not allow write past end of device */
2573 if (unlikely(to
>= mtd
->size
||
2574 ops
->ooboffs
+ ops
->ooblen
>
2575 ((mtd
->size
>> chip
->page_shift
) -
2576 (to
>> chip
->page_shift
)) * len
)) {
2577 pr_debug("%s: attempt to write beyond end of device\n",
2582 chipnr
= (int)(to
>> chip
->chip_shift
);
2583 chip
->select_chip(mtd
, chipnr
);
2585 /* Shift to get page */
2586 page
= (int)(to
>> chip
->page_shift
);
2589 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2590 * of my DiskOnChip 2000 test units) will clear the whole data page too
2591 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2592 * it in the doc2000 driver in August 1999. dwmw2.
2594 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2596 /* Check, if it is write protected */
2597 if (nand_check_wp(mtd
)) {
2598 chip
->select_chip(mtd
, -1);
2602 /* Invalidate the page cache, if we write to the cached page */
2603 if (page
== chip
->pagebuf
)
2606 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2608 if (ops
->mode
== MTD_OPS_RAW
)
2609 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2611 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2613 chip
->select_chip(mtd
, -1);
2618 ops
->oobretlen
= ops
->ooblen
;
2624 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2625 * @mtd: MTD device structure
2626 * @to: offset to write to
2627 * @ops: oob operation description structure
2629 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2630 struct mtd_oob_ops
*ops
)
2632 int ret
= -ENOTSUPP
;
2636 /* Do not allow writes past end of device */
2637 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2638 pr_debug("%s: attempt to write beyond end of device\n",
2643 nand_get_device(mtd
, FL_WRITING
);
2645 switch (ops
->mode
) {
2646 case MTD_OPS_PLACE_OOB
:
2647 case MTD_OPS_AUTO_OOB
:
2656 ret
= nand_do_write_oob(mtd
, to
, ops
);
2658 ret
= nand_do_write_ops(mtd
, to
, ops
);
2661 nand_release_device(mtd
);
2666 * single_erase - [GENERIC] NAND standard block erase command function
2667 * @mtd: MTD device structure
2668 * @page: the page address of the block which will be erased
2670 * Standard erase command for NAND chips. Returns NAND status.
2672 static int single_erase(struct mtd_info
*mtd
, int page
)
2674 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2675 /* Send commands to erase a block */
2676 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2677 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2679 return chip
->waitfunc(mtd
, chip
);
2683 * nand_erase - [MTD Interface] erase block(s)
2684 * @mtd: MTD device structure
2685 * @instr: erase instruction
2687 * Erase one ore more blocks.
2689 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2691 return nand_erase_nand(mtd
, instr
, 0);
2695 * nand_erase_nand - [INTERN] erase block(s)
2696 * @mtd: MTD device structure
2697 * @instr: erase instruction
2698 * @allowbbt: allow erasing the bbt area
2700 * Erase one ore more blocks.
2702 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2705 int page
, status
, pages_per_block
, ret
, chipnr
;
2706 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2709 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2710 __func__
, (unsigned long long)instr
->addr
,
2711 (unsigned long long)instr
->len
);
2713 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2716 /* Grab the lock and see if the device is available */
2717 nand_get_device(mtd
, FL_ERASING
);
2719 /* Shift to get first page */
2720 page
= (int)(instr
->addr
>> chip
->page_shift
);
2721 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2723 /* Calculate pages in each block */
2724 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2726 /* Select the NAND device */
2727 chip
->select_chip(mtd
, chipnr
);
2729 /* Check, if it is write protected */
2730 if (nand_check_wp(mtd
)) {
2731 pr_debug("%s: device is write protected!\n",
2733 instr
->state
= MTD_ERASE_FAILED
;
2737 /* Loop through the pages */
2740 instr
->state
= MTD_ERASING
;
2745 /* Check if we have a bad block, we do not erase bad blocks! */
2746 if (!instr
->scrub
&& nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2747 chip
->page_shift
, allowbbt
)) {
2748 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2750 instr
->state
= MTD_ERASE_FAILED
;
2755 * Invalidate the page cache, if we erase the block which
2756 * contains the current cached page.
2758 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2759 (page
+ pages_per_block
))
2762 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2765 * See if operation failed and additional status checks are
2768 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2769 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2772 /* See if block erase succeeded */
2773 if (status
& NAND_STATUS_FAIL
) {
2774 pr_debug("%s: failed erase, page 0x%08x\n",
2776 instr
->state
= MTD_ERASE_FAILED
;
2778 ((loff_t
)page
<< chip
->page_shift
);
2782 /* Increment page address and decrement length */
2783 len
-= (1ULL << chip
->phys_erase_shift
);
2784 page
+= pages_per_block
;
2786 /* Check, if we cross a chip boundary */
2787 if (len
&& !(page
& chip
->pagemask
)) {
2789 chip
->select_chip(mtd
, -1);
2790 chip
->select_chip(mtd
, chipnr
);
2793 instr
->state
= MTD_ERASE_DONE
;
2797 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2799 /* Deselect and wake up anyone waiting on the device */
2800 chip
->select_chip(mtd
, -1);
2801 nand_release_device(mtd
);
2803 /* Do call back function */
2805 mtd_erase_callback(instr
);
2807 /* Return more or less happy */
2812 * nand_sync - [MTD Interface] sync
2813 * @mtd: MTD device structure
2815 * Sync is actually a wait for chip ready function.
2817 static void nand_sync(struct mtd_info
*mtd
)
2819 pr_debug("%s: called\n", __func__
);
2821 /* Grab the lock and see if the device is available */
2822 nand_get_device(mtd
, FL_SYNCING
);
2823 /* Release it and go back */
2824 nand_release_device(mtd
);
2828 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2829 * @mtd: MTD device structure
2830 * @offs: offset relative to mtd start
2832 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2834 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2835 int chipnr
= (int)(offs
>> chip
->chip_shift
);
2838 /* Select the NAND device */
2839 nand_get_device(mtd
, FL_READING
);
2840 chip
->select_chip(mtd
, chipnr
);
2842 ret
= nand_block_checkbad(mtd
, offs
, 0);
2844 chip
->select_chip(mtd
, -1);
2845 nand_release_device(mtd
);
2851 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2852 * @mtd: MTD device structure
2853 * @ofs: offset relative to mtd start
2855 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2859 ret
= nand_block_isbad(mtd
, ofs
);
2861 /* If it was bad already, return success and do nothing */
2867 return nand_block_markbad_lowlevel(mtd
, ofs
);
2871 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2872 * @mtd: MTD device structure
2873 * @chip: nand chip info structure
2874 * @addr: feature address.
2875 * @subfeature_param: the subfeature parameters, a four bytes array.
2877 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2878 int addr
, uint8_t *subfeature_param
)
2883 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2884 if (!chip
->onfi_version
||
2885 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
2886 & ONFI_OPT_CMD_SET_GET_FEATURES
))
2890 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
2891 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
2892 chip
->write_byte(mtd
, subfeature_param
[i
]);
2894 status
= chip
->waitfunc(mtd
, chip
);
2895 if (status
& NAND_STATUS_FAIL
)
2901 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2902 * @mtd: MTD device structure
2903 * @chip: nand chip info structure
2904 * @addr: feature address.
2905 * @subfeature_param: the subfeature parameters, a four bytes array.
2907 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2908 int addr
, uint8_t *subfeature_param
)
2912 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2913 if (!chip
->onfi_version
||
2914 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
2915 & ONFI_OPT_CMD_SET_GET_FEATURES
))
2919 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
2920 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
2921 *subfeature_param
++ = chip
->read_byte(mtd
);
2925 /* Set default functions */
2926 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2928 /* check for proper chip_delay setup, set 20us if not */
2929 if (!chip
->chip_delay
)
2930 chip
->chip_delay
= 20;
2932 /* check, if a user supplied command function given */
2933 if (chip
->cmdfunc
== NULL
)
2934 chip
->cmdfunc
= nand_command
;
2936 /* check, if a user supplied wait function given */
2937 if (chip
->waitfunc
== NULL
)
2938 chip
->waitfunc
= nand_wait
;
2940 if (!chip
->select_chip
)
2941 chip
->select_chip
= nand_select_chip
;
2943 /* set for ONFI nand */
2944 if (!chip
->onfi_set_features
)
2945 chip
->onfi_set_features
= nand_onfi_set_features
;
2946 if (!chip
->onfi_get_features
)
2947 chip
->onfi_get_features
= nand_onfi_get_features
;
2949 /* If called twice, pointers that depend on busw may need to be reset */
2950 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
2951 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2952 if (!chip
->read_word
)
2953 chip
->read_word
= nand_read_word
;
2954 if (!chip
->block_bad
)
2955 chip
->block_bad
= nand_block_bad
;
2956 if (!chip
->block_markbad
)
2957 chip
->block_markbad
= nand_default_block_markbad
;
2958 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
2959 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2960 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
2961 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
2962 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
2963 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2964 if (!chip
->scan_bbt
)
2965 chip
->scan_bbt
= nand_default_bbt
;
2967 if (!chip
->controller
) {
2968 chip
->controller
= &chip
->hwcontrol
;
2969 spin_lock_init(&chip
->controller
->lock
);
2970 init_waitqueue_head(&chip
->controller
->wq
);
2975 /* Sanitize ONFI strings so we can safely print them */
2976 static void sanitize_string(char *s
, size_t len
)
2980 /* Null terminate */
2983 /* Remove non printable chars */
2984 for (i
= 0; i
< len
- 1; i
++) {
2985 if (s
[i
] < ' ' || s
[i
] > 127)
2989 /* Remove trailing spaces */
2993 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2998 for (i
= 0; i
< 8; i
++)
2999 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3005 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3006 /* Parse the Extended Parameter Page. */
3007 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3008 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3010 struct onfi_ext_param_page
*ep
;
3011 struct onfi_ext_section
*s
;
3012 struct onfi_ext_ecc_info
*ecc
;
3018 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3019 ep
= kmalloc(len
, GFP_KERNEL
);
3023 /* Send our own NAND_CMD_PARAM. */
3024 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3026 /* Use the Change Read Column command to skip the ONFI param pages. */
3027 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3028 sizeof(*p
) * p
->num_of_param_pages
, -1);
3030 /* Read out the Extended Parameter Page. */
3031 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3032 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3033 != le16_to_cpu(ep
->crc
))) {
3034 pr_debug("fail in the CRC.\n");
3039 * Check the signature.
3040 * Do not strictly follow the ONFI spec, maybe changed in future.
3042 if (strncmp((char *)ep
->sig
, "EPPS", 4)) {
3043 pr_debug("The signature is invalid.\n");
3047 /* find the ECC section. */
3048 cursor
= (uint8_t *)(ep
+ 1);
3049 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3050 s
= ep
->sections
+ i
;
3051 if (s
->type
== ONFI_SECTION_TYPE_2
)
3053 cursor
+= s
->length
* 16;
3055 if (i
== ONFI_EXT_SECTION_MAX
) {
3056 pr_debug("We can not find the ECC section.\n");
3060 /* get the info we want. */
3061 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3063 if (!ecc
->codeword_size
) {
3064 pr_debug("Invalid codeword size\n");
3068 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3069 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3077 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3079 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3080 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3082 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3087 * Configure chip properties from Micron vendor-specific ONFI table
3089 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3090 struct nand_onfi_params
*p
)
3092 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3094 if (le16_to_cpu(p
->vendor_revision
) < 1)
3097 chip
->read_retries
= micron
->read_retry_options
;
3098 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3102 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3104 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3107 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3111 /* Try ONFI for unknown chip or LP */
3112 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3113 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3114 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3117 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3118 for (i
= 0; i
< 3; i
++) {
3119 for (j
= 0; j
< sizeof(*p
); j
++)
3120 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3121 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3122 le16_to_cpu(p
->crc
)) {
3128 pr_err("Could not find valid ONFI parameter page; aborting\n");
3133 val
= le16_to_cpu(p
->revision
);
3135 chip
->onfi_version
= 23;
3136 else if (val
& (1 << 4))
3137 chip
->onfi_version
= 22;
3138 else if (val
& (1 << 3))
3139 chip
->onfi_version
= 21;
3140 else if (val
& (1 << 2))
3141 chip
->onfi_version
= 20;
3142 else if (val
& (1 << 1))
3143 chip
->onfi_version
= 10;
3145 if (!chip
->onfi_version
) {
3146 pr_info("unsupported ONFI version: %d\n", val
);
3150 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3151 sanitize_string(p
->model
, sizeof(p
->model
));
3153 mtd
->name
= p
->model
;
3155 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3158 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3159 * (don't ask me who thought of this...). MTD assumes that these
3160 * dimensions will be power-of-2, so just truncate the remaining area.
3162 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3163 mtd
->erasesize
*= mtd
->writesize
;
3165 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3167 /* See erasesize comment */
3168 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3169 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3170 chip
->bits_per_cell
= p
->bits_per_cell
;
3172 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3173 *busw
= NAND_BUSWIDTH_16
;
3177 if (p
->ecc_bits
!= 0xff) {
3178 chip
->ecc_strength_ds
= p
->ecc_bits
;
3179 chip
->ecc_step_ds
= 512;
3180 } else if (chip
->onfi_version
>= 21 &&
3181 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3184 * The nand_flash_detect_ext_param_page() uses the
3185 * Change Read Column command which maybe not supported
3186 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3187 * now. We do not replace user supplied command function.
3189 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3190 chip
->cmdfunc
= nand_command_lp
;
3192 /* The Extended Parameter Page is supported since ONFI 2.1. */
3193 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3194 pr_warn("Failed to detect ONFI extended param page\n");
3196 pr_warn("Could not retrieve ONFI ECC requirements\n");
3199 if (p
->jedec_id
== NAND_MFR_MICRON
)
3200 nand_onfi_detect_micron(chip
, p
);
3205 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3213 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3215 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3218 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3219 struct jedec_ecc_info
*ecc
;
3223 /* Try JEDEC for unknown chip or LP */
3224 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3225 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3226 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3227 chip
->read_byte(mtd
) != 'C')
3230 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3231 for (i
= 0; i
< 3; i
++) {
3232 for (j
= 0; j
< sizeof(*p
); j
++)
3233 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3235 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3236 le16_to_cpu(p
->crc
))
3241 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3246 val
= le16_to_cpu(p
->revision
);
3248 chip
->jedec_version
= 10;
3249 else if (val
& (1 << 1))
3250 chip
->jedec_version
= 1; /* vendor specific version */
3252 if (!chip
->jedec_version
) {
3253 pr_info("unsupported JEDEC version: %d\n", val
);
3257 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3258 sanitize_string(p
->model
, sizeof(p
->model
));
3260 mtd
->name
= p
->model
;
3262 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3264 /* Please reference to the comment for nand_flash_detect_onfi. */
3265 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3266 mtd
->erasesize
*= mtd
->writesize
;
3268 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3270 /* Please reference to the comment for nand_flash_detect_onfi. */
3271 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3272 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3273 chip
->bits_per_cell
= p
->bits_per_cell
;
3275 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3276 *busw
= NAND_BUSWIDTH_16
;
3281 ecc
= &p
->ecc_info
[0];
3283 if (ecc
->codeword_size
>= 9) {
3284 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3285 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3287 pr_warn("Invalid codeword size\n");
3294 * nand_id_has_period - Check if an ID string has a given wraparound period
3295 * @id_data: the ID string
3296 * @arrlen: the length of the @id_data array
3297 * @period: the period of repitition
3299 * Check if an ID string is repeated within a given sequence of bytes at
3300 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3301 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3302 * if the repetition has a period of @period; otherwise, returns zero.
3304 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3307 for (i
= 0; i
< period
; i
++)
3308 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3309 if (id_data
[i
] != id_data
[j
])
3315 * nand_id_len - Get the length of an ID string returned by CMD_READID
3316 * @id_data: the ID string
3317 * @arrlen: the length of the @id_data array
3319 * Returns the length of the ID string, according to known wraparound/trailing
3320 * zero patterns. If no pattern exists, returns the length of the array.
3322 static int nand_id_len(u8
*id_data
, int arrlen
)
3324 int last_nonzero
, period
;
3326 /* Find last non-zero byte */
3327 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3328 if (id_data
[last_nonzero
])
3332 if (last_nonzero
< 0)
3335 /* Calculate wraparound period */
3336 for (period
= 1; period
< arrlen
; period
++)
3337 if (nand_id_has_period(id_data
, arrlen
, period
))
3340 /* There's a repeated pattern */
3341 if (period
< arrlen
)
3344 /* There are trailing zeros */
3345 if (last_nonzero
< arrlen
- 1)
3346 return last_nonzero
+ 1;
3348 /* No pattern detected */
3352 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3353 static int nand_get_bits_per_cell(u8 cellinfo
)
3357 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3358 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3363 * Many new NAND share similar device ID codes, which represent the size of the
3364 * chip. The rest of the parameters must be decoded according to generic or
3365 * manufacturer-specific "extended ID" decoding patterns.
3367 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3368 u8 id_data
[8], int *busw
)
3371 /* The 3rd id byte holds MLC / multichip data */
3372 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3373 /* The 4th id byte is the important one */
3376 id_len
= nand_id_len(id_data
, 8);
3379 * Field definitions are in the following datasheets:
3380 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3381 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3382 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3384 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3385 * ID to decide what to do.
3387 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3388 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3390 mtd
->writesize
= 2048 << (extid
& 0x03);
3393 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3413 default: /* Other cases are "reserved" (unknown) */
3414 mtd
->oobsize
= 1024;
3418 /* Calc blocksize */
3419 mtd
->erasesize
= (128 * 1024) <<
3420 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3422 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3423 !nand_is_slc(chip
)) {
3427 mtd
->writesize
= 2048 << (extid
& 0x03);
3430 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3454 /* Calc blocksize */
3455 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3457 mtd
->erasesize
= (128 * 1024) << tmp
;
3458 else if (tmp
== 0x03)
3459 mtd
->erasesize
= 768 * 1024;
3461 mtd
->erasesize
= (64 * 1024) << tmp
;
3465 mtd
->writesize
= 1024 << (extid
& 0x03);
3468 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3469 (mtd
->writesize
>> 9);
3471 /* Calc blocksize. Blocksize is multiples of 64KiB */
3472 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3474 /* Get buswidth information */
3475 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3478 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3479 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3481 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3483 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3485 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3486 nand_is_slc(chip
) &&
3487 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3488 !(id_data
[4] & 0x80) /* !BENAND */) {
3489 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3496 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3497 * decodes a matching ID table entry and assigns the MTD size parameters for
3500 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3501 struct nand_flash_dev
*type
, u8 id_data
[8],
3504 int maf_id
= id_data
[0];
3506 mtd
->erasesize
= type
->erasesize
;
3507 mtd
->writesize
= type
->pagesize
;
3508 mtd
->oobsize
= mtd
->writesize
/ 32;
3509 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3511 /* All legacy ID NAND are small-page, SLC */
3512 chip
->bits_per_cell
= 1;
3515 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3516 * some Spansion chips have erasesize that conflicts with size
3517 * listed in nand_ids table.
3518 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3520 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3521 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3522 && mtd
->writesize
== 512) {
3523 mtd
->erasesize
= 128 * 1024;
3524 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3529 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3530 * heuristic patterns using various detected parameters (e.g., manufacturer,
3531 * page size, cell-type information).
3533 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3534 struct nand_chip
*chip
, u8 id_data
[8])
3536 int maf_id
= id_data
[0];
3538 /* Set the bad block position */
3539 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3540 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3542 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3545 * Bad block marker is stored in the last page of each block on Samsung
3546 * and Hynix MLC devices; stored in first two pages of each block on
3547 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3548 * AMD/Spansion, and Macronix. All others scan only the first page.
3550 if (!nand_is_slc(chip
) &&
3551 (maf_id
== NAND_MFR_SAMSUNG
||
3552 maf_id
== NAND_MFR_HYNIX
))
3553 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3554 else if ((nand_is_slc(chip
) &&
3555 (maf_id
== NAND_MFR_SAMSUNG
||
3556 maf_id
== NAND_MFR_HYNIX
||
3557 maf_id
== NAND_MFR_TOSHIBA
||
3558 maf_id
== NAND_MFR_AMD
||
3559 maf_id
== NAND_MFR_MACRONIX
)) ||
3560 (mtd
->writesize
== 2048 &&
3561 maf_id
== NAND_MFR_MICRON
))
3562 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3565 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3567 return type
->id_len
;
3570 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3571 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3573 if (!strncmp((char *)type
->id
, (char *)id_data
, type
->id_len
)) {
3574 mtd
->writesize
= type
->pagesize
;
3575 mtd
->erasesize
= type
->erasesize
;
3576 mtd
->oobsize
= type
->oobsize
;
3578 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3579 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3580 chip
->options
|= type
->options
;
3581 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3582 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3583 chip
->onfi_timing_mode_default
=
3584 type
->onfi_timing_mode_default
;
3586 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3589 mtd
->name
= type
->name
;
3597 * Get the flash and manufacturer id and lookup if the type is supported.
3599 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3600 struct nand_chip
*chip
,
3601 int *maf_id
, int *dev_id
,
3602 struct nand_flash_dev
*type
)
3608 /* Select the device */
3609 chip
->select_chip(mtd
, 0);
3612 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3615 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3617 /* Send the command for reading device ID */
3618 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3620 /* Read manufacturer and device IDs */
3621 *maf_id
= chip
->read_byte(mtd
);
3622 *dev_id
= chip
->read_byte(mtd
);
3625 * Try again to make sure, as some systems the bus-hold or other
3626 * interface concerns can cause random data which looks like a
3627 * possibly credible NAND flash to appear. If the two results do
3628 * not match, ignore the device completely.
3631 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3633 /* Read entire ID string */
3634 for (i
= 0; i
< 8; i
++)
3635 id_data
[i
] = chip
->read_byte(mtd
);
3637 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3638 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3639 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3640 return ERR_PTR(-ENODEV
);
3644 type
= nand_flash_ids
;
3646 for (; type
->name
!= NULL
; type
++) {
3647 if (is_full_id_nand(type
)) {
3648 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3650 } else if (*dev_id
== type
->dev_id
) {
3655 chip
->onfi_version
= 0;
3656 if (!type
->name
|| !type
->pagesize
) {
3657 /* Check if the chip is ONFI compliant */
3658 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3661 /* Check if the chip is JEDEC compliant */
3662 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3667 return ERR_PTR(-ENODEV
);
3670 mtd
->name
= type
->name
;
3672 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3674 if (!type
->pagesize
) {
3675 /* Decode parameters from extended ID */
3676 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3678 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3680 /* Get chip options */
3681 chip
->options
|= type
->options
;
3684 * Check if chip is not a Samsung device. Do not clear the
3685 * options for chips which do not have an extended id.
3687 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3688 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3691 /* Try to identify manufacturer */
3692 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3693 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3697 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3698 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3699 chip
->options
|= busw
;
3700 nand_set_defaults(chip
, busw
);
3701 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3703 * Check, if buswidth is correct. Hardware drivers should set
3706 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3708 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3709 pr_warn("bus width %d instead %d bit\n",
3710 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3712 return ERR_PTR(-EINVAL
);
3715 nand_decode_bbm_options(mtd
, chip
, id_data
);
3717 /* Calculate the address shift from the page size */
3718 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3719 /* Convert chipsize to number of pages per chip -1 */
3720 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3722 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3723 ffs(mtd
->erasesize
) - 1;
3724 if (chip
->chipsize
& 0xffffffff)
3725 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3727 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3728 chip
->chip_shift
+= 32 - 1;
3731 chip
->badblockbits
= 8;
3732 chip
->erase
= single_erase
;
3734 /* Do not replace user supplied command function! */
3735 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3736 chip
->cmdfunc
= nand_command_lp
;
3738 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3741 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3742 if (chip
->onfi_version
)
3743 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3744 chip
->onfi_params
.model
);
3745 else if (chip
->jedec_version
)
3746 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3747 chip
->jedec_params
.model
);
3749 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3752 if (chip
->jedec_version
)
3753 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3754 chip
->jedec_params
.model
);
3756 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3759 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3763 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3764 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3765 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3769 #if CONFIG_IS_ENABLED(OF_CONTROL)
3770 DECLARE_GLOBAL_DATA_PTR
;
3772 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3774 int ret
, ecc_mode
= -1, ecc_strength
, ecc_step
;
3775 const void *blob
= gd
->fdt_blob
;
3778 ret
= fdtdec_get_int(blob
, node
, "nand-bus-width", -1);
3780 chip
->options
|= NAND_BUSWIDTH_16
;
3782 if (fdtdec_get_bool(blob
, node
, "nand-on-flash-bbt"))
3783 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3785 str
= fdt_getprop(blob
, node
, "nand-ecc-mode", NULL
);
3787 if (!strcmp(str
, "none"))
3788 ecc_mode
= NAND_ECC_NONE
;
3789 else if (!strcmp(str
, "soft"))
3790 ecc_mode
= NAND_ECC_SOFT
;
3791 else if (!strcmp(str
, "hw"))
3792 ecc_mode
= NAND_ECC_HW
;
3793 else if (!strcmp(str
, "hw_syndrome"))
3794 ecc_mode
= NAND_ECC_HW_SYNDROME
;
3795 else if (!strcmp(str
, "hw_oob_first"))
3796 ecc_mode
= NAND_ECC_HW_OOB_FIRST
;
3797 else if (!strcmp(str
, "soft_bch"))
3798 ecc_mode
= NAND_ECC_SOFT_BCH
;
3802 ecc_strength
= fdtdec_get_int(blob
, node
, "nand-ecc-strength", -1);
3803 ecc_step
= fdtdec_get_int(blob
, node
, "nand-ecc-step-size", -1);
3805 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3806 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3807 pr_err("must set both strength and step size in DT\n");
3812 chip
->ecc
.mode
= ecc_mode
;
3814 if (ecc_strength
>= 0)
3815 chip
->ecc
.strength
= ecc_strength
;
3818 chip
->ecc
.size
= ecc_step
;
3823 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3827 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
3830 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3831 * @mtd: MTD device structure
3832 * @maxchips: number of chips to scan for
3833 * @table: alternative NAND ID table
3835 * This is the first phase of the normal nand_scan() function. It reads the
3836 * flash ID and sets up MTD fields accordingly.
3839 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3840 struct nand_flash_dev
*table
)
3842 int i
, nand_maf_id
, nand_dev_id
;
3843 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3844 struct nand_flash_dev
*type
;
3847 if (chip
->flash_node
) {
3848 ret
= nand_dt_init(mtd
, chip
, chip
->flash_node
);
3853 /* Set the default functions */
3854 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
3856 /* Read the flash type */
3857 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
3858 &nand_dev_id
, table
);
3861 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3862 pr_warn("No NAND device found\n");
3863 chip
->select_chip(mtd
, -1);
3864 return PTR_ERR(type
);
3867 chip
->select_chip(mtd
, -1);
3869 /* Check for a chip array */
3870 for (i
= 1; i
< maxchips
; i
++) {
3871 chip
->select_chip(mtd
, i
);
3872 /* See comment in nand_get_flash_type for reset */
3873 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3874 /* Send the command for reading device ID */
3875 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3876 /* Read manufacturer and device IDs */
3877 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3878 nand_dev_id
!= chip
->read_byte(mtd
)) {
3879 chip
->select_chip(mtd
, -1);
3882 chip
->select_chip(mtd
, -1);
3887 pr_info("%d chips detected\n", i
);
3890 /* Store the number of chips and calc total size for mtd */
3892 mtd
->size
= i
* chip
->chipsize
;
3896 EXPORT_SYMBOL(nand_scan_ident
);
3899 * Check if the chip configuration meet the datasheet requirements.
3901 * If our configuration corrects A bits per B bytes and the minimum
3902 * required correction level is X bits per Y bytes, then we must ensure
3903 * both of the following are true:
3905 * (1) A / B >= X / Y
3908 * Requirement (1) ensures we can correct for the required bitflip density.
3909 * Requirement (2) ensures we can correct even when all bitflips are clumped
3910 * in the same sector.
3912 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
3914 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3915 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
3918 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
3919 /* Not enough information */
3923 * We get the number of corrected bits per page to compare
3924 * the correction density.
3926 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
3927 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
3929 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
3933 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3934 * @mtd: MTD device structure
3936 * This is the second phase of the normal nand_scan() function. It fills out
3937 * all the uninitialized function pointers with the defaults and scans for a
3938 * bad block table if appropriate.
3940 int nand_scan_tail(struct mtd_info
*mtd
)
3943 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3944 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
3945 struct nand_buffers
*nbuf
;
3947 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3948 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
3949 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
3951 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
3952 nbuf
= kzalloc(sizeof(struct nand_buffers
), GFP_KERNEL
);
3953 chip
->buffers
= nbuf
;
3959 /* Set the internal oob buffer location, just after the page data */
3960 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3963 * If no default placement scheme is given, select an appropriate one.
3965 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
3966 switch (mtd
->oobsize
) {
3968 ecc
->layout
= &nand_oob_8
;
3971 ecc
->layout
= &nand_oob_16
;
3974 ecc
->layout
= &nand_oob_64
;
3977 ecc
->layout
= &nand_oob_128
;
3980 pr_warn("No oob scheme defined for oobsize %d\n",
3986 if (!chip
->write_page
)
3987 chip
->write_page
= nand_write_page
;
3990 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3991 * selected and we have 256 byte pagesize fallback to software ECC
3994 switch (ecc
->mode
) {
3995 case NAND_ECC_HW_OOB_FIRST
:
3996 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3997 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
3998 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4001 if (!ecc
->read_page
)
4002 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4005 /* Use standard hwecc read page function? */
4006 if (!ecc
->read_page
)
4007 ecc
->read_page
= nand_read_page_hwecc
;
4008 if (!ecc
->write_page
)
4009 ecc
->write_page
= nand_write_page_hwecc
;
4010 if (!ecc
->read_page_raw
)
4011 ecc
->read_page_raw
= nand_read_page_raw
;
4012 if (!ecc
->write_page_raw
)
4013 ecc
->write_page_raw
= nand_write_page_raw
;
4015 ecc
->read_oob
= nand_read_oob_std
;
4016 if (!ecc
->write_oob
)
4017 ecc
->write_oob
= nand_write_oob_std
;
4018 if (!ecc
->read_subpage
)
4019 ecc
->read_subpage
= nand_read_subpage
;
4020 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4021 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4023 case NAND_ECC_HW_SYNDROME
:
4024 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4026 ecc
->read_page
== nand_read_page_hwecc
||
4028 ecc
->write_page
== nand_write_page_hwecc
)) {
4029 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4032 /* Use standard syndrome read/write page function? */
4033 if (!ecc
->read_page
)
4034 ecc
->read_page
= nand_read_page_syndrome
;
4035 if (!ecc
->write_page
)
4036 ecc
->write_page
= nand_write_page_syndrome
;
4037 if (!ecc
->read_page_raw
)
4038 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4039 if (!ecc
->write_page_raw
)
4040 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4042 ecc
->read_oob
= nand_read_oob_syndrome
;
4043 if (!ecc
->write_oob
)
4044 ecc
->write_oob
= nand_write_oob_syndrome
;
4046 if (mtd
->writesize
>= ecc
->size
) {
4047 if (!ecc
->strength
) {
4048 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4053 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4054 ecc
->size
, mtd
->writesize
);
4055 ecc
->mode
= NAND_ECC_SOFT
;
4058 ecc
->calculate
= nand_calculate_ecc
;
4059 ecc
->correct
= nand_correct_data
;
4060 ecc
->read_page
= nand_read_page_swecc
;
4061 ecc
->read_subpage
= nand_read_subpage
;
4062 ecc
->write_page
= nand_write_page_swecc
;
4063 ecc
->read_page_raw
= nand_read_page_raw
;
4064 ecc
->write_page_raw
= nand_write_page_raw
;
4065 ecc
->read_oob
= nand_read_oob_std
;
4066 ecc
->write_oob
= nand_write_oob_std
;
4073 case NAND_ECC_SOFT_BCH
:
4074 if (!mtd_nand_has_bch()) {
4075 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4078 ecc
->calculate
= nand_bch_calculate_ecc
;
4079 ecc
->correct
= nand_bch_correct_data
;
4080 ecc
->read_page
= nand_read_page_swecc
;
4081 ecc
->read_subpage
= nand_read_subpage
;
4082 ecc
->write_page
= nand_write_page_swecc
;
4083 ecc
->read_page_raw
= nand_read_page_raw
;
4084 ecc
->write_page_raw
= nand_write_page_raw
;
4085 ecc
->read_oob
= nand_read_oob_std
;
4086 ecc
->write_oob
= nand_write_oob_std
;
4088 * Board driver should supply ecc.size and ecc.strength values
4089 * to select how many bits are correctable. Otherwise, default
4090 * to 4 bits for large page devices.
4092 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4097 /* See nand_bch_init() for details. */
4099 ecc
->priv
= nand_bch_init(mtd
);
4101 pr_warn("BCH ECC initialization failed!\n");
4107 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4108 ecc
->read_page
= nand_read_page_raw
;
4109 ecc
->write_page
= nand_write_page_raw
;
4110 ecc
->read_oob
= nand_read_oob_std
;
4111 ecc
->read_page_raw
= nand_read_page_raw
;
4112 ecc
->write_page_raw
= nand_write_page_raw
;
4113 ecc
->write_oob
= nand_write_oob_std
;
4114 ecc
->size
= mtd
->writesize
;
4120 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4124 /* For many systems, the standard OOB write also works for raw */
4125 if (!ecc
->read_oob_raw
)
4126 ecc
->read_oob_raw
= ecc
->read_oob
;
4127 if (!ecc
->write_oob_raw
)
4128 ecc
->write_oob_raw
= ecc
->write_oob
;
4131 * The number of bytes available for a client to place data into
4132 * the out of band area.
4136 for (i
= 0; ecc
->layout
->oobfree
[i
].length
; i
++)
4137 mtd
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4140 /* ECC sanity check: warn if it's too weak */
4141 if (!nand_ecc_strength_good(mtd
))
4142 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4146 * Set the number of read / write steps for one page depending on ECC
4149 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4150 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4151 pr_warn("Invalid ECC parameters\n");
4154 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4156 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4157 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4158 switch (ecc
->steps
) {
4160 mtd
->subpage_sft
= 1;
4165 mtd
->subpage_sft
= 2;
4169 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4171 /* Initialize state */
4172 chip
->state
= FL_READY
;
4174 /* Invalidate the pagebuffer reference */
4177 /* Large page NAND with SOFT_ECC should support subpage reads */
4178 switch (ecc
->mode
) {
4180 case NAND_ECC_SOFT_BCH
:
4181 if (chip
->page_shift
> 9)
4182 chip
->options
|= NAND_SUBPAGE_READ
;
4189 /* Fill in remaining MTD driver data */
4190 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4191 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4193 mtd
->_erase
= nand_erase
;
4194 mtd
->_read
= nand_read
;
4195 mtd
->_write
= nand_write
;
4196 mtd
->_panic_write
= panic_nand_write
;
4197 mtd
->_read_oob
= nand_read_oob
;
4198 mtd
->_write_oob
= nand_write_oob
;
4199 mtd
->_sync
= nand_sync
;
4201 mtd
->_unlock
= NULL
;
4202 mtd
->_block_isreserved
= nand_block_isreserved
;
4203 mtd
->_block_isbad
= nand_block_isbad
;
4204 mtd
->_block_markbad
= nand_block_markbad
;
4205 mtd
->writebufsize
= mtd
->writesize
;
4207 /* propagate ecc info to mtd_info */
4208 mtd
->ecclayout
= ecc
->layout
;
4209 mtd
->ecc_strength
= ecc
->strength
;
4210 mtd
->ecc_step_size
= ecc
->size
;
4212 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4213 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4216 if (!mtd
->bitflip_threshold
)
4217 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4221 EXPORT_SYMBOL(nand_scan_tail
);
4224 * nand_scan - [NAND Interface] Scan for the NAND device
4225 * @mtd: MTD device structure
4226 * @maxchips: number of chips to scan for
4228 * This fills out all the uninitialized function pointers with the defaults.
4229 * The flash ID is read and the mtd/chip structures are filled with the
4230 * appropriate values.
4232 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4236 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4238 ret
= nand_scan_tail(mtd
);
4241 EXPORT_SYMBOL(nand_scan
);
4243 MODULE_LICENSE("GPL");
4244 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4245 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4246 MODULE_DESCRIPTION("Generic NAND flash driver code");