drivers/mtd/nand/ndfc.c

   1 /*
   2  * Overview:
   3  *   Platform independend driver for NDFC (NanD Flash Controller)
   4  *   integrated into IBM/AMCC PPC4xx cores
   5  *
   6  * (C) Copyright 2006-2009
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * Based on original work by
  10  *      Thomas Gleixner
  11  *      Copyright 2006 IBM
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33
  34 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
  35     defined(CONFIG_NAND_NDFC)
  36
  37 #include <nand.h>
  38 #include <linux/mtd/ndfc.h>
  39 #include <linux/mtd/nand_ecc.h>
  40 #include <asm/processor.h>
  41 #include <asm/io.h>
  42 #include <ppc4xx.h>
  43
  44 /*
  45  * We need to store the info, which chip-select (CS) is used for the
  46  * chip number. For example on Sequoia NAND chip #0 uses
  47  * CS #3.
  48  */
  49 static int ndfc_cs[NDFC_MAX_BANKS];
  50
  51 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  52 {
  53         struct nand_chip *this = mtd->priv;
  54         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  55
  56         if (cmd == NAND_CMD_NONE)
  57                 return;
  58
  59         if (ctrl & NAND_CLE)
  60                 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
  61         else
  62                 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
  63 }
  64
  65 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  66 {
  67         struct nand_chip *this = mtdinfo->priv;
  68         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  69
  70         return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
  71 }
  72
  73 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
  74 {
  75         struct nand_chip *this = mtdinfo->priv;
  76         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  77         u32 ccr;
  78
  79         ccr = in_be32((u32 *)(base + NDFC_CCR));
  80         ccr |= NDFC_CCR_RESET_ECC;
  81         out_be32((u32 *)(base + NDFC_CCR), ccr);
  82 }
  83
  84 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
  85                               const u_char *dat, u_char *ecc_code)
  86 {
  87         struct nand_chip *this = mtdinfo->priv;
  88         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  89         u32 ecc;
  90         u8 *p = (u8 *)&ecc;
  91
  92         ecc = in_be32((u32 *)(base + NDFC_ECC));
  93
  94         /* The NDFC uses Smart Media (SMC) bytes order
  95          */
  96         ecc_code[0] = p[2];
  97         ecc_code[1] = p[1];
  98         ecc_code[2] = p[3];
  99
 100         return 0;
 101 }
 102
 103 /*
 104  * Speedups for buffer read/write/verify
 105  *
 106  * NDFC allows 32bit read/write of data. So we can speed up the buffer
 107  * functions. No further checking, as nand_base will always read/write
 108  * page aligned.
 109  */
 110 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 111 {
 112         struct nand_chip *this = mtdinfo->priv;
 113         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 114         uint32_t *p = (uint32_t *) buf;
 115
 116         for (;len > 0; len -= 4)
 117                 *p++ = in_be32((u32 *)(base + NDFC_DATA));
 118 }
 119
 120 #ifndef CONFIG_NAND_SPL
 121 /*
 122  * Don't use these speedup functions in NAND boot image, since the image
 123  * has to fit into 4kByte.
 124  */
 125 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 126 {
 127         struct nand_chip *this = mtdinfo->priv;
 128         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 129         uint32_t *p = (uint32_t *) buf;
 130
 131         for (; len > 0; len -= 4)
 132                 out_be32((u32 *)(base + NDFC_DATA), *p++);
 133 }
 134
 135 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 136 {
 137         struct nand_chip *this = mtdinfo->priv;
 138         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 139         uint32_t *p = (uint32_t *) buf;
 140
 141         for (; len > 0; len -= 4)
 142                 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
 143                         return -1;
 144
 145         return 0;
 146 }
 147 #endif /* #ifndef CONFIG_NAND_SPL */
 148
 149 #ifndef CONFIG_SYS_NAND_BCR
 150 #define CONFIG_SYS_NAND_BCR 0x80002222
 151 #endif
 152
 153 void board_nand_select_device(struct nand_chip *nand, int chip)
 154 {
 155         /*
 156          * Don't use "chip" to address the NAND device,
 157          * generate the cs from the address where it is encoded.
 158          */
 159         ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
 160         int cs = ndfc_cs[chip];
 161
 162         /* Set NandFlash Core Configuration Register */
 163         /* 1 col x 2 rows */
 164         out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
 165         out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
 166 }
 167
 168 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
 169 {
 170         /*
 171          * Nothing to do here!
 172          */
 173 }
 174
 175 int board_nand_init(struct nand_chip *nand)
 176 {
 177         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 178         ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
 179         static int chip = 0;
 180
 181         /*
 182          * Save chip-select for this chip #
 183          */
 184         ndfc_cs[chip] = cs;
 185
 186         /*
 187          * Select required NAND chip in NDFC
 188          */
 189         board_nand_select_device(nand, chip);
 190
 191         nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
 192         nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
 193         nand->cmd_ctrl = ndfc_hwcontrol;
 194         nand->chip_delay = 50;
 195         nand->read_buf = ndfc_read_buf;
 196         nand->dev_ready = ndfc_dev_ready;
 197         nand->ecc.correct = nand_correct_data;
 198         nand->ecc.hwctl = ndfc_enable_hwecc;
 199         nand->ecc.calculate = ndfc_calculate_ecc;
 200         nand->ecc.mode = NAND_ECC_HW;
 201         nand->ecc.size = 256;
 202         nand->ecc.bytes = 3;
 203         nand->select_chip = ndfc_select_chip;
 204
 205 #ifndef CONFIG_NAND_SPL
 206         nand->write_buf  = ndfc_write_buf;
 207         nand->verify_buf = ndfc_verify_buf;
 208 #else
 209         /*
 210          * Setup EBC (CS0 only right now)
 211          */
 212         mtebc(EBC0_CFG, 0xb8400000);
 213
 214         mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
 215         mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
 216 #endif
 217
 218         chip++;
 219
 220         return 0;
 221 }
 222
 223 #endif