2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
9 * ----------------------------------------------------------------------------
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
15 * Copyright (C) 2005 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
31 #include <linux/compiler.h>
32 #include <asm/arch/emac_defs.h>
34 #include "davinci_emac.h"
36 unsigned int emac_dbg
= 0;
37 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
39 #ifdef EMAC_HW_RAM_ADDR
40 static inline unsigned long BD_TO_HW(unsigned long x
)
45 return x
- EMAC_WRAPPER_RAM_ADDR
+ EMAC_HW_RAM_ADDR
;
48 static inline unsigned long HW_TO_BD(unsigned long x
)
53 return x
- EMAC_HW_RAM_ADDR
+ EMAC_WRAPPER_RAM_ADDR
;
56 #define BD_TO_HW(x) (x)
57 #define HW_TO_BD(x) (x)
60 #ifdef DAVINCI_EMAC_GIG_ENABLE
61 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
63 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
66 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
67 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
68 EMAC_MDIO_CLOCK_FREQ) - 1)
71 static void davinci_eth_mdio_enable(void);
73 static int gen_init_phy(int phy_addr
);
74 static int gen_is_phy_connected(int phy_addr
);
75 static int gen_get_link_speed(int phy_addr
);
76 static int gen_auto_negotiate(int phy_addr
);
78 void eth_mdio_enable(void)
80 davinci_eth_mdio_enable();
84 static volatile emac_regs
*adap_emac
= (emac_regs
*)EMAC_BASE_ADDR
;
85 static volatile ewrap_regs
*adap_ewrap
= (ewrap_regs
*)EMAC_WRAPPER_BASE_ADDR
;
86 static volatile mdio_regs
*adap_mdio
= (mdio_regs
*)EMAC_MDIO_BASE_ADDR
;
88 /* EMAC descriptors */
89 static volatile emac_desc
*emac_rx_desc
= (emac_desc
*)(EMAC_WRAPPER_RAM_ADDR
+ EMAC_RX_DESC_BASE
);
90 static volatile emac_desc
*emac_tx_desc
= (emac_desc
*)(EMAC_WRAPPER_RAM_ADDR
+ EMAC_TX_DESC_BASE
);
91 static volatile emac_desc
*emac_rx_active_head
= 0;
92 static volatile emac_desc
*emac_rx_active_tail
= 0;
93 static int emac_rx_queue_active
= 0;
95 /* Receive packet buffers */
96 static unsigned char emac_rx_buffers
[EMAC_MAX_RX_BUFFERS
* EMAC_RXBUF_SIZE
]
97 __aligned(ARCH_DMA_MINALIGN
);
99 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
100 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
103 /* PHY address for a discovered PHY (0xff - not found) */
104 static u_int8_t active_phy_addr
[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
];
106 /* number of PHY found active */
107 static u_int8_t num_phy
;
109 phy_t phy
[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
];
111 static inline void davinci_flush_rx_descs(void)
113 /* flush the whole RX descs area */
114 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR
+ EMAC_RX_DESC_BASE
,
115 EMAC_WRAPPER_RAM_ADDR
+ EMAC_TX_DESC_BASE
);
118 static inline void davinci_invalidate_rx_descs(void)
120 /* invalidate the whole RX descs area */
121 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR
+ EMAC_RX_DESC_BASE
,
122 EMAC_WRAPPER_RAM_ADDR
+ EMAC_TX_DESC_BASE
);
125 static inline void davinci_flush_desc(emac_desc
*desc
)
127 flush_dcache_range((unsigned long)desc
,
128 (unsigned long)desc
+ sizeof(*desc
));
131 static int davinci_eth_set_mac_addr(struct eth_device
*dev
)
133 unsigned long mac_hi
;
134 unsigned long mac_lo
;
137 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
139 * Using channel 0 only - other channels are disabled
141 writel(0, &adap_emac
->MACINDEX
);
142 mac_hi
= (dev
->enetaddr
[3] << 24) |
143 (dev
->enetaddr
[2] << 16) |
144 (dev
->enetaddr
[1] << 8) |
146 mac_lo
= (dev
->enetaddr
[5] << 8) |
149 writel(mac_hi
, &adap_emac
->MACADDRHI
);
150 #if defined(DAVINCI_EMAC_VERSION2)
151 writel(mac_lo
| EMAC_MAC_ADDR_IS_VALID
| EMAC_MAC_ADDR_MATCH
,
152 &adap_emac
->MACADDRLO
);
154 writel(mac_lo
, &adap_emac
->MACADDRLO
);
157 writel(0, &adap_emac
->MACHASH1
);
158 writel(0, &adap_emac
->MACHASH2
);
160 /* Set source MAC address - REQUIRED */
161 writel(mac_hi
, &adap_emac
->MACSRCADDRHI
);
162 writel(mac_lo
, &adap_emac
->MACSRCADDRLO
);
168 static void davinci_eth_mdio_enable(void)
172 clkdiv
= CONFIG_SYS_EMAC_TI_CLKDIV
;
174 writel((clkdiv
& 0xff) |
175 MDIO_CONTROL_ENABLE
|
177 MDIO_CONTROL_FAULT_ENABLE
,
178 &adap_mdio
->CONTROL
);
180 while (readl(&adap_mdio
->CONTROL
) & MDIO_CONTROL_IDLE
)
185 * Tries to find an active connected PHY. Returns 1 if address if found.
186 * If no active PHY (or more than one PHY) found returns 0.
187 * Sets active_phy_addr variable.
189 static int davinci_eth_phy_detect(void)
191 u_int32_t phy_act_state
;
194 unsigned int count
= 0;
196 for (i
= 0; i
< CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
; i
++)
197 active_phy_addr
[i
] = 0xff;
200 phy_act_state
= readl(&adap_mdio
->ALIVE
);
202 if (phy_act_state
== 0)
203 return 0; /* No active PHYs */
205 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state
);
207 for (i
= 0, j
= 0; i
< 32; i
++)
208 if (phy_act_state
& (1 << i
)) {
210 if (count
<= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
) {
211 active_phy_addr
[j
++] = i
;
213 printf("%s: to many PHYs detected.\n",
226 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
227 int davinci_eth_phy_read(u_int8_t phy_addr
, u_int8_t reg_num
, u_int16_t
*data
)
231 while (readl(&adap_mdio
->USERACCESS0
) & MDIO_USERACCESS0_GO
)
234 writel(MDIO_USERACCESS0_GO
|
235 MDIO_USERACCESS0_WRITE_READ
|
236 ((reg_num
& 0x1f) << 21) |
237 ((phy_addr
& 0x1f) << 16),
238 &adap_mdio
->USERACCESS0
);
240 /* Wait for command to complete */
241 while ((tmp
= readl(&adap_mdio
->USERACCESS0
)) & MDIO_USERACCESS0_GO
)
244 if (tmp
& MDIO_USERACCESS0_ACK
) {
245 *data
= tmp
& 0xffff;
253 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
254 int davinci_eth_phy_write(u_int8_t phy_addr
, u_int8_t reg_num
, u_int16_t data
)
257 while (readl(&adap_mdio
->USERACCESS0
) & MDIO_USERACCESS0_GO
)
260 writel(MDIO_USERACCESS0_GO
|
261 MDIO_USERACCESS0_WRITE_WRITE
|
262 ((reg_num
& 0x1f) << 21) |
263 ((phy_addr
& 0x1f) << 16) |
265 &adap_mdio
->USERACCESS0
);
267 /* Wait for command to complete */
268 while (readl(&adap_mdio
->USERACCESS0
) & MDIO_USERACCESS0_GO
)
274 /* PHY functions for a generic PHY */
275 static int gen_init_phy(int phy_addr
)
279 if (gen_get_link_speed(phy_addr
)) {
280 /* Try another time */
281 ret
= gen_get_link_speed(phy_addr
);
287 static int gen_is_phy_connected(int phy_addr
)
291 return davinci_eth_phy_read(phy_addr
, MII_PHYSID1
, &dummy
);
294 static int get_active_phy(void)
298 for (i
= 0; i
< num_phy
; i
++)
299 if (phy
[i
].get_link_speed(active_phy_addr
[i
]))
302 return -1; /* Return error if no link */
305 static int gen_get_link_speed(int phy_addr
)
309 if (davinci_eth_phy_read(phy_addr
, MII_STATUS_REG
, &tmp
) &&
311 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
312 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
313 davinci_eth_phy_read(phy_addr
, MII_LPA
, &tmp
);
315 /* Speed doesn't matter, there is no setting for it in EMAC. */
316 if (tmp
& (LPA_100FULL
| LPA_10FULL
)) {
317 /* set EMAC for Full Duplex */
318 writel(EMAC_MACCONTROL_MIIEN_ENABLE
|
319 EMAC_MACCONTROL_FULLDUPLEX_ENABLE
,
320 &adap_emac
->MACCONTROL
);
322 /*set EMAC for Half Duplex */
323 writel(EMAC_MACCONTROL_MIIEN_ENABLE
,
324 &adap_emac
->MACCONTROL
);
327 if (tmp
& (LPA_100FULL
| LPA_100HALF
))
328 writel(readl(&adap_emac
->MACCONTROL
) |
329 EMAC_MACCONTROL_RMIISPEED_100
,
330 &adap_emac
->MACCONTROL
);
332 writel(readl(&adap_emac
->MACCONTROL
) &
333 ~EMAC_MACCONTROL_RMIISPEED_100
,
334 &adap_emac
->MACCONTROL
);
342 static int gen_auto_negotiate(int phy_addr
)
346 unsigned long cntr
= 0;
348 if (!davinci_eth_phy_read(phy_addr
, MII_BMCR
, &tmp
))
351 val
= tmp
| BMCR_FULLDPLX
| BMCR_ANENABLE
|
353 davinci_eth_phy_write(phy_addr
, MII_BMCR
, val
);
355 if (!davinci_eth_phy_read(phy_addr
, MII_ADVERTISE
, &val
))
358 val
|= (ADVERTISE_100FULL
| ADVERTISE_100HALF
| ADVERTISE_10FULL
|
360 davinci_eth_phy_write(phy_addr
, MII_ADVERTISE
, val
);
362 if (!davinci_eth_phy_read(phy_addr
, MII_BMCR
, &tmp
))
365 /* Restart Auto_negotiation */
366 tmp
|= BMCR_ANRESTART
;
367 davinci_eth_phy_write(phy_addr
, MII_BMCR
, tmp
);
369 /*check AutoNegotiate complete */
372 if (!davinci_eth_phy_read(phy_addr
, MII_BMSR
, &tmp
))
375 if (tmp
& BMSR_ANEGCOMPLETE
)
379 } while (cntr
< 200);
381 if (!davinci_eth_phy_read(phy_addr
, MII_BMSR
, &tmp
))
384 if (!(tmp
& BMSR_ANEGCOMPLETE
))
387 return(gen_get_link_speed(phy_addr
));
389 /* End of generic PHY functions */
392 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
393 static int davinci_mii_phy_read(const char *devname
, unsigned char addr
, unsigned char reg
, unsigned short *value
)
395 return(davinci_eth_phy_read(addr
, reg
, value
) ? 0 : 1);
398 static int davinci_mii_phy_write(const char *devname
, unsigned char addr
, unsigned char reg
, unsigned short value
)
400 return(davinci_eth_phy_write(addr
, reg
, value
) ? 0 : 1);
404 static void __attribute__((unused
)) davinci_eth_gigabit_enable(int phy_addr
)
408 if (davinci_eth_phy_read(phy_addr
, 0, &data
)) {
409 if (data
& (1 << 6)) { /* speed selection MSB */
411 * Check if link detected is giga-bit
412 * If Gigabit mode detected, enable gigbit in MAC
414 writel(readl(&adap_emac
->MACCONTROL
) |
415 EMAC_MACCONTROL_GIGFORCE
|
416 EMAC_MACCONTROL_GIGABIT_ENABLE
,
417 &adap_emac
->MACCONTROL
);
422 /* Eth device open */
423 static int davinci_eth_open(struct eth_device
*dev
, bd_t
*bis
)
426 u_int32_t clkdiv
, cnt
;
427 volatile emac_desc
*rx_desc
;
430 debug_emac("+ emac_open\n");
432 /* Reset EMAC module and disable interrupts in wrapper */
433 writel(1, &adap_emac
->SOFTRESET
);
434 while (readl(&adap_emac
->SOFTRESET
) != 0)
436 #if defined(DAVINCI_EMAC_VERSION2)
437 writel(1, &adap_ewrap
->softrst
);
438 while (readl(&adap_ewrap
->softrst
) != 0)
441 writel(0, &adap_ewrap
->EWCTL
);
442 for (cnt
= 0; cnt
< 5; cnt
++) {
443 clkdiv
= readl(&adap_ewrap
->EWCTL
);
447 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
448 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
449 adap_ewrap
->c0rxen
= adap_ewrap
->c1rxen
= adap_ewrap
->c2rxen
= 0;
450 adap_ewrap
->c0txen
= adap_ewrap
->c1txen
= adap_ewrap
->c2txen
= 0;
451 adap_ewrap
->c0miscen
= adap_ewrap
->c1miscen
= adap_ewrap
->c2miscen
= 0;
453 rx_desc
= emac_rx_desc
;
455 writel(1, &adap_emac
->TXCONTROL
);
456 writel(1, &adap_emac
->RXCONTROL
);
458 davinci_eth_set_mac_addr(dev
);
460 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
461 addr
= &adap_emac
->TX0HDP
;
462 for(cnt
= 0; cnt
< 16; cnt
++)
465 addr
= &adap_emac
->RX0HDP
;
466 for(cnt
= 0; cnt
< 16; cnt
++)
469 /* Clear Statistics (do this before setting MacControl register) */
470 addr
= &adap_emac
->RXGOODFRAMES
;
471 for(cnt
= 0; cnt
< EMAC_NUM_STATS
; cnt
++)
474 /* No multicast addressing */
475 writel(0, &adap_emac
->MACHASH1
);
476 writel(0, &adap_emac
->MACHASH2
);
478 /* Create RX queue and set receive process in place */
479 emac_rx_active_head
= emac_rx_desc
;
480 for (cnt
= 0; cnt
< EMAC_MAX_RX_BUFFERS
; cnt
++) {
481 rx_desc
->next
= BD_TO_HW((u_int32_t
)(rx_desc
+ 1));
482 rx_desc
->buffer
= &emac_rx_buffers
[cnt
* EMAC_RXBUF_SIZE
];
483 rx_desc
->buff_off_len
= EMAC_MAX_ETHERNET_PKT_SIZE
;
484 rx_desc
->pkt_flag_len
= EMAC_CPPI_OWNERSHIP_BIT
;
488 /* Finalize the rx desc list */
491 emac_rx_active_tail
= rx_desc
;
492 emac_rx_queue_active
= 1;
494 davinci_flush_rx_descs();
497 writel(EMAC_MAX_ETHERNET_PKT_SIZE
, &adap_emac
->RXMAXLEN
);
498 writel(0, &adap_emac
->RXBUFFEROFFSET
);
501 * No fancy configs - Use this for promiscous debug
502 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
504 writel(EMAC_RXMBPENABLE_RXBROADEN
, &adap_emac
->RXMBPENABLE
);
506 /* Enable ch 0 only */
507 writel(1, &adap_emac
->RXUNICASTSET
);
509 /* Enable MII interface and Full duplex mode */
510 #if defined(CONFIG_SOC_DA8XX) || \
511 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
512 writel((EMAC_MACCONTROL_MIIEN_ENABLE
|
513 EMAC_MACCONTROL_FULLDUPLEX_ENABLE
|
514 EMAC_MACCONTROL_RMIISPEED_100
),
515 &adap_emac
->MACCONTROL
);
517 writel((EMAC_MACCONTROL_MIIEN_ENABLE
|
518 EMAC_MACCONTROL_FULLDUPLEX_ENABLE
),
519 &adap_emac
->MACCONTROL
);
522 /* Init MDIO & get link state */
523 clkdiv
= CONFIG_SYS_EMAC_TI_CLKDIV
;
524 writel((clkdiv
& 0xff) | MDIO_CONTROL_ENABLE
| MDIO_CONTROL_FAULT
,
525 &adap_mdio
->CONTROL
);
527 /* We need to wait for MDIO to start */
530 index
= get_active_phy();
534 emac_gigabit_enable(active_phy_addr
[index
]);
536 /* Start receive process */
537 writel(BD_TO_HW((u_int32_t
)emac_rx_desc
), &adap_emac
->RX0HDP
);
539 debug_emac("- emac_open\n");
544 /* EMAC Channel Teardown */
545 static void davinci_eth_ch_teardown(int ch
)
550 debug_emac("+ emac_ch_teardown\n");
552 if (ch
== EMAC_CH_TX
) {
553 /* Init TX channel teardown */
554 writel(0, &adap_emac
->TXTEARDOWN
);
557 * Wait here for Tx teardown completion interrupt to
558 * occur. Note: A task delay can be called here to pend
559 * rather than occupying CPU cycles - anyway it has
560 * been found that teardown takes very few cpu cycles
561 * and does not affect functionality
567 cnt
= readl(&adap_emac
->TX0CP
);
568 } while (cnt
!= 0xfffffffc);
569 writel(cnt
, &adap_emac
->TX0CP
);
570 writel(0, &adap_emac
->TX0HDP
);
572 /* Init RX channel teardown */
573 writel(0, &adap_emac
->RXTEARDOWN
);
576 * Wait here for Rx teardown completion interrupt to
577 * occur. Note: A task delay can be called here to pend
578 * rather than occupying CPU cycles - anyway it has
579 * been found that teardown takes very few cpu cycles
580 * and does not affect functionality
586 cnt
= readl(&adap_emac
->RX0CP
);
587 } while (cnt
!= 0xfffffffc);
588 writel(cnt
, &adap_emac
->RX0CP
);
589 writel(0, &adap_emac
->RX0HDP
);
592 debug_emac("- emac_ch_teardown\n");
595 /* Eth device close */
596 static void davinci_eth_close(struct eth_device
*dev
)
598 debug_emac("+ emac_close\n");
600 davinci_eth_ch_teardown(EMAC_CH_TX
); /* TX Channel teardown */
601 if (readl(&adap_emac
->RXCONTROL
) & 1)
602 davinci_eth_ch_teardown(EMAC_CH_RX
); /* RX Channel teardown */
604 /* Reset EMAC module and disable interrupts in wrapper */
605 writel(1, &adap_emac
->SOFTRESET
);
606 #if defined(DAVINCI_EMAC_VERSION2)
607 writel(1, &adap_ewrap
->softrst
);
609 writel(0, &adap_ewrap
->EWCTL
);
612 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
613 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
614 adap_ewrap
->c0rxen
= adap_ewrap
->c1rxen
= adap_ewrap
->c2rxen
= 0;
615 adap_ewrap
->c0txen
= adap_ewrap
->c1txen
= adap_ewrap
->c2txen
= 0;
616 adap_ewrap
->c0miscen
= adap_ewrap
->c1miscen
= adap_ewrap
->c2miscen
= 0;
618 debug_emac("- emac_close\n");
621 static int tx_send_loop
= 0;
624 * This function sends a single packet on the network and returns
625 * positive number (number of bytes transmitted) or negative for error
627 static int davinci_eth_send_packet (struct eth_device
*dev
,
628 void *packet
, int length
)
634 index
= get_active_phy();
636 printf(" WARN: emac_send_packet: No link\n");
640 emac_gigabit_enable(active_phy_addr
[index
]);
642 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
643 if (length
< EMAC_MIN_ETHERNET_PKT_SIZE
) {
644 length
= EMAC_MIN_ETHERNET_PKT_SIZE
;
647 /* Populate the TX descriptor */
648 emac_tx_desc
->next
= 0;
649 emac_tx_desc
->buffer
= (u_int8_t
*) packet
;
650 emac_tx_desc
->buff_off_len
= (length
& 0xffff);
651 emac_tx_desc
->pkt_flag_len
= ((length
& 0xffff) |
653 EMAC_CPPI_OWNERSHIP_BIT
|
656 flush_dcache_range((unsigned long)packet
,
657 (unsigned long)packet
+ length
);
658 davinci_flush_desc(emac_tx_desc
);
660 /* Send the packet */
661 writel(BD_TO_HW((unsigned long)emac_tx_desc
), &adap_emac
->TX0HDP
);
663 /* Wait for packet to complete or link down */
665 if (!phy
[index
].get_link_speed(active_phy_addr
[index
])) {
666 davinci_eth_ch_teardown (EMAC_CH_TX
);
670 emac_gigabit_enable(active_phy_addr
[index
]);
672 if (readl(&adap_emac
->TXINTSTATRAW
) & 0x01) {
683 * This function handles receipt of a packet from the network
685 static int davinci_eth_rcv_packet (struct eth_device
*dev
)
687 volatile emac_desc
*rx_curr_desc
;
688 volatile emac_desc
*curr_desc
;
689 volatile emac_desc
*tail_desc
;
690 int status
, ret
= -1;
692 davinci_invalidate_rx_descs();
694 rx_curr_desc
= emac_rx_active_head
;
695 status
= rx_curr_desc
->pkt_flag_len
;
696 if ((rx_curr_desc
) && ((status
& EMAC_CPPI_OWNERSHIP_BIT
) == 0)) {
697 if (status
& EMAC_CPPI_RX_ERROR_FRAME
) {
698 /* Error in packet - discard it and requeue desc */
699 printf ("WARN: emac_rcv_pkt: Error in packet\n");
701 unsigned long tmp
= (unsigned long)rx_curr_desc
->buffer
;
703 invalidate_dcache_range(tmp
, tmp
+ EMAC_RXBUF_SIZE
);
704 net_process_received_packet(
705 rx_curr_desc
->buffer
,
706 rx_curr_desc
->buff_off_len
& 0xffff);
707 ret
= rx_curr_desc
->buff_off_len
& 0xffff;
710 /* Ack received packet descriptor */
711 writel(BD_TO_HW((ulong
)rx_curr_desc
), &adap_emac
->RX0CP
);
712 curr_desc
= rx_curr_desc
;
713 emac_rx_active_head
=
714 (volatile emac_desc
*) (HW_TO_BD(rx_curr_desc
->next
));
716 if (status
& EMAC_CPPI_EOQ_BIT
) {
717 if (emac_rx_active_head
) {
718 writel(BD_TO_HW((ulong
)emac_rx_active_head
),
721 emac_rx_queue_active
= 0;
722 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
726 /* Recycle RX descriptor */
727 rx_curr_desc
->buff_off_len
= EMAC_MAX_ETHERNET_PKT_SIZE
;
728 rx_curr_desc
->pkt_flag_len
= EMAC_CPPI_OWNERSHIP_BIT
;
729 rx_curr_desc
->next
= 0;
730 davinci_flush_desc(rx_curr_desc
);
732 if (emac_rx_active_head
== 0) {
733 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
734 emac_rx_active_head
= curr_desc
;
735 emac_rx_active_tail
= curr_desc
;
736 if (emac_rx_queue_active
!= 0) {
737 writel(BD_TO_HW((ulong
)emac_rx_active_head
),
739 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
740 emac_rx_queue_active
= 1;
743 tail_desc
= emac_rx_active_tail
;
744 emac_rx_active_tail
= curr_desc
;
745 tail_desc
->next
= BD_TO_HW((ulong
) curr_desc
);
746 status
= tail_desc
->pkt_flag_len
;
747 if (status
& EMAC_CPPI_EOQ_BIT
) {
748 davinci_flush_desc(tail_desc
);
749 writel(BD_TO_HW((ulong
)curr_desc
),
751 status
&= ~EMAC_CPPI_EOQ_BIT
;
752 tail_desc
->pkt_flag_len
= status
;
754 davinci_flush_desc(tail_desc
);
762 * This function initializes the emac hardware. It does NOT initialize
763 * EMAC modules power or pin multiplexors, that is done by board_init()
764 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
766 int davinci_emac_initialize(void)
772 struct eth_device
*dev
;
774 dev
= malloc(sizeof *dev
);
779 memset(dev
, 0, sizeof *dev
);
780 strcpy(dev
->name
, "DaVinci-EMAC");
783 dev
->init
= davinci_eth_open
;
784 dev
->halt
= davinci_eth_close
;
785 dev
->send
= davinci_eth_send_packet
;
786 dev
->recv
= davinci_eth_rcv_packet
;
787 dev
->write_hwaddr
= davinci_eth_set_mac_addr
;
791 davinci_eth_mdio_enable();
793 /* let the EMAC detect the PHYs */
796 for (i
= 0; i
< 256; i
++) {
797 if (readl(&adap_mdio
->ALIVE
))
803 printf("No ETH PHY detected!!!\n");
807 /* Find if PHY(s) is/are connected */
808 ret
= davinci_eth_phy_detect();
812 debug_emac(" %d ETH PHY detected\n", ret
);
814 /* Get PHY ID and initialize phy_ops for a detected PHY */
815 for (i
= 0; i
< num_phy
; i
++) {
816 if (!davinci_eth_phy_read(active_phy_addr
[i
], MII_PHYSID1
,
818 active_phy_addr
[i
] = 0xff;
822 phy_id
= (tmp
<< 16) & 0xffff0000;
824 if (!davinci_eth_phy_read(active_phy_addr
[i
], MII_PHYSID2
,
826 active_phy_addr
[i
] = 0xff;
830 phy_id
|= tmp
& 0x0000ffff;
835 sprintf(phy
[i
].name
, "KSZ8873 @ 0x%02x",
837 phy
[i
].init
= ksz8873_init_phy
;
838 phy
[i
].is_phy_connected
= ksz8873_is_phy_connected
;
839 phy
[i
].get_link_speed
= ksz8873_get_link_speed
;
840 phy
[i
].auto_negotiate
= ksz8873_auto_negotiate
;
845 sprintf(phy
[i
].name
, "LXT972 @ 0x%02x",
847 phy
[i
].init
= lxt972_init_phy
;
848 phy
[i
].is_phy_connected
= lxt972_is_phy_connected
;
849 phy
[i
].get_link_speed
= lxt972_get_link_speed
;
850 phy
[i
].auto_negotiate
= lxt972_auto_negotiate
;
855 sprintf(phy
[i
].name
, "DP83848 @ 0x%02x",
857 phy
[i
].init
= dp83848_init_phy
;
858 phy
[i
].is_phy_connected
= dp83848_is_phy_connected
;
859 phy
[i
].get_link_speed
= dp83848_get_link_speed
;
860 phy
[i
].auto_negotiate
= dp83848_auto_negotiate
;
865 sprintf(phy
[i
].name
, "ET1011C @ 0x%02x",
867 phy
[i
].init
= gen_init_phy
;
868 phy
[i
].is_phy_connected
= gen_is_phy_connected
;
869 phy
[i
].get_link_speed
= et1011c_get_link_speed
;
870 phy
[i
].auto_negotiate
= gen_auto_negotiate
;
874 sprintf(phy
[i
].name
, "GENERIC @ 0x%02x",
876 phy
[i
].init
= gen_init_phy
;
877 phy
[i
].is_phy_connected
= gen_is_phy_connected
;
878 phy
[i
].get_link_speed
= gen_get_link_speed
;
879 phy
[i
].auto_negotiate
= gen_auto_negotiate
;
882 debug("Ethernet PHY: %s\n", phy
[i
].name
);
884 miiphy_register(phy
[i
].name
, davinci_mii_phy_read
,
885 davinci_mii_phy_write
);
888 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
889 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
890 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
891 for (i
= 0; i
< num_phy
; i
++) {
892 if (phy
[i
].is_phy_connected(i
))
893 phy
[i
].auto_negotiate(i
);