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net: davinci_emac: Remove useless dcache ops on descriptors
[people/ms/u-boot.git] / drivers / net / davinci_emac.c
1 /*
2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
7 * follows:
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * dm644x_emac.c
12 *
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
14 *
15 * Copyright (C) 2005 Texas Instruments.
16 *
17 * ----------------------------------------------------------------------------
18 *
19 * SPDX-License-Identifier: GPL-2.0+
20 *
21 * Modifications:
22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
24 */
25 #include <common.h>
26 #include <command.h>
27 #include <net.h>
28 #include <miiphy.h>
29 #include <malloc.h>
30 #include <netdev.h>
31 #include <linux/compiler.h>
32 #include <asm/arch/emac_defs.h>
33 #include <asm/io.h>
34 #include "davinci_emac.h"
35
36 unsigned int emac_dbg = 0;
37 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
38
39 #ifdef EMAC_HW_RAM_ADDR
40 static inline unsigned long BD_TO_HW(unsigned long x)
41 {
42 if (x == 0)
43 return 0;
44
45 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
46 }
47
48 static inline unsigned long HW_TO_BD(unsigned long x)
49 {
50 if (x == 0)
51 return 0;
52
53 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
54 }
55 #else
56 #define BD_TO_HW(x) (x)
57 #define HW_TO_BD(x) (x)
58 #endif
59
60 #ifdef DAVINCI_EMAC_GIG_ENABLE
61 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
62 #else
63 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
64 #endif
65
66 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
67 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
68 EMAC_MDIO_CLOCK_FREQ) - 1)
69 #endif
70
71 static void davinci_eth_mdio_enable(void);
72
73 static int gen_init_phy(int phy_addr);
74 static int gen_is_phy_connected(int phy_addr);
75 static int gen_get_link_speed(int phy_addr);
76 static int gen_auto_negotiate(int phy_addr);
77
78 void eth_mdio_enable(void)
79 {
80 davinci_eth_mdio_enable();
81 }
82
83 /* EMAC Addresses */
84 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
85 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
86 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
87
88 /* EMAC descriptors */
89 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
90 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
91 static volatile emac_desc *emac_rx_active_head = 0;
92 static volatile emac_desc *emac_rx_active_tail = 0;
93 static int emac_rx_queue_active = 0;
94
95 /* Receive packet buffers */
96 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
97 __aligned(ARCH_DMA_MINALIGN);
98
99 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
100 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
101 #endif
102
103 /* PHY address for a discovered PHY (0xff - not found) */
104 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
105
106 /* number of PHY found active */
107 static u_int8_t num_phy;
108
109 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
110
111 static int davinci_eth_set_mac_addr(struct eth_device *dev)
112 {
113 unsigned long mac_hi;
114 unsigned long mac_lo;
115
116 /*
117 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
118 * receive)
119 * Using channel 0 only - other channels are disabled
120 * */
121 writel(0, &adap_emac->MACINDEX);
122 mac_hi = (dev->enetaddr[3] << 24) |
123 (dev->enetaddr[2] << 16) |
124 (dev->enetaddr[1] << 8) |
125 (dev->enetaddr[0]);
126 mac_lo = (dev->enetaddr[5] << 8) |
127 (dev->enetaddr[4]);
128
129 writel(mac_hi, &adap_emac->MACADDRHI);
130 #if defined(DAVINCI_EMAC_VERSION2)
131 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
132 &adap_emac->MACADDRLO);
133 #else
134 writel(mac_lo, &adap_emac->MACADDRLO);
135 #endif
136
137 writel(0, &adap_emac->MACHASH1);
138 writel(0, &adap_emac->MACHASH2);
139
140 /* Set source MAC address - REQUIRED */
141 writel(mac_hi, &adap_emac->MACSRCADDRHI);
142 writel(mac_lo, &adap_emac->MACSRCADDRLO);
143
144
145 return 0;
146 }
147
148 static void davinci_eth_mdio_enable(void)
149 {
150 u_int32_t clkdiv;
151
152 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
153
154 writel((clkdiv & 0xff) |
155 MDIO_CONTROL_ENABLE |
156 MDIO_CONTROL_FAULT |
157 MDIO_CONTROL_FAULT_ENABLE,
158 &adap_mdio->CONTROL);
159
160 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
161 ;
162 }
163
164 /*
165 * Tries to find an active connected PHY. Returns 1 if address if found.
166 * If no active PHY (or more than one PHY) found returns 0.
167 * Sets active_phy_addr variable.
168 */
169 static int davinci_eth_phy_detect(void)
170 {
171 u_int32_t phy_act_state;
172 int i;
173 int j;
174 unsigned int count = 0;
175
176 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
177 active_phy_addr[i] = 0xff;
178
179 udelay(1000);
180 phy_act_state = readl(&adap_mdio->ALIVE);
181
182 if (phy_act_state == 0)
183 return 0; /* No active PHYs */
184
185 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
186
187 for (i = 0, j = 0; i < 32; i++)
188 if (phy_act_state & (1 << i)) {
189 count++;
190 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
191 active_phy_addr[j++] = i;
192 } else {
193 printf("%s: to many PHYs detected.\n",
194 __func__);
195 count = 0;
196 break;
197 }
198 }
199
200 num_phy = count;
201
202 return count;
203 }
204
205
206 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
207 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
208 {
209 int tmp;
210
211 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
212 ;
213
214 writel(MDIO_USERACCESS0_GO |
215 MDIO_USERACCESS0_WRITE_READ |
216 ((reg_num & 0x1f) << 21) |
217 ((phy_addr & 0x1f) << 16),
218 &adap_mdio->USERACCESS0);
219
220 /* Wait for command to complete */
221 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
222 ;
223
224 if (tmp & MDIO_USERACCESS0_ACK) {
225 *data = tmp & 0xffff;
226 return 0;
227 }
228
229 return -EIO;
230 }
231
232 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
233 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
234 {
235
236 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
237 ;
238
239 writel(MDIO_USERACCESS0_GO |
240 MDIO_USERACCESS0_WRITE_WRITE |
241 ((reg_num & 0x1f) << 21) |
242 ((phy_addr & 0x1f) << 16) |
243 (data & 0xffff),
244 &adap_mdio->USERACCESS0);
245
246 /* Wait for command to complete */
247 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
248 ;
249
250 return 0;
251 }
252
253 /* PHY functions for a generic PHY */
254 static int gen_init_phy(int phy_addr)
255 {
256 int ret = 1;
257
258 if (gen_get_link_speed(phy_addr)) {
259 /* Try another time */
260 ret = gen_get_link_speed(phy_addr);
261 }
262
263 return(ret);
264 }
265
266 static int gen_is_phy_connected(int phy_addr)
267 {
268 u_int16_t dummy;
269
270 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
271 }
272
273 static int get_active_phy(void)
274 {
275 int i;
276
277 for (i = 0; i < num_phy; i++)
278 if (phy[i].get_link_speed(active_phy_addr[i]))
279 return i;
280
281 return -1; /* Return error if no link */
282 }
283
284 static int gen_get_link_speed(int phy_addr)
285 {
286 u_int16_t tmp;
287
288 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
289 (tmp & 0x04)) {
290 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
291 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
292 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
293
294 /* Speed doesn't matter, there is no setting for it in EMAC. */
295 if (tmp & (LPA_100FULL | LPA_10FULL)) {
296 /* set EMAC for Full Duplex */
297 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
298 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
299 &adap_emac->MACCONTROL);
300 } else {
301 /*set EMAC for Half Duplex */
302 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
303 &adap_emac->MACCONTROL);
304 }
305
306 if (tmp & (LPA_100FULL | LPA_100HALF))
307 writel(readl(&adap_emac->MACCONTROL) |
308 EMAC_MACCONTROL_RMIISPEED_100,
309 &adap_emac->MACCONTROL);
310 else
311 writel(readl(&adap_emac->MACCONTROL) &
312 ~EMAC_MACCONTROL_RMIISPEED_100,
313 &adap_emac->MACCONTROL);
314 #endif
315 return(1);
316 }
317
318 return(0);
319 }
320
321 static int gen_auto_negotiate(int phy_addr)
322 {
323 u_int16_t tmp;
324 u_int16_t val;
325 unsigned long cntr = 0;
326
327 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
328 return 0;
329
330 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
331 BMCR_SPEED100;
332 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
333
334 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
335 return 0;
336
337 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
338 ADVERTISE_10HALF);
339 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
340
341 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
342 return(0);
343
344 /* Restart Auto_negotiation */
345 tmp |= BMCR_ANRESTART;
346 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
347
348 /*check AutoNegotiate complete */
349 do {
350 udelay(40000);
351 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
352 return 0;
353
354 if (tmp & BMSR_ANEGCOMPLETE)
355 break;
356
357 cntr++;
358 } while (cntr < 200);
359
360 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
361 return(0);
362
363 if (!(tmp & BMSR_ANEGCOMPLETE))
364 return(0);
365
366 return(gen_get_link_speed(phy_addr));
367 }
368 /* End of generic PHY functions */
369
370
371 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
372 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
373 int reg)
374 {
375 unsigned short value = 0;
376 int retval = davinci_eth_phy_read(addr, reg, &value);
377 if (retval < 0)
378 return retval;
379 return value;
380 }
381
382 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
383 int reg, u16 value)
384 {
385 return davinci_eth_phy_write(addr, reg, value);
386 }
387 #endif
388
389 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
390 {
391 u_int16_t data;
392
393 if (davinci_eth_phy_read(phy_addr, 0, &data)) {
394 if (data & (1 << 6)) { /* speed selection MSB */
395 /*
396 * Check if link detected is giga-bit
397 * If Gigabit mode detected, enable gigbit in MAC
398 */
399 writel(readl(&adap_emac->MACCONTROL) |
400 EMAC_MACCONTROL_GIGFORCE |
401 EMAC_MACCONTROL_GIGABIT_ENABLE,
402 &adap_emac->MACCONTROL);
403 }
404 }
405 }
406
407 /* Eth device open */
408 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
409 {
410 dv_reg_p addr;
411 u_int32_t clkdiv, cnt;
412 volatile emac_desc *rx_desc;
413 int index;
414
415 debug_emac("+ emac_open\n");
416
417 /* Reset EMAC module and disable interrupts in wrapper */
418 writel(1, &adap_emac->SOFTRESET);
419 while (readl(&adap_emac->SOFTRESET) != 0)
420 ;
421 #if defined(DAVINCI_EMAC_VERSION2)
422 writel(1, &adap_ewrap->softrst);
423 while (readl(&adap_ewrap->softrst) != 0)
424 ;
425 #else
426 writel(0, &adap_ewrap->EWCTL);
427 for (cnt = 0; cnt < 5; cnt++) {
428 clkdiv = readl(&adap_ewrap->EWCTL);
429 }
430 #endif
431
432 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
433 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
434 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
435 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
436 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
437 #endif
438 rx_desc = emac_rx_desc;
439
440 writel(1, &adap_emac->TXCONTROL);
441 writel(1, &adap_emac->RXCONTROL);
442
443 davinci_eth_set_mac_addr(dev);
444
445 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
446 addr = &adap_emac->TX0HDP;
447 for (cnt = 0; cnt < 8; cnt++)
448 writel(0, addr++);
449
450 addr = &adap_emac->RX0HDP;
451 for (cnt = 0; cnt < 8; cnt++)
452 writel(0, addr++);
453
454 /* Clear Statistics (do this before setting MacControl register) */
455 addr = &adap_emac->RXGOODFRAMES;
456 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
457 writel(0, addr++);
458
459 /* No multicast addressing */
460 writel(0, &adap_emac->MACHASH1);
461 writel(0, &adap_emac->MACHASH2);
462
463 /* Create RX queue and set receive process in place */
464 emac_rx_active_head = emac_rx_desc;
465 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
466 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
467 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
468 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
469 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
470 rx_desc++;
471 }
472
473 /* Finalize the rx desc list */
474 rx_desc--;
475 rx_desc->next = 0;
476 emac_rx_active_tail = rx_desc;
477 emac_rx_queue_active = 1;
478
479 /* Enable TX/RX */
480 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
481 writel(0, &adap_emac->RXBUFFEROFFSET);
482
483 /*
484 * No fancy configs - Use this for promiscous debug
485 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
486 */
487 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
488
489 /* Enable ch 0 only */
490 writel(1, &adap_emac->RXUNICASTSET);
491
492 /* Enable MII interface and Full duplex mode */
493 #if defined(CONFIG_SOC_DA8XX) || \
494 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
495 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
496 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
497 EMAC_MACCONTROL_RMIISPEED_100),
498 &adap_emac->MACCONTROL);
499 #else
500 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
501 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
502 &adap_emac->MACCONTROL);
503 #endif
504
505 /* Init MDIO & get link state */
506 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
507 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
508 &adap_mdio->CONTROL);
509
510 /* We need to wait for MDIO to start */
511 udelay(1000);
512
513 index = get_active_phy();
514 if (index == -1)
515 return(0);
516
517 emac_gigabit_enable(active_phy_addr[index]);
518
519 /* Start receive process */
520 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
521
522 debug_emac("- emac_open\n");
523
524 return(1);
525 }
526
527 /* EMAC Channel Teardown */
528 static void davinci_eth_ch_teardown(int ch)
529 {
530 dv_reg dly = 0xff;
531 dv_reg cnt;
532
533 debug_emac("+ emac_ch_teardown\n");
534
535 if (ch == EMAC_CH_TX) {
536 /* Init TX channel teardown */
537 writel(0, &adap_emac->TXTEARDOWN);
538 do {
539 /*
540 * Wait here for Tx teardown completion interrupt to
541 * occur. Note: A task delay can be called here to pend
542 * rather than occupying CPU cycles - anyway it has
543 * been found that teardown takes very few cpu cycles
544 * and does not affect functionality
545 */
546 dly--;
547 udelay(1);
548 if (dly == 0)
549 break;
550 cnt = readl(&adap_emac->TX0CP);
551 } while (cnt != 0xfffffffc);
552 writel(cnt, &adap_emac->TX0CP);
553 writel(0, &adap_emac->TX0HDP);
554 } else {
555 /* Init RX channel teardown */
556 writel(0, &adap_emac->RXTEARDOWN);
557 do {
558 /*
559 * Wait here for Rx teardown completion interrupt to
560 * occur. Note: A task delay can be called here to pend
561 * rather than occupying CPU cycles - anyway it has
562 * been found that teardown takes very few cpu cycles
563 * and does not affect functionality
564 */
565 dly--;
566 udelay(1);
567 if (dly == 0)
568 break;
569 cnt = readl(&adap_emac->RX0CP);
570 } while (cnt != 0xfffffffc);
571 writel(cnt, &adap_emac->RX0CP);
572 writel(0, &adap_emac->RX0HDP);
573 }
574
575 debug_emac("- emac_ch_teardown\n");
576 }
577
578 /* Eth device close */
579 static void davinci_eth_close(struct eth_device *dev)
580 {
581 debug_emac("+ emac_close\n");
582
583 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
584 if (readl(&adap_emac->RXCONTROL) & 1)
585 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
586
587 /* Reset EMAC module and disable interrupts in wrapper */
588 writel(1, &adap_emac->SOFTRESET);
589 #if defined(DAVINCI_EMAC_VERSION2)
590 writel(1, &adap_ewrap->softrst);
591 #else
592 writel(0, &adap_ewrap->EWCTL);
593 #endif
594
595 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
596 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
597 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
598 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
599 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
600 #endif
601 debug_emac("- emac_close\n");
602 }
603
604 static int tx_send_loop = 0;
605
606 /*
607 * This function sends a single packet on the network and returns
608 * positive number (number of bytes transmitted) or negative for error
609 */
610 static int davinci_eth_send_packet (struct eth_device *dev,
611 void *packet, int length)
612 {
613 int ret_status = -1;
614 int index;
615 tx_send_loop = 0;
616
617 index = get_active_phy();
618 if (index == -1) {
619 printf(" WARN: emac_send_packet: No link\n");
620 return (ret_status);
621 }
622
623 emac_gigabit_enable(active_phy_addr[index]);
624
625 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
626 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
627 length = EMAC_MIN_ETHERNET_PKT_SIZE;
628 }
629
630 /* Populate the TX descriptor */
631 emac_tx_desc->next = 0;
632 emac_tx_desc->buffer = (u_int8_t *) packet;
633 emac_tx_desc->buff_off_len = (length & 0xffff);
634 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
635 EMAC_CPPI_SOP_BIT |
636 EMAC_CPPI_OWNERSHIP_BIT |
637 EMAC_CPPI_EOP_BIT);
638
639 flush_dcache_range((unsigned long)packet,
640 (unsigned long)packet + length);
641
642 /* Send the packet */
643 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
644
645 /* Wait for packet to complete or link down */
646 while (1) {
647 if (!phy[index].get_link_speed(active_phy_addr[index])) {
648 davinci_eth_ch_teardown (EMAC_CH_TX);
649 return (ret_status);
650 }
651
652 emac_gigabit_enable(active_phy_addr[index]);
653
654 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
655 ret_status = length;
656 break;
657 }
658 tx_send_loop++;
659 }
660
661 return (ret_status);
662 }
663
664 /*
665 * This function handles receipt of a packet from the network
666 */
667 static int davinci_eth_rcv_packet (struct eth_device *dev)
668 {
669 volatile emac_desc *rx_curr_desc;
670 volatile emac_desc *curr_desc;
671 volatile emac_desc *tail_desc;
672 int status, ret = -1;
673
674 rx_curr_desc = emac_rx_active_head;
675 if (!rx_curr_desc)
676 return 0;
677 status = rx_curr_desc->pkt_flag_len;
678 if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
679 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
680 /* Error in packet - discard it and requeue desc */
681 printf ("WARN: emac_rcv_pkt: Error in packet\n");
682 } else {
683 unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
684
685 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
686 net_process_received_packet(
687 rx_curr_desc->buffer,
688 rx_curr_desc->buff_off_len & 0xffff);
689 ret = rx_curr_desc->buff_off_len & 0xffff;
690 }
691
692 /* Ack received packet descriptor */
693 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
694 curr_desc = rx_curr_desc;
695 emac_rx_active_head =
696 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
697
698 if (status & EMAC_CPPI_EOQ_BIT) {
699 if (emac_rx_active_head) {
700 writel(BD_TO_HW((ulong)emac_rx_active_head),
701 &adap_emac->RX0HDP);
702 } else {
703 emac_rx_queue_active = 0;
704 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
705 }
706 }
707
708 /* Recycle RX descriptor */
709 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
710 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
711 rx_curr_desc->next = 0;
712
713 if (emac_rx_active_head == 0) {
714 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
715 emac_rx_active_head = curr_desc;
716 emac_rx_active_tail = curr_desc;
717 if (emac_rx_queue_active != 0) {
718 writel(BD_TO_HW((ulong)emac_rx_active_head),
719 &adap_emac->RX0HDP);
720 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
721 emac_rx_queue_active = 1;
722 }
723 } else {
724 tail_desc = emac_rx_active_tail;
725 emac_rx_active_tail = curr_desc;
726 tail_desc->next = BD_TO_HW((ulong) curr_desc);
727 status = tail_desc->pkt_flag_len;
728 if (status & EMAC_CPPI_EOQ_BIT) {
729 writel(BD_TO_HW((ulong)curr_desc),
730 &adap_emac->RX0HDP);
731 status &= ~EMAC_CPPI_EOQ_BIT;
732 tail_desc->pkt_flag_len = status;
733 }
734 }
735 return (ret);
736 }
737 return (0);
738 }
739
740 /*
741 * This function initializes the emac hardware. It does NOT initialize
742 * EMAC modules power or pin multiplexors, that is done by board_init()
743 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
744 */
745 int davinci_emac_initialize(void)
746 {
747 u_int32_t phy_id;
748 u_int16_t tmp;
749 int i;
750 int ret;
751 struct eth_device *dev;
752
753 dev = malloc(sizeof *dev);
754
755 if (dev == NULL)
756 return -1;
757
758 memset(dev, 0, sizeof *dev);
759 strcpy(dev->name, "DaVinci-EMAC");
760
761 dev->iobase = 0;
762 dev->init = davinci_eth_open;
763 dev->halt = davinci_eth_close;
764 dev->send = davinci_eth_send_packet;
765 dev->recv = davinci_eth_rcv_packet;
766 dev->write_hwaddr = davinci_eth_set_mac_addr;
767
768 eth_register(dev);
769
770 davinci_eth_mdio_enable();
771
772 /* let the EMAC detect the PHYs */
773 udelay(5000);
774
775 for (i = 0; i < 256; i++) {
776 if (readl(&adap_mdio->ALIVE))
777 break;
778 udelay(1000);
779 }
780
781 if (i >= 256) {
782 printf("No ETH PHY detected!!!\n");
783 return(0);
784 }
785
786 /* Find if PHY(s) is/are connected */
787 ret = davinci_eth_phy_detect();
788 if (!ret)
789 return(0);
790 else
791 debug_emac(" %d ETH PHY detected\n", ret);
792
793 /* Get PHY ID and initialize phy_ops for a detected PHY */
794 for (i = 0; i < num_phy; i++) {
795 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
796 &tmp)) {
797 active_phy_addr[i] = 0xff;
798 continue;
799 }
800
801 phy_id = (tmp << 16) & 0xffff0000;
802
803 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
804 &tmp)) {
805 active_phy_addr[i] = 0xff;
806 continue;
807 }
808
809 phy_id |= tmp & 0x0000ffff;
810
811 switch (phy_id) {
812 #ifdef PHY_KSZ8873
813 case PHY_KSZ8873:
814 sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
815 active_phy_addr[i]);
816 phy[i].init = ksz8873_init_phy;
817 phy[i].is_phy_connected = ksz8873_is_phy_connected;
818 phy[i].get_link_speed = ksz8873_get_link_speed;
819 phy[i].auto_negotiate = ksz8873_auto_negotiate;
820 break;
821 #endif
822 #ifdef PHY_LXT972
823 case PHY_LXT972:
824 sprintf(phy[i].name, "LXT972 @ 0x%02x",
825 active_phy_addr[i]);
826 phy[i].init = lxt972_init_phy;
827 phy[i].is_phy_connected = lxt972_is_phy_connected;
828 phy[i].get_link_speed = lxt972_get_link_speed;
829 phy[i].auto_negotiate = lxt972_auto_negotiate;
830 break;
831 #endif
832 #ifdef PHY_DP83848
833 case PHY_DP83848:
834 sprintf(phy[i].name, "DP83848 @ 0x%02x",
835 active_phy_addr[i]);
836 phy[i].init = dp83848_init_phy;
837 phy[i].is_phy_connected = dp83848_is_phy_connected;
838 phy[i].get_link_speed = dp83848_get_link_speed;
839 phy[i].auto_negotiate = dp83848_auto_negotiate;
840 break;
841 #endif
842 #ifdef PHY_ET1011C
843 case PHY_ET1011C:
844 sprintf(phy[i].name, "ET1011C @ 0x%02x",
845 active_phy_addr[i]);
846 phy[i].init = gen_init_phy;
847 phy[i].is_phy_connected = gen_is_phy_connected;
848 phy[i].get_link_speed = et1011c_get_link_speed;
849 phy[i].auto_negotiate = gen_auto_negotiate;
850 break;
851 #endif
852 default:
853 sprintf(phy[i].name, "GENERIC @ 0x%02x",
854 active_phy_addr[i]);
855 phy[i].init = gen_init_phy;
856 phy[i].is_phy_connected = gen_is_phy_connected;
857 phy[i].get_link_speed = gen_get_link_speed;
858 phy[i].auto_negotiate = gen_auto_negotiate;
859 }
860
861 debug("Ethernet PHY: %s\n", phy[i].name);
862
863 int retval;
864 struct mii_dev *mdiodev = mdio_alloc();
865 if (!mdiodev)
866 return -ENOMEM;
867 strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
868 mdiodev->read = davinci_mii_phy_read;
869 mdiodev->write = davinci_mii_phy_write;
870
871 retval = mdio_register(mdiodev);
872 if (retval < 0)
873 return retval;
874 }
875
876 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
877 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
878 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
879 for (i = 0; i < num_phy; i++) {
880 if (phy[i].is_phy_connected(i))
881 phy[i].auto_negotiate(i);
882 }
883 #endif
884 return(1);
885 }
"Das U-Boot" Source Tree