drivers/net/designware.h

   1 /*
   2  * (C) Copyright 2010
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _DW_ETH_H
   9 #define _DW_ETH_H
  10
  11 #include <asm/gpio.h>
  12
  13 #define CONFIG_TX_DESCR_NUM     16
  14 #define CONFIG_RX_DESCR_NUM     16
  15 #define CONFIG_ETH_BUFSIZE      2048
  16 #define TX_TOTAL_BUFSIZE        (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  17 #define RX_TOTAL_BUFSIZE        (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  18
  19 #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
  20 #define CONFIG_MDIO_TIMEOUT     (3 * CONFIG_SYS_HZ)
  21
  22 struct eth_mac_regs {
  23         u32 conf;               /* 0x00 */
  24         u32 framefilt;          /* 0x04 */
  25         u32 hashtablehigh;      /* 0x08 */
  26         u32 hashtablelow;       /* 0x0c */
  27         u32 miiaddr;            /* 0x10 */
  28         u32 miidata;            /* 0x14 */
  29         u32 flowcontrol;        /* 0x18 */
  30         u32 vlantag;            /* 0x1c */
  31         u32 version;            /* 0x20 */
  32         u8 reserved_1[20];
  33         u32 intreg;             /* 0x38 */
  34         u32 intmask;            /* 0x3c */
  35         u32 macaddr0hi;         /* 0x40 */
  36         u32 macaddr0lo;         /* 0x44 */
  37 };
  38
  39 /* MAC configuration register definitions */
  40 #define FRAMEBURSTENABLE        (1 << 21)
  41 #define MII_PORTSELECT          (1 << 15)
  42 #define FES_100                 (1 << 14)
  43 #define DISABLERXOWN            (1 << 13)
  44 #define FULLDPLXMODE            (1 << 11)
  45 #define RXENABLE                (1 << 2)
  46 #define TXENABLE                (1 << 3)
  47
  48 /* MII address register definitions */
  49 #define MII_BUSY                (1 << 0)
  50 #define MII_WRITE               (1 << 1)
  51 #define MII_CLKRANGE_60_100M    (0)
  52 #define MII_CLKRANGE_100_150M   (0x4)
  53 #define MII_CLKRANGE_20_35M     (0x8)
  54 #define MII_CLKRANGE_35_60M     (0xC)
  55 #define MII_CLKRANGE_150_250M   (0x10)
  56 #define MII_CLKRANGE_250_300M   (0x14)
  57
  58 #define MIIADDRSHIFT            (11)
  59 #define MIIREGSHIFT             (6)
  60 #define MII_REGMSK              (0x1F << 6)
  61 #define MII_ADDRMSK             (0x1F << 11)
  62
  63
  64 struct eth_dma_regs {
  65         u32 busmode;            /* 0x00 */
  66         u32 txpolldemand;       /* 0x04 */
  67         u32 rxpolldemand;       /* 0x08 */
  68         u32 rxdesclistaddr;     /* 0x0c */
  69         u32 txdesclistaddr;     /* 0x10 */
  70         u32 status;             /* 0x14 */
  71         u32 opmode;             /* 0x18 */
  72         u32 intenable;          /* 0x1c */
  73         u32 reserved1[2];
  74         u32 axibus;             /* 0x28 */
  75         u32 reserved2[7];
  76         u32 currhosttxdesc;     /* 0x48 */
  77         u32 currhostrxdesc;     /* 0x4c */
  78         u32 currhosttxbuffaddr; /* 0x50 */
  79         u32 currhostrxbuffaddr; /* 0x54 */
  80 };
  81
  82 #define DW_DMA_BASE_OFFSET      (0x1000)
  83
  84 /* Default DMA Burst length */
  85 #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
  86 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
  87 #endif
  88
  89 /* Bus mode register definitions */
  90 #define FIXEDBURST              (1 << 16)
  91 #define PRIORXTX_41             (3 << 14)
  92 #define PRIORXTX_31             (2 << 14)
  93 #define PRIORXTX_21             (1 << 14)
  94 #define PRIORXTX_11             (0 << 14)
  95 #define DMA_PBL                 (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
  96 #define RXHIGHPRIO              (1 << 1)
  97 #define DMAMAC_SRST             (1 << 0)
  98
  99 /* Poll demand definitions */
 100 #define POLL_DATA               (0xFFFFFFFF)
 101
 102 /* Operation mode definitions */
 103 #define STOREFORWARD            (1 << 21)
 104 #define FLUSHTXFIFO             (1 << 20)
 105 #define TXSTART                 (1 << 13)
 106 #define TXSECONDFRAME           (1 << 2)
 107 #define RXSTART                 (1 << 1)
 108
 109 /* Descriptior related definitions */
 110 #define MAC_MAX_FRAME_SZ        (1600)
 111
 112 struct dmamacdescr {
 113         u32 txrx_status;
 114         u32 dmamac_cntl;
 115         void *dmamac_addr;
 116         struct dmamacdescr *dmamac_next;
 117 } __aligned(ARCH_DMA_MINALIGN);
 118
 119 /*
 120  * txrx_status definitions
 121  */
 122
 123 /* tx status bits definitions */
 124 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 125
 126 #define DESC_TXSTS_OWNBYDMA             (1 << 31)
 127 #define DESC_TXSTS_TXINT                (1 << 30)
 128 #define DESC_TXSTS_TXLAST               (1 << 29)
 129 #define DESC_TXSTS_TXFIRST              (1 << 28)
 130 #define DESC_TXSTS_TXCRCDIS             (1 << 27)
 131
 132 #define DESC_TXSTS_TXPADDIS             (1 << 26)
 133 #define DESC_TXSTS_TXCHECKINSCTRL       (3 << 22)
 134 #define DESC_TXSTS_TXRINGEND            (1 << 21)
 135 #define DESC_TXSTS_TXCHAIN              (1 << 20)
 136 #define DESC_TXSTS_MSK                  (0x1FFFF << 0)
 137
 138 #else
 139
 140 #define DESC_TXSTS_OWNBYDMA             (1 << 31)
 141 #define DESC_TXSTS_MSK                  (0x1FFFF << 0)
 142
 143 #endif
 144
 145 /* rx status bits definitions */
 146 #define DESC_RXSTS_OWNBYDMA             (1 << 31)
 147 #define DESC_RXSTS_DAFILTERFAIL         (1 << 30)
 148 #define DESC_RXSTS_FRMLENMSK            (0x3FFF << 16)
 149 #define DESC_RXSTS_FRMLENSHFT           (16)
 150
 151 #define DESC_RXSTS_ERROR                (1 << 15)
 152 #define DESC_RXSTS_RXTRUNCATED          (1 << 14)
 153 #define DESC_RXSTS_SAFILTERFAIL         (1 << 13)
 154 #define DESC_RXSTS_RXIPC_GIANTFRAME     (1 << 12)
 155 #define DESC_RXSTS_RXDAMAGED            (1 << 11)
 156 #define DESC_RXSTS_RXVLANTAG            (1 << 10)
 157 #define DESC_RXSTS_RXFIRST              (1 << 9)
 158 #define DESC_RXSTS_RXLAST               (1 << 8)
 159 #define DESC_RXSTS_RXIPC_GIANT          (1 << 7)
 160 #define DESC_RXSTS_RXCOLLISION          (1 << 6)
 161 #define DESC_RXSTS_RXFRAMEETHER         (1 << 5)
 162 #define DESC_RXSTS_RXWATCHDOG           (1 << 4)
 163 #define DESC_RXSTS_RXMIIERROR           (1 << 3)
 164 #define DESC_RXSTS_RXDRIBBLING          (1 << 2)
 165 #define DESC_RXSTS_RXCRC                (1 << 1)
 166
 167 /*
 168  * dmamac_cntl definitions
 169  */
 170
 171 /* tx control bits definitions */
 172 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 173
 174 #define DESC_TXCTRL_SIZE1MASK           (0x1FFF << 0)
 175 #define DESC_TXCTRL_SIZE1SHFT           (0)
 176 #define DESC_TXCTRL_SIZE2MASK           (0x1FFF << 16)
 177 #define DESC_TXCTRL_SIZE2SHFT           (16)
 178
 179 #else
 180
 181 #define DESC_TXCTRL_TXINT               (1 << 31)
 182 #define DESC_TXCTRL_TXLAST              (1 << 30)
 183 #define DESC_TXCTRL_TXFIRST             (1 << 29)
 184 #define DESC_TXCTRL_TXCHECKINSCTRL      (3 << 27)
 185 #define DESC_TXCTRL_TXCRCDIS            (1 << 26)
 186 #define DESC_TXCTRL_TXRINGEND           (1 << 25)
 187 #define DESC_TXCTRL_TXCHAIN             (1 << 24)
 188
 189 #define DESC_TXCTRL_SIZE1MASK           (0x7FF << 0)
 190 #define DESC_TXCTRL_SIZE1SHFT           (0)
 191 #define DESC_TXCTRL_SIZE2MASK           (0x7FF << 11)
 192 #define DESC_TXCTRL_SIZE2SHFT           (11)
 193
 194 #endif
 195
 196 /* rx control bits definitions */
 197 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 198
 199 #define DESC_RXCTRL_RXINTDIS            (1 << 31)
 200 #define DESC_RXCTRL_RXRINGEND           (1 << 15)
 201 #define DESC_RXCTRL_RXCHAIN             (1 << 14)
 202
 203 #define DESC_RXCTRL_SIZE1MASK           (0x1FFF << 0)
 204 #define DESC_RXCTRL_SIZE1SHFT           (0)
 205 #define DESC_RXCTRL_SIZE2MASK           (0x1FFF << 16)
 206 #define DESC_RXCTRL_SIZE2SHFT           (16)
 207
 208 #else
 209
 210 #define DESC_RXCTRL_RXINTDIS            (1 << 31)
 211 #define DESC_RXCTRL_RXRINGEND           (1 << 25)
 212 #define DESC_RXCTRL_RXCHAIN             (1 << 24)
 213
 214 #define DESC_RXCTRL_SIZE1MASK           (0x7FF << 0)
 215 #define DESC_RXCTRL_SIZE1SHFT           (0)
 216 #define DESC_RXCTRL_SIZE2MASK           (0x7FF << 11)
 217 #define DESC_RXCTRL_SIZE2SHFT           (11)
 218
 219 #endif
 220
 221 struct dw_eth_dev {
 222         struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
 223         struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
 224         char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 225         char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 226
 227         u32 interface;
 228         u32 max_speed;
 229         u32 tx_currdescnum;
 230         u32 rx_currdescnum;
 231
 232         struct eth_mac_regs *mac_regs_p;
 233         struct eth_dma_regs *dma_regs_p;
 234 #ifndef CONFIG_DM_ETH
 235         struct eth_device *dev;
 236 #endif
 237         struct gpio_desc reset_gpio;
 238         struct phy_device *phydev;
 239         struct mii_dev *bus;
 240 };
 241
 242 #ifdef CONFIG_DM_ETH
 243 struct dw_eth_pdata {
 244         struct eth_pdata eth_pdata;
 245         u32 reset_delays[3];
 246 };
 247 #endif
 248
 249 #endif