drivers/net/e1000.h

   1 /*******************************************************************************
   2
   3
   4   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms of the GNU General Public License as published by the Free
   8   Software Foundation; either version 2 of the License, or (at your option)
   9   any later version.
  10
  11   This program is distributed in the hope that it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc., 59
  18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  19
  20   The full GNU General Public License is included in this distribution in the
  21   file called LICENSE.
  22
  23   Contact Information:
  24   Linux NICS <linux.nics@intel.com>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* e1000_hw.h
  30  * Structures, enums, and macros for the MAC
  31  */
  32
  33 #ifndef _E1000_HW_H_
  34 #define _E1000_HW_H_
  35
  36 #include <common.h>
  37 #include <malloc.h>
  38 #include <net.h>
  39 #include <netdev.h>
  40 #include <asm/io.h>
  41 #include <pci.h>
  42
  43 #define E1000_ERR(args...) printf("e1000: " args)
  44
  45 #ifdef E1000_DEBUG
  46 #define E1000_DBG(args...)      printf("e1000: " args)
  47 #define DEBUGOUT(fmt,args...) printf(fmt ,##args)
  48 #define DEBUGFUNC()        printf("%s\n", __FUNCTION__);
  49 #else
  50 #define E1000_DBG(args...)
  51 #define DEBUGFUNC()
  52 #define DEBUGOUT(fmt,args...)
  53 #endif
  54
  55 /* Forward declarations of structures used by the shared code */
  56 struct e1000_hw;
  57 struct e1000_hw_stats;
  58
  59 typedef enum {
  60         FALSE = 0,
  61         TRUE = 1
  62 } boolean_t;
  63
  64 /* Enumerated types specific to the e1000 hardware */
  65 /* Media Access Controlers */
  66 typedef enum {
  67         e1000_undefined = 0,
  68         e1000_82542_rev2_0,
  69         e1000_82542_rev2_1,
  70         e1000_82543,
  71         e1000_82544,
  72         e1000_82540,
  73         e1000_82545,
  74         e1000_82546,
  75         e1000_82541,
  76         e1000_82541_rev_2,
  77         e1000_num_macs
  78 } e1000_mac_type;
  79
  80 /* Media Types */
  81 typedef enum {
  82         e1000_media_type_copper = 0,
  83         e1000_media_type_fiber = 1,
  84         e1000_num_media_types
  85 } e1000_media_type;
  86
  87 typedef enum {
  88         e1000_10_half = 0,
  89         e1000_10_full = 1,
  90         e1000_100_half = 2,
  91         e1000_100_full = 3
  92 } e1000_speed_duplex_type;
  93
  94 typedef enum {
  95         e1000_lan_a = 0,
  96         e1000_lan_b = 1
  97 } e1000_lan_loc;
  98
  99 /* Flow Control Settings */
 100 typedef enum {
 101         e1000_fc_none = 0,
 102         e1000_fc_rx_pause = 1,
 103         e1000_fc_tx_pause = 2,
 104         e1000_fc_full = 3,
 105         e1000_fc_default = 0xFF
 106 } e1000_fc_type;
 107
 108 /* PCI bus types */
 109 typedef enum {
 110         e1000_bus_type_unknown = 0,
 111         e1000_bus_type_pci,
 112         e1000_bus_type_pcix
 113 } e1000_bus_type;
 114
 115 /* PCI bus speeds */
 116 typedef enum {
 117         e1000_bus_speed_unknown = 0,
 118         e1000_bus_speed_33,
 119         e1000_bus_speed_66,
 120         e1000_bus_speed_100,
 121         e1000_bus_speed_133,
 122         e1000_bus_speed_reserved
 123 } e1000_bus_speed;
 124
 125 /* PCI bus widths */
 126 typedef enum {
 127         e1000_bus_width_unknown = 0,
 128         e1000_bus_width_32,
 129         e1000_bus_width_64
 130 } e1000_bus_width;
 131
 132 /* PHY status info structure and supporting enums */
 133 typedef enum {
 134         e1000_cable_length_50 = 0,
 135         e1000_cable_length_50_80,
 136         e1000_cable_length_80_110,
 137         e1000_cable_length_110_140,
 138         e1000_cable_length_140,
 139         e1000_cable_length_undefined = 0xFF
 140 } e1000_cable_length;
 141
 142 typedef enum {
 143         e1000_10bt_ext_dist_enable_normal = 0,
 144         e1000_10bt_ext_dist_enable_lower,
 145         e1000_10bt_ext_dist_enable_undefined = 0xFF
 146 } e1000_10bt_ext_dist_enable;
 147
 148 typedef enum {
 149         e1000_rev_polarity_normal = 0,
 150         e1000_rev_polarity_reversed,
 151         e1000_rev_polarity_undefined = 0xFF
 152 } e1000_rev_polarity;
 153
 154 typedef enum {
 155         e1000_polarity_reversal_enabled = 0,
 156         e1000_polarity_reversal_disabled,
 157         e1000_polarity_reversal_undefined = 0xFF
 158 } e1000_polarity_reversal;
 159
 160 typedef enum {
 161         e1000_auto_x_mode_manual_mdi = 0,
 162         e1000_auto_x_mode_manual_mdix,
 163         e1000_auto_x_mode_auto1,
 164         e1000_auto_x_mode_auto2,
 165         e1000_auto_x_mode_undefined = 0xFF
 166 } e1000_auto_x_mode;
 167
 168 typedef enum {
 169         e1000_1000t_rx_status_not_ok = 0,
 170         e1000_1000t_rx_status_ok,
 171         e1000_1000t_rx_status_undefined = 0xFF
 172 } e1000_1000t_rx_status;
 173
 174 typedef enum {
 175     e1000_phy_m88 = 0,
 176     e1000_phy_igp,
 177     e1000_phy_igp_2,
 178     e1000_phy_undefined = 0xFF
 179 } e1000_phy_type;
 180
 181 struct e1000_phy_info {
 182         e1000_cable_length cable_length;
 183         e1000_10bt_ext_dist_enable extended_10bt_distance;
 184         e1000_rev_polarity cable_polarity;
 185         e1000_polarity_reversal polarity_correction;
 186         e1000_auto_x_mode mdix_mode;
 187         e1000_1000t_rx_status local_rx;
 188         e1000_1000t_rx_status remote_rx;
 189 };
 190
 191 struct e1000_phy_stats {
 192         uint32_t idle_errors;
 193         uint32_t receive_errors;
 194 };
 195
 196 /* Error Codes */
 197 #define E1000_SUCCESS                           0
 198 #define E1000_ERR_EEPROM                        1
 199 #define E1000_ERR_PHY                           2
 200 #define E1000_ERR_CONFIG                        3
 201 #define E1000_ERR_PARAM                         4
 202 #define E1000_ERR_MAC_TYPE                      5
 203 #define E1000_ERR_PHY_TYPE                      6
 204 #define E1000_ERR_NOLINK                        7
 205 #define E1000_ERR_TIMEOUT                       8
 206 #define E1000_ERR_RESET                         9
 207 #define E1000_ERR_MASTER_REQUESTS_PENDING       10
 208 #define E1000_ERR_HOST_INTERFACE_COMMAND        11
 209 #define E1000_BLK_PHY_RESET                     12
 210
 211 /* PCI Device IDs */
 212 #define E1000_DEV_ID_82542          0x1000
 213 #define E1000_DEV_ID_82543GC_FIBER  0x1001
 214 #define E1000_DEV_ID_82543GC_COPPER 0x1004
 215 #define E1000_DEV_ID_82544EI_COPPER 0x1008
 216 #define E1000_DEV_ID_82544EI_FIBER  0x1009
 217 #define E1000_DEV_ID_82544GC_COPPER 0x100C
 218 #define E1000_DEV_ID_82544GC_LOM    0x100D
 219 #define E1000_DEV_ID_82540EM        0x100E
 220 #define E1000_DEV_ID_82540EM_LOM    0x1015
 221 #define E1000_DEV_ID_82545GM_COPPER 0x1026
 222 #define E1000_DEV_ID_82545EM_COPPER 0x100F
 223 #define E1000_DEV_ID_82545EM_FIBER  0x1011
 224 #define E1000_DEV_ID_82546EB_COPPER 0x1010
 225 #define E1000_DEV_ID_82546EB_FIBER  0x1012
 226 #define E1000_DEV_ID_82541ER        0x1078
 227 #define E1000_DEV_ID_82541GI_LF     0x107C
 228 #define NUM_DEV_IDS 16
 229
 230 #define NODE_ADDRESS_SIZE 6
 231 #define ETH_LENGTH_OF_ADDRESS 6
 232
 233 /* MAC decode size is 128K - This is the size of BAR0 */
 234 #define MAC_DECODE_SIZE (128 * 1024)
 235
 236 #define E1000_82542_2_0_REV_ID 2
 237 #define E1000_82542_2_1_REV_ID 3
 238
 239 #define SPEED_10    10
 240 #define SPEED_100   100
 241 #define SPEED_1000  1000
 242 #define HALF_DUPLEX 1
 243 #define FULL_DUPLEX 2
 244
 245 /* The sizes (in bytes) of a ethernet packet */
 246 #define ENET_HEADER_SIZE             14
 247 #define MAXIMUM_ETHERNET_FRAME_SIZE  1518       /* With FCS */
 248 #define MINIMUM_ETHERNET_FRAME_SIZE  64 /* With FCS */
 249 #define ETHERNET_FCS_SIZE            4
 250 #define MAXIMUM_ETHERNET_PACKET_SIZE \
 251     (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 252 #define MINIMUM_ETHERNET_PACKET_SIZE \
 253     (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 254 #define CRC_LENGTH                   ETHERNET_FCS_SIZE
 255 #define MAX_JUMBO_FRAME_SIZE         0x3F00
 256
 257 /* 802.1q VLAN Packet Sizes */
 258 #define VLAN_TAG_SIZE                     4     /* 802.3ac tag (not DMAed) */
 259
 260 /* Ethertype field values */
 261 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 262 #define ETHERNET_IP_TYPE        0x0800  /* IP packets */
 263 #define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
 264
 265 /* Packet Header defines */
 266 #define IP_PROTOCOL_TCP    6
 267 #define IP_PROTOCOL_UDP    0x11
 268
 269 /* This defines the bits that are set in the Interrupt Mask
 270  * Set/Read Register.  Each bit is documented below:
 271  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 272  *   o RXSEQ  = Receive Sequence Error
 273  */
 274 #define POLL_IMS_ENABLE_MASK ( \
 275     E1000_IMS_RXDMT0 |         \
 276     E1000_IMS_RXSEQ)
 277
 278 /* This defines the bits that are set in the Interrupt Mask
 279  * Set/Read Register.  Each bit is documented below:
 280  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 281  *   o TXDW   = Transmit Descriptor Written Back
 282  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 283  *   o RXSEQ  = Receive Sequence Error
 284  *   o LSC    = Link Status Change
 285  */
 286 #define IMS_ENABLE_MASK ( \
 287     E1000_IMS_RXT0   |    \
 288     E1000_IMS_TXDW   |    \
 289     E1000_IMS_RXDMT0 |    \
 290     E1000_IMS_RXSEQ  |    \
 291     E1000_IMS_LSC)
 292
 293 /* The number of high/low register pairs in the RAR. The RAR (Receive Address
 294  * Registers) holds the directed and multicast addresses that we monitor. We
 295  * reserve one of these spots for our directed address, allowing us room for
 296  * E1000_RAR_ENTRIES - 1 multicast addresses.
 297  */
 298 #define E1000_RAR_ENTRIES 16
 299
 300 #define MIN_NUMBER_OF_DESCRIPTORS 8
 301 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
 302
 303 /* Receive Descriptor */
 304 struct e1000_rx_desc {
 305         uint64_t buffer_addr;   /* Address of the descriptor's data buffer */
 306         uint16_t length;        /* Length of data DMAed into data buffer */
 307         uint16_t csum;          /* Packet checksum */
 308         uint8_t status;         /* Descriptor status */
 309         uint8_t errors;         /* Descriptor Errors */
 310         uint16_t special;
 311 };
 312
 313 /* Receive Decriptor bit definitions */
 314 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 315 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 316 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 317 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 318 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 319 #define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 320 #define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 321 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 322 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 323 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 324 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 325 #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
 326 #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
 327 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 328 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 329 #define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 330 #define E1000_RXD_SPC_PRI_SHIFT 0x000D  /* Priority is in upper 3 of 16 */
 331 #define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 332 #define E1000_RXD_SPC_CFI_SHIFT 0x000C  /* CFI is bit 12 */
 333
 334 /* mask to determine if packets should be dropped due to frame errors */
 335 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 336     E1000_RXD_ERR_CE  |                \
 337     E1000_RXD_ERR_SE  |                \
 338     E1000_RXD_ERR_SEQ |                \
 339     E1000_RXD_ERR_CXE |                \
 340     E1000_RXD_ERR_RXE)
 341
 342 /* Transmit Descriptor */
 343 struct e1000_tx_desc {
 344         uint64_t buffer_addr;   /* Address of the descriptor's data buffer */
 345         union {
 346                 uint32_t data;
 347                 struct {
 348                         uint16_t length;        /* Data buffer length */
 349                         uint8_t cso;    /* Checksum offset */
 350                         uint8_t cmd;    /* Descriptor control */
 351                 } flags;
 352         } lower;
 353         union {
 354                 uint32_t data;
 355                 struct {
 356                         uint8_t status; /* Descriptor status */
 357                         uint8_t css;    /* Checksum start */
 358                         uint16_t special;
 359                 } fields;
 360         } upper;
 361 };
 362
 363 /* Transmit Descriptor bit definitions */
 364 #define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
 365 #define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
 366 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 367 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 368 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 369 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 370 #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 371 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 372 #define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
 373 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 374 #define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 375 #define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
 376 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 377 #define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
 378 #define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
 379 #define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
 380 #define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
 381 #define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
 382 #define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
 383 #define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 384
 385 /* Offload Context Descriptor */
 386 struct e1000_context_desc {
 387         union {
 388                 uint32_t ip_config;
 389                 struct {
 390                         uint8_t ipcss;  /* IP checksum start */
 391                         uint8_t ipcso;  /* IP checksum offset */
 392                         uint16_t ipcse; /* IP checksum end */
 393                 } ip_fields;
 394         } lower_setup;
 395         union {
 396                 uint32_t tcp_config;
 397                 struct {
 398                         uint8_t tucss;  /* TCP checksum start */
 399                         uint8_t tucso;  /* TCP checksum offset */
 400                         uint16_t tucse; /* TCP checksum end */
 401                 } tcp_fields;
 402         } upper_setup;
 403         uint32_t cmd_and_length;        /* */
 404         union {
 405                 uint32_t data;
 406                 struct {
 407                         uint8_t status; /* Descriptor status */
 408                         uint8_t hdr_len;        /* Header length */
 409                         uint16_t mss;   /* Maximum segment size */
 410                 } fields;
 411         } tcp_seg_setup;
 412 };
 413
 414 /* Offload data descriptor */
 415 struct e1000_data_desc {
 416         uint64_t buffer_addr;   /* Address of the descriptor's buffer address */
 417         union {
 418                 uint32_t data;
 419                 struct {
 420                         uint16_t length;        /* Data buffer length */
 421                         uint8_t typ_len_ext;    /* */
 422                         uint8_t cmd;    /* */
 423                 } flags;
 424         } lower;
 425         union {
 426                 uint32_t data;
 427                 struct {
 428                         uint8_t status; /* Descriptor status */
 429                         uint8_t popts;  /* Packet Options */
 430                         uint16_t special;       /* */
 431                 } fields;
 432         } upper;
 433 };
 434
 435 /* Filters */
 436 #define E1000_NUM_UNICAST          16   /* Unicast filter entries */
 437 #define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
 438 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 439
 440 /* Receive Address Register */
 441 struct e1000_rar {
 442         volatile uint32_t low;  /* receive address low */
 443         volatile uint32_t high; /* receive address high */
 444 };
 445
 446 /* The number of entries in the Multicast Table Array (MTA). */
 447 #define E1000_NUM_MTA_REGISTERS 128
 448
 449 /* IPv4 Address Table Entry */
 450 struct e1000_ipv4_at_entry {
 451         volatile uint32_t ipv4_addr;    /* IP Address (RW) */
 452         volatile uint32_t reserved;
 453 };
 454
 455 /* Four wakeup IP addresses are supported */
 456 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
 457 #define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
 458 #define E1000_IP6AT_SIZE                  1
 459
 460 /* IPv6 Address Table Entry */
 461 struct e1000_ipv6_at_entry {
 462         volatile uint8_t ipv6_addr[16];
 463 };
 464
 465 /* Flexible Filter Length Table Entry */
 466 struct e1000_fflt_entry {
 467         volatile uint32_t length;       /* Flexible Filter Length (RW) */
 468         volatile uint32_t reserved;
 469 };
 470
 471 /* Flexible Filter Mask Table Entry */
 472 struct e1000_ffmt_entry {
 473         volatile uint32_t mask; /* Flexible Filter Mask (RW) */
 474         volatile uint32_t reserved;
 475 };
 476
 477 /* Flexible Filter Value Table Entry */
 478 struct e1000_ffvt_entry {
 479         volatile uint32_t value;        /* Flexible Filter Value (RW) */
 480         volatile uint32_t reserved;
 481 };
 482
 483 /* Four Flexible Filters are supported */
 484 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
 485
 486 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 487 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 488
 489 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 490 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 491 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 492
 493 /* Register Set. (82543, 82544)
 494  *
 495  * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
 496  * These registers are physically located on the NIC, but are mapped into the
 497  * host memory address space.
 498  *
 499  * RW - register is both readable and writable
 500  * RO - register is read only
 501  * WO - register is write only
 502  * R/clr - register is read only and is cleared when read
 503  * A - register array
 504  */
 505 #define E1000_CTRL     0x00000  /* Device Control - RW */
 506 #define E1000_STATUS   0x00008  /* Device Status - RO */
 507 #define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
 508 #define E1000_EERD     0x00014  /* EEPROM Read - RW */
 509 #define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
 510 #define E1000_MDIC     0x00020  /* MDI Control - RW */
 511 #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
 512 #define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
 513 #define E1000_FCT      0x00030  /* Flow Control Type - RW */
 514 #define E1000_VET      0x00038  /* VLAN Ether Type - RW */
 515 #define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
 516 #define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
 517 #define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
 518 #define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
 519 #define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
 520 #define E1000_RCTL     0x00100  /* RX Control - RW */
 521 #define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
 522 #define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
 523 #define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
 524 #define E1000_TCTL     0x00400  /* TX Control - RW */
 525 #define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
 526 #define E1000_TBT      0x00448  /* TX Burst Timer - RW */
 527 #define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
 528 #define E1000_LEDCTL   0x00E00  /* LED Control - RW */
 529 #define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
 530 #define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
 531 #define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
 532 #define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
 533 #define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
 534 #define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
 535 #define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
 536 #define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
 537 #define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
 538 #define E1000_RXDCTL   0x02828  /* RX Descriptor Control - RW */
 539 #define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
 540 #define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
 541 #define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
 542 #define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
 543 #define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
 544 #define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
 545 #define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
 546 #define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
 547 #define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
 548 #define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
 549 #define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
 550 #define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
 551 #define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
 552 #define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
 553 #define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
 554 #define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
 555 #define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
 556 #define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
 557 #define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
 558 #define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
 559 #define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
 560 #define E1000_COLC     0x04028  /* Collision Count - R/clr */
 561 #define E1000_DC       0x04030  /* Defer Count - R/clr */
 562 #define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
 563 #define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
 564 #define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
 565 #define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
 566 #define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
 567 #define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
 568 #define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
 569 #define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
 570 #define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
 571 #define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
 572 #define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
 573 #define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
 574 #define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
 575 #define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
 576 #define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
 577 #define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
 578 #define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
 579 #define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
 580 #define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
 581 #define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
 582 #define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
 583 #define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
 584 #define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
 585 #define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
 586 #define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
 587 #define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
 588 #define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
 589 #define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
 590 #define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
 591 #define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
 592 #define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
 593 #define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
 594 #define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
 595 #define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
 596 #define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
 597 #define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
 598 #define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
 599 #define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
 600 #define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
 601 #define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
 602 #define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
 603 #define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
 604 #define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
 605 #define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
 606 #define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
 607 #define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
 608 #define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
 609 #define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
 610 #define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
 611 #define E1000_RA       0x05400  /* Receive Address - RW Array */
 612 #define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
 613 #define E1000_WUC      0x05800  /* Wakeup Control - RW */
 614 #define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
 615 #define E1000_WUS      0x05810  /* Wakeup Status - RO */
 616 #define E1000_MANC     0x05820  /* Management Control - RW */
 617 #define E1000_IPAV     0x05838  /* IP Address Valid - RW */
 618 #define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
 619 #define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
 620 #define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
 621 #define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
 622 #define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
 623 #define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
 624 #define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
 625
 626 /* Register Set (82542)
 627  *
 628  * Some of the 82542 registers are located at different offsets than they are
 629  * in more current versions of the 8254x. Despite the difference in location,
 630  * the registers function in the same manner.
 631  */
 632 #define E1000_82542_CTRL     E1000_CTRL
 633 #define E1000_82542_STATUS   E1000_STATUS
 634 #define E1000_82542_EECD     E1000_EECD
 635 #define E1000_82542_EERD     E1000_EERD
 636 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
 637 #define E1000_82542_MDIC     E1000_MDIC
 638 #define E1000_82542_FCAL     E1000_FCAL
 639 #define E1000_82542_FCAH     E1000_FCAH
 640 #define E1000_82542_FCT      E1000_FCT
 641 #define E1000_82542_VET      E1000_VET
 642 #define E1000_82542_RA       0x00040
 643 #define E1000_82542_ICR      E1000_ICR
 644 #define E1000_82542_ITR      E1000_ITR
 645 #define E1000_82542_ICS      E1000_ICS
 646 #define E1000_82542_IMS      E1000_IMS
 647 #define E1000_82542_IMC      E1000_IMC
 648 #define E1000_82542_RCTL     E1000_RCTL
 649 #define E1000_82542_RDTR     0x00108
 650 #define E1000_82542_RDBAL    0x00110
 651 #define E1000_82542_RDBAH    0x00114
 652 #define E1000_82542_RDLEN    0x00118
 653 #define E1000_82542_RDH      0x00120
 654 #define E1000_82542_RDT      0x00128
 655 #define E1000_82542_FCRTH    0x00160
 656 #define E1000_82542_FCRTL    0x00168
 657 #define E1000_82542_FCTTV    E1000_FCTTV
 658 #define E1000_82542_TXCW     E1000_TXCW
 659 #define E1000_82542_RXCW     E1000_RXCW
 660 #define E1000_82542_MTA      0x00200
 661 #define E1000_82542_TCTL     E1000_TCTL
 662 #define E1000_82542_TIPG     E1000_TIPG
 663 #define E1000_82542_TDBAL    0x00420
 664 #define E1000_82542_TDBAH    0x00424
 665 #define E1000_82542_TDLEN    0x00428
 666 #define E1000_82542_TDH      0x00430
 667 #define E1000_82542_TDT      0x00438
 668 #define E1000_82542_TIDV     0x00440
 669 #define E1000_82542_TBT      E1000_TBT
 670 #define E1000_82542_AIT      E1000_AIT
 671 #define E1000_82542_VFTA     0x00600
 672 #define E1000_82542_LEDCTL   E1000_LEDCTL
 673 #define E1000_82542_PBA      E1000_PBA
 674 #define E1000_82542_RXDCTL   E1000_RXDCTL
 675 #define E1000_82542_RADV     E1000_RADV
 676 #define E1000_82542_RSRPD    E1000_RSRPD
 677 #define E1000_82542_TXDMAC   E1000_TXDMAC
 678 #define E1000_82542_TXDCTL   E1000_TXDCTL
 679 #define E1000_82542_TADV     E1000_TADV
 680 #define E1000_82542_TSPMT    E1000_TSPMT
 681 #define E1000_82542_CRCERRS  E1000_CRCERRS
 682 #define E1000_82542_ALGNERRC E1000_ALGNERRC
 683 #define E1000_82542_SYMERRS  E1000_SYMERRS
 684 #define E1000_82542_RXERRC   E1000_RXERRC
 685 #define E1000_82542_MPC      E1000_MPC
 686 #define E1000_82542_SCC      E1000_SCC
 687 #define E1000_82542_ECOL     E1000_ECOL
 688 #define E1000_82542_MCC      E1000_MCC
 689 #define E1000_82542_LATECOL  E1000_LATECOL
 690 #define E1000_82542_COLC     E1000_COLC
 691 #define E1000_82542_DC       E1000_DC
 692 #define E1000_82542_TNCRS    E1000_TNCRS
 693 #define E1000_82542_SEC      E1000_SEC
 694 #define E1000_82542_CEXTERR  E1000_CEXTERR
 695 #define E1000_82542_RLEC     E1000_RLEC
 696 #define E1000_82542_XONRXC   E1000_XONRXC
 697 #define E1000_82542_XONTXC   E1000_XONTXC
 698 #define E1000_82542_XOFFRXC  E1000_XOFFRXC
 699 #define E1000_82542_XOFFTXC  E1000_XOFFTXC
 700 #define E1000_82542_FCRUC    E1000_FCRUC
 701 #define E1000_82542_PRC64    E1000_PRC64
 702 #define E1000_82542_PRC127   E1000_PRC127
 703 #define E1000_82542_PRC255   E1000_PRC255
 704 #define E1000_82542_PRC511   E1000_PRC511
 705 #define E1000_82542_PRC1023  E1000_PRC1023
 706 #define E1000_82542_PRC1522  E1000_PRC1522
 707 #define E1000_82542_GPRC     E1000_GPRC
 708 #define E1000_82542_BPRC     E1000_BPRC
 709 #define E1000_82542_MPRC     E1000_MPRC
 710 #define E1000_82542_GPTC     E1000_GPTC
 711 #define E1000_82542_GORCL    E1000_GORCL
 712 #define E1000_82542_GORCH    E1000_GORCH
 713 #define E1000_82542_GOTCL    E1000_GOTCL
 714 #define E1000_82542_GOTCH    E1000_GOTCH
 715 #define E1000_82542_RNBC     E1000_RNBC
 716 #define E1000_82542_RUC      E1000_RUC
 717 #define E1000_82542_RFC      E1000_RFC
 718 #define E1000_82542_ROC      E1000_ROC
 719 #define E1000_82542_RJC      E1000_RJC
 720 #define E1000_82542_MGTPRC   E1000_MGTPRC
 721 #define E1000_82542_MGTPDC   E1000_MGTPDC
 722 #define E1000_82542_MGTPTC   E1000_MGTPTC
 723 #define E1000_82542_TORL     E1000_TORL
 724 #define E1000_82542_TORH     E1000_TORH
 725 #define E1000_82542_TOTL     E1000_TOTL
 726 #define E1000_82542_TOTH     E1000_TOTH
 727 #define E1000_82542_TPR      E1000_TPR
 728 #define E1000_82542_TPT      E1000_TPT
 729 #define E1000_82542_PTC64    E1000_PTC64
 730 #define E1000_82542_PTC127   E1000_PTC127
 731 #define E1000_82542_PTC255   E1000_PTC255
 732 #define E1000_82542_PTC511   E1000_PTC511
 733 #define E1000_82542_PTC1023  E1000_PTC1023
 734 #define E1000_82542_PTC1522  E1000_PTC1522
 735 #define E1000_82542_MPTC     E1000_MPTC
 736 #define E1000_82542_BPTC     E1000_BPTC
 737 #define E1000_82542_TSCTC    E1000_TSCTC
 738 #define E1000_82542_TSCTFC   E1000_TSCTFC
 739 #define E1000_82542_RXCSUM   E1000_RXCSUM
 740 #define E1000_82542_WUC      E1000_WUC
 741 #define E1000_82542_WUFC     E1000_WUFC
 742 #define E1000_82542_WUS      E1000_WUS
 743 #define E1000_82542_MANC     E1000_MANC
 744 #define E1000_82542_IPAV     E1000_IPAV
 745 #define E1000_82542_IP4AT    E1000_IP4AT
 746 #define E1000_82542_IP6AT    E1000_IP6AT
 747 #define E1000_82542_WUPL     E1000_WUPL
 748 #define E1000_82542_WUPM     E1000_WUPM
 749 #define E1000_82542_FFLT     E1000_FFLT
 750 #define E1000_82542_FFMT     E1000_FFMT
 751 #define E1000_82542_FFVT     E1000_FFVT
 752
 753 /* Statistics counters collected by the MAC */
 754 struct e1000_hw_stats {
 755         uint64_t crcerrs;
 756         uint64_t algnerrc;
 757         uint64_t symerrs;
 758         uint64_t rxerrc;
 759         uint64_t mpc;
 760         uint64_t scc;
 761         uint64_t ecol;
 762         uint64_t mcc;
 763         uint64_t latecol;
 764         uint64_t colc;
 765         uint64_t dc;
 766         uint64_t tncrs;
 767         uint64_t sec;
 768         uint64_t cexterr;
 769         uint64_t rlec;
 770         uint64_t xonrxc;
 771         uint64_t xontxc;
 772         uint64_t xoffrxc;
 773         uint64_t xofftxc;
 774         uint64_t fcruc;
 775         uint64_t prc64;
 776         uint64_t prc127;
 777         uint64_t prc255;
 778         uint64_t prc511;
 779         uint64_t prc1023;
 780         uint64_t prc1522;
 781         uint64_t gprc;
 782         uint64_t bprc;
 783         uint64_t mprc;
 784         uint64_t gptc;
 785         uint64_t gorcl;
 786         uint64_t gorch;
 787         uint64_t gotcl;
 788         uint64_t gotch;
 789         uint64_t rnbc;
 790         uint64_t ruc;
 791         uint64_t rfc;
 792         uint64_t roc;
 793         uint64_t rjc;
 794         uint64_t mgprc;
 795         uint64_t mgpdc;
 796         uint64_t mgptc;
 797         uint64_t torl;
 798         uint64_t torh;
 799         uint64_t totl;
 800         uint64_t toth;
 801         uint64_t tpr;
 802         uint64_t tpt;
 803         uint64_t ptc64;
 804         uint64_t ptc127;
 805         uint64_t ptc255;
 806         uint64_t ptc511;
 807         uint64_t ptc1023;
 808         uint64_t ptc1522;
 809         uint64_t mptc;
 810         uint64_t bptc;
 811         uint64_t tsctc;
 812         uint64_t tsctfc;
 813 };
 814
 815 /* Structure containing variables used by the shared code (e1000_hw.c) */
 816 struct e1000_hw {
 817         pci_dev_t pdev;
 818         uint8_t *hw_addr;
 819         e1000_mac_type mac_type;
 820         e1000_phy_type phy_type;
 821         uint32_t phy_init_script;
 822         e1000_media_type media_type;
 823         e1000_lan_loc lan_loc;
 824         e1000_fc_type fc;
 825 #if 0
 826         e1000_bus_speed bus_speed;
 827         e1000_bus_width bus_width;
 828         e1000_bus_type bus_type;
 829         uint32_t io_base;
 830 #endif
 831         uint32_t phy_id;
 832         uint32_t phy_addr;
 833         uint32_t original_fc;
 834         uint32_t txcw;
 835         uint32_t autoneg_failed;
 836 #if 0
 837         uint32_t max_frame_size;
 838         uint32_t min_frame_size;
 839         uint32_t mc_filter_type;
 840         uint32_t num_mc_addrs;
 841         uint32_t collision_delta;
 842         uint32_t tx_packet_delta;
 843         uint32_t ledctl_default;
 844         uint32_t ledctl_mode1;
 845         uint32_t ledctl_mode2;
 846 #endif
 847         uint16_t autoneg_advertised;
 848         uint16_t pci_cmd_word;
 849         uint16_t fc_high_water;
 850         uint16_t fc_low_water;
 851         uint16_t fc_pause_time;
 852 #if 0
 853         uint16_t current_ifs_val;
 854         uint16_t ifs_min_val;
 855         uint16_t ifs_max_val;
 856         uint16_t ifs_step_size;
 857         uint16_t ifs_ratio;
 858 #endif
 859         uint16_t device_id;
 860         uint16_t vendor_id;
 861         uint16_t subsystem_id;
 862         uint16_t subsystem_vendor_id;
 863         uint8_t revision_id;
 864 #if 0
 865         uint8_t autoneg;
 866         uint8_t mdix;
 867         uint8_t forced_speed_duplex;
 868         uint8_t wait_autoneg_complete;
 869         uint8_t dma_fairness;
 870 #endif
 871 #if 0
 872         uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
 873         boolean_t disable_polarity_correction;
 874 #endif
 875         boolean_t get_link_status;
 876         boolean_t tbi_compatibility_en;
 877         boolean_t tbi_compatibility_on;
 878         boolean_t fc_send_xon;
 879         boolean_t report_tx_early;
 880 #if 0
 881         boolean_t adaptive_ifs;
 882         boolean_t ifs_params_forced;
 883         boolean_t in_ifs_mode;
 884 #endif
 885 };
 886
 887 #define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
 888 #define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
 889
 890 /* Register Bit Masks */
 891 /* Device Control */
 892 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 893 #define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
 894 #define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
 895 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 896 #define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
 897 #define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
 898 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 899 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 900 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 901 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 902 #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
 903 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 904 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 905 #define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
 906 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 907 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 908 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 909 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 910 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 911 #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
 912 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 913 #define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
 914 #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
 915 #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
 916 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 917 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 918 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 919 #define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
 920 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 921 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 922
 923 /* Device Status */
 924 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 925 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 926 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 927 #define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
 928 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 929 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 930 #define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
 931 #define E1000_STATUS_SPEED_MASK 0x000000C0
 932 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 933 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 934 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 935 #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
 936 #define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
 937 #define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
 938 #define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
 939 #define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
 940 #define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
 941
 942 /* Constants used to intrepret the masked PCI-X bus speed. */
 943 #define E1000_STATUS_PCIX_SPEED_66  0x00000000  /* PCI-X bus speed  50-66 MHz */
 944 #define E1000_STATUS_PCIX_SPEED_100 0x00004000  /* PCI-X bus speed  66-100 MHz */
 945 #define E1000_STATUS_PCIX_SPEED_133 0x00008000  /* PCI-X bus speed 100-133 MHz */
 946
 947 /* EEPROM/Flash Control */
 948 #define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
 949 #define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
 950 #define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
 951 #define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
 952 #define E1000_EECD_FWE_MASK  0x00000030
 953 #define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
 954 #define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
 955 #define E1000_EECD_FWE_SHIFT 4
 956 #define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
 957 #define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
 958 #define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
 959 #define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
 960
 961 /* EEPROM Read */
 962 #define E1000_EERD_START      0x00000001        /* Start Read */
 963 #define E1000_EERD_DONE       0x00000010        /* Read Done */
 964 #define E1000_EERD_ADDR_SHIFT 8
 965 #define E1000_EERD_ADDR_MASK  0x0000FF00        /* Read Address */
 966 #define E1000_EERD_DATA_SHIFT 16
 967 #define E1000_EERD_DATA_MASK  0xFFFF0000        /* Read Data */
 968
 969 /* Extended Device Control */
 970 #define E1000_CTRL_EXT_GPI0_EN   0x00000001     /* Maps SDP4 to GPI0 */
 971 #define E1000_CTRL_EXT_GPI1_EN   0x00000002     /* Maps SDP5 to GPI1 */
 972 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
 973 #define E1000_CTRL_EXT_GPI2_EN   0x00000004     /* Maps SDP6 to GPI2 */
 974 #define E1000_CTRL_EXT_GPI3_EN   0x00000008     /* Maps SDP7 to GPI3 */
 975 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010     /* Value of SW Defineable Pin 4 */
 976 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020     /* Value of SW Defineable Pin 5 */
 977 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
 978 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040     /* Value of SW Defineable Pin 6 */
 979 #define E1000_CTRL_EXT_SWDPIN6   0x00000040     /* SWDPIN 6 value */
 980 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080     /* Value of SW Defineable Pin 7 */
 981 #define E1000_CTRL_EXT_SWDPIN7   0x00000080     /* SWDPIN 7 value */
 982 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100     /* Direction of SDP4 0=in 1=out */
 983 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200     /* Direction of SDP5 0=in 1=out */
 984 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400     /* Direction of SDP6 0=in 1=out */
 985 #define E1000_CTRL_EXT_SWDPIO6   0x00000400     /* SWDPIN 6 Input or output */
 986 #define E1000_CTRL_EXT_SDP7_DIR  0x00000800     /* Direction of SDP7 0=in 1=out */
 987 #define E1000_CTRL_EXT_SWDPIO7   0x00000800     /* SWDPIN 7 Input or output */
 988 #define E1000_CTRL_EXT_ASDCHK    0x00001000     /* Initiate an ASD sequence */
 989 #define E1000_CTRL_EXT_EE_RST    0x00002000     /* Reinitialize from EEPROM */
 990 #define E1000_CTRL_EXT_IPS       0x00004000     /* Invert Power State */
 991 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000     /* Speed Select Bypass */
 992 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 993 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 994 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
 995 #define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
 996 #define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
 997 #define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
 998 #define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
 999 #define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
1000
1001 /* MDI Control */
1002 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1003 #define E1000_MDIC_REG_MASK  0x001F0000
1004 #define E1000_MDIC_REG_SHIFT 16
1005 #define E1000_MDIC_PHY_MASK  0x03E00000
1006 #define E1000_MDIC_PHY_SHIFT 21
1007 #define E1000_MDIC_OP_WRITE  0x04000000
1008 #define E1000_MDIC_OP_READ   0x08000000
1009 #define E1000_MDIC_READY     0x10000000
1010 #define E1000_MDIC_INT_EN    0x20000000
1011 #define E1000_MDIC_ERROR     0x40000000
1012
1013 /* LED Control */
1014 #define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
1015 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1016 #define E1000_LEDCTL_LED0_IVRT       0x00000040
1017 #define E1000_LEDCTL_LED0_BLINK      0x00000080
1018 #define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
1019 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1020 #define E1000_LEDCTL_LED1_IVRT       0x00004000
1021 #define E1000_LEDCTL_LED1_BLINK      0x00008000
1022 #define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
1023 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1024 #define E1000_LEDCTL_LED2_IVRT       0x00400000
1025 #define E1000_LEDCTL_LED2_BLINK      0x00800000
1026 #define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
1027 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1028 #define E1000_LEDCTL_LED3_IVRT       0x40000000
1029 #define E1000_LEDCTL_LED3_BLINK      0x80000000
1030
1031 #define E1000_LEDCTL_MODE_LINK_10_1000  0x0
1032 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1033 #define E1000_LEDCTL_MODE_LINK_UP       0x2
1034 #define E1000_LEDCTL_MODE_ACTIVITY      0x3
1035 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1036 #define E1000_LEDCTL_MODE_LINK_10       0x5
1037 #define E1000_LEDCTL_MODE_LINK_100      0x6
1038 #define E1000_LEDCTL_MODE_LINK_1000     0x7
1039 #define E1000_LEDCTL_MODE_PCIX_MODE     0x8
1040 #define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
1041 #define E1000_LEDCTL_MODE_COLLISION     0xA
1042 #define E1000_LEDCTL_MODE_BUS_SPEED     0xB
1043 #define E1000_LEDCTL_MODE_BUS_SIZE      0xC
1044 #define E1000_LEDCTL_MODE_PAUSED        0xD
1045 #define E1000_LEDCTL_MODE_LED_ON        0xE
1046 #define E1000_LEDCTL_MODE_LED_OFF       0xF
1047
1048 /* Receive Address */
1049 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
1050
1051 /* Interrupt Cause Read */
1052 #define E1000_ICR_TXDW    0x00000001    /* Transmit desc written back */
1053 #define E1000_ICR_TXQE    0x00000002    /* Transmit Queue empty */
1054 #define E1000_ICR_LSC     0x00000004    /* Link Status Change */
1055 #define E1000_ICR_RXSEQ   0x00000008    /* rx sequence error */
1056 #define E1000_ICR_RXDMT0  0x00000010    /* rx desc min. threshold (0) */
1057 #define E1000_ICR_RXO     0x00000040    /* rx overrun */
1058 #define E1000_ICR_RXT0    0x00000080    /* rx timer intr (ring 0) */
1059 #define E1000_ICR_MDAC    0x00000200    /* MDIO access complete */
1060 #define E1000_ICR_RXCFG   0x00000400    /* RX /c/ ordered set */
1061 #define E1000_ICR_GPI_EN0 0x00000800    /* GP Int 0 */
1062 #define E1000_ICR_GPI_EN1 0x00001000    /* GP Int 1 */
1063 #define E1000_ICR_GPI_EN2 0x00002000    /* GP Int 2 */
1064 #define E1000_ICR_GPI_EN3 0x00004000    /* GP Int 3 */
1065 #define E1000_ICR_TXD_LOW 0x00008000
1066 #define E1000_ICR_SRPD    0x00010000
1067
1068 /* Interrupt Cause Set */
1069 #define E1000_ICS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1070 #define E1000_ICS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1071 #define E1000_ICS_LSC     E1000_ICR_LSC /* Link Status Change */
1072 #define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1073 #define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1074 #define E1000_ICS_RXO     E1000_ICR_RXO /* rx overrun */
1075 #define E1000_ICS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1076 #define E1000_ICS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1077 #define E1000_ICS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1078 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1079 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1080 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1081 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1082 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1083 #define E1000_ICS_SRPD    E1000_ICR_SRPD
1084
1085 /* Interrupt Mask Set */
1086 #define E1000_IMS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1087 #define E1000_IMS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1088 #define E1000_IMS_LSC     E1000_ICR_LSC /* Link Status Change */
1089 #define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1090 #define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1091 #define E1000_IMS_RXO     E1000_ICR_RXO /* rx overrun */
1092 #define E1000_IMS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1093 #define E1000_IMS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1094 #define E1000_IMS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1095 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1096 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1097 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1098 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1099 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1100 #define E1000_IMS_SRPD    E1000_ICR_SRPD
1101
1102 /* Interrupt Mask Clear */
1103 #define E1000_IMC_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1104 #define E1000_IMC_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1105 #define E1000_IMC_LSC     E1000_ICR_LSC /* Link Status Change */
1106 #define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1107 #define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1108 #define E1000_IMC_RXO     E1000_ICR_RXO /* rx overrun */
1109 #define E1000_IMC_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1110 #define E1000_IMC_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1111 #define E1000_IMC_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1112 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1113 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1114 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1115 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1116 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1117 #define E1000_IMC_SRPD    E1000_ICR_SRPD
1118
1119 /* Receive Control */
1120 #define E1000_RCTL_RST          0x00000001      /* Software reset */
1121 #define E1000_RCTL_EN           0x00000002      /* enable */
1122 #define E1000_RCTL_SBP          0x00000004      /* store bad packet */
1123 #define E1000_RCTL_UPE          0x00000008      /* unicast promiscuous enable */
1124 #define E1000_RCTL_MPE          0x00000010      /* multicast promiscuous enab */
1125 #define E1000_RCTL_LPE          0x00000020      /* long packet enable */
1126 #define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
1127 #define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
1128 #define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
1129 #define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
1130 #define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min threshold size */
1131 #define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min threshold size */
1132 #define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min threshold size */
1133 #define E1000_RCTL_MO_SHIFT     12      /* multicast offset shift */
1134 #define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
1135 #define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
1136 #define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
1137 #define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
1138 #define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
1139 #define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
1140 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1141 #define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
1142 #define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
1143 #define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
1144 #define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
1145 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1146 #define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
1147 #define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
1148 #define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
1149 #define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
1150 #define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
1151 #define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
1152 #define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
1153 #define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
1154 #define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
1155
1156 /* Receive Descriptor */
1157 #define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
1158 #define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
1159 #define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
1160 #define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
1161 #define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
1162
1163 /* Flow Control */
1164 #define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
1165 #define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
1166 #define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
1167 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
1168
1169 /* Receive Descriptor Control */
1170 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1171 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1172 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1173 #define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
1174
1175 /* Transmit Descriptor Control */
1176 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1177 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1178 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1179 #define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
1180 #define E1000_TXDCTL_LWTHRESH 0xFE000000        /* TXDCTL Low Threshold */
1181 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1182
1183 /* Transmit Configuration Word */
1184 #define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
1185 #define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
1186 #define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
1187 #define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
1188 #define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
1189 #define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
1190 #define E1000_TXCW_NP         0x00008000        /* TXCW next page */
1191 #define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
1192 #define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
1193 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
1194
1195 /* Receive Configuration Word */
1196 #define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
1197 #define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
1198 #define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
1199 #define E1000_RXCW_CC    0x10000000     /* Receive config change */
1200 #define E1000_RXCW_C     0x20000000     /* Receive config */
1201 #define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
1202 #define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
1203
1204 /* Transmit Control */
1205 #define E1000_TCTL_RST    0x00000001    /* software reset */
1206 #define E1000_TCTL_EN     0x00000002    /* enable tx */
1207 #define E1000_TCTL_BCE    0x00000004    /* busy check enable */
1208 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
1209 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
1210 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
1211 #define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
1212 #define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
1213 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
1214 #define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
1215
1216 /* Receive Checksum Control */
1217 #define E1000_RXCSUM_PCSS_MASK 0x000000FF       /* Packet Checksum Start */
1218 #define E1000_RXCSUM_IPOFL     0x00000100       /* IPv4 checksum offload */
1219 #define E1000_RXCSUM_TUOFL     0x00000200       /* TCP / UDP checksum offload */
1220 #define E1000_RXCSUM_IPV6OFL   0x00000400       /* IPv6 checksum offload */
1221
1222 /* Definitions for power management and wakeup registers */
1223 /* Wake Up Control */
1224 #define E1000_WUC_APME       0x00000001 /* APM Enable */
1225 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
1226 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1227 #define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
1228
1229 /* Wake Up Filter Control */
1230 #define E1000_WUFC_LNKC 0x00000001      /* Link Status Change Wakeup Enable */
1231 #define E1000_WUFC_MAG  0x00000002      /* Magic Packet Wakeup Enable */
1232 #define E1000_WUFC_EX   0x00000004      /* Directed Exact Wakeup Enable */
1233 #define E1000_WUFC_MC   0x00000008      /* Directed Multicast Wakeup Enable */
1234 #define E1000_WUFC_BC   0x00000010      /* Broadcast Wakeup Enable */
1235 #define E1000_WUFC_ARP  0x00000020      /* ARP Request Packet Wakeup Enable */
1236 #define E1000_WUFC_IPV4 0x00000040      /* Directed IPv4 Packet Wakeup Enable */
1237 #define E1000_WUFC_IPV6 0x00000080      /* Directed IPv6 Packet Wakeup Enable */
1238 #define E1000_WUFC_FLX0 0x00010000      /* Flexible Filter 0 Enable */
1239 #define E1000_WUFC_FLX1 0x00020000      /* Flexible Filter 1 Enable */
1240 #define E1000_WUFC_FLX2 0x00040000      /* Flexible Filter 2 Enable */
1241 #define E1000_WUFC_FLX3 0x00080000      /* Flexible Filter 3 Enable */
1242 #define E1000_WUFC_ALL_FILTERS 0x000F00FF       /* Mask for all wakeup filters */
1243 #define E1000_WUFC_FLX_OFFSET 16        /* Offset to the Flexible Filters bits */
1244 #define E1000_WUFC_FLX_FILTERS 0x000F0000       /* Mask for the 4 flexible filters */
1245
1246 /* Wake Up Status */
1247 #define E1000_WUS_LNKC 0x00000001       /* Link Status Changed */
1248 #define E1000_WUS_MAG  0x00000002       /* Magic Packet Received */
1249 #define E1000_WUS_EX   0x00000004       /* Directed Exact Received */
1250 #define E1000_WUS_MC   0x00000008       /* Directed Multicast Received */
1251 #define E1000_WUS_BC   0x00000010       /* Broadcast Received */
1252 #define E1000_WUS_ARP  0x00000020       /* ARP Request Packet Received */
1253 #define E1000_WUS_IPV4 0x00000040       /* Directed IPv4 Packet Wakeup Received */
1254 #define E1000_WUS_IPV6 0x00000080       /* Directed IPv6 Packet Wakeup Received */
1255 #define E1000_WUS_FLX0 0x00010000       /* Flexible Filter 0 Match */
1256 #define E1000_WUS_FLX1 0x00020000       /* Flexible Filter 1 Match */
1257 #define E1000_WUS_FLX2 0x00040000       /* Flexible Filter 2 Match */
1258 #define E1000_WUS_FLX3 0x00080000       /* Flexible Filter 3 Match */
1259 #define E1000_WUS_FLX_FILTERS 0x000F0000        /* Mask for the 4 flexible filters */
1260
1261 /* Management Control */
1262 #define E1000_MANC_SMBUS_EN      0x00000001     /* SMBus Enabled - RO */
1263 #define E1000_MANC_ASF_EN        0x00000002     /* ASF Enabled - RO */
1264 #define E1000_MANC_R_ON_FORCE    0x00000004     /* Reset on Force TCO - RO */
1265 #define E1000_MANC_RMCP_EN       0x00000100     /* Enable RCMP 026Fh Filtering */
1266 #define E1000_MANC_0298_EN       0x00000200     /* Enable RCMP 0298h Filtering */
1267 #define E1000_MANC_IPV4_EN       0x00000400     /* Enable IPv4 */
1268 #define E1000_MANC_IPV6_EN       0x00000800     /* Enable IPv6 */
1269 #define E1000_MANC_SNAP_EN       0x00001000     /* Accept LLC/SNAP */
1270 #define E1000_MANC_ARP_EN        0x00002000     /* Enable ARP Request Filtering */
1271 #define E1000_MANC_NEIGHBOR_EN   0x00004000     /* Enable Neighbor Discovery
1272                                                  * Filtering */
1273 #define E1000_MANC_TCO_RESET     0x00010000     /* TCO Reset Occurred */
1274 #define E1000_MANC_RCV_TCO_EN    0x00020000     /* Receive TCO Packets Enabled */
1275 #define E1000_MANC_REPORT_STATUS 0x00040000     /* Status Reporting Enabled */
1276 #define E1000_MANC_SMB_REQ       0x01000000     /* SMBus Request */
1277 #define E1000_MANC_SMB_GNT       0x02000000     /* SMBus Grant */
1278 #define E1000_MANC_SMB_CLK_IN    0x04000000     /* SMBus Clock In */
1279 #define E1000_MANC_SMB_DATA_IN   0x08000000     /* SMBus Data In */
1280 #define E1000_MANC_SMB_DATA_OUT  0x10000000     /* SMBus Data Out */
1281 #define E1000_MANC_SMB_CLK_OUT   0x20000000     /* SMBus Clock Out */
1282
1283 #define E1000_MANC_SMB_DATA_OUT_SHIFT  28       /* SMBus Data Out Shift */
1284 #define E1000_MANC_SMB_CLK_OUT_SHIFT   29       /* SMBus Clock Out Shift */
1285
1286 /* Wake Up Packet Length */
1287 #define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
1288
1289 #define E1000_MDALIGN          4096
1290
1291 /* EEPROM Commands */
1292 #define EEPROM_READ_OPCODE  0x6 /* EERPOM read opcode */
1293 #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
1294 #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
1295 #define EEPROM_EWEN_OPCODE  0x13        /* EERPOM erase/write enable */
1296 #define EEPROM_EWDS_OPCODE  0x10        /* EERPOM erast/write disable */
1297
1298 /* EEPROM Word Offsets */
1299 #define EEPROM_COMPAT              0x0003
1300 #define EEPROM_ID_LED_SETTINGS     0x0004
1301 #define EEPROM_INIT_CONTROL1_REG   0x000A
1302 #define EEPROM_INIT_CONTROL2_REG   0x000F
1303 #define EEPROM_FLASH_VERSION       0x0032
1304 #define EEPROM_CHECKSUM_REG        0x003F
1305
1306 /* Word definitions for ID LED Settings */
1307 #define ID_LED_RESERVED_0000 0x0000
1308 #define ID_LED_RESERVED_FFFF 0xFFFF
1309 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
1310                               (ID_LED_OFF1_OFF2 << 8) | \
1311                               (ID_LED_DEF1_DEF2 << 4) | \
1312                               (ID_LED_DEF1_DEF2))
1313 #define ID_LED_DEF1_DEF2     0x1
1314 #define ID_LED_DEF1_ON2      0x2
1315 #define ID_LED_DEF1_OFF2     0x3
1316 #define ID_LED_ON1_DEF2      0x4
1317 #define ID_LED_ON1_ON2       0x5
1318 #define ID_LED_ON1_OFF2      0x6
1319 #define ID_LED_OFF1_DEF2     0x7
1320 #define ID_LED_OFF1_ON2      0x8
1321 #define ID_LED_OFF1_OFF2     0x9
1322
1323 /* Mask bits for fields in Word 0x03 of the EEPROM */
1324 #define EEPROM_COMPAT_SERVER 0x0400
1325 #define EEPROM_COMPAT_CLIENT 0x0200
1326
1327 /* Mask bits for fields in Word 0x0a of the EEPROM */
1328 #define EEPROM_WORD0A_ILOS   0x0010
1329 #define EEPROM_WORD0A_SWDPIO 0x01E0
1330 #define EEPROM_WORD0A_LRST   0x0200
1331 #define EEPROM_WORD0A_FD     0x0400
1332 #define EEPROM_WORD0A_66MHZ  0x0800
1333
1334 /* Mask bits for fields in Word 0x0f of the EEPROM */
1335 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
1336 #define EEPROM_WORD0F_PAUSE      0x1000
1337 #define EEPROM_WORD0F_ASM_DIR    0x2000
1338 #define EEPROM_WORD0F_ANE        0x0800
1339 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1340
1341 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1342 #define EEPROM_SUM 0xBABA
1343
1344 /* EEPROM Map defines (WORD OFFSETS)*/
1345 #define EEPROM_NODE_ADDRESS_BYTE_0 0
1346 #define EEPROM_PBA_BYTE_1          8
1347
1348 /* EEPROM Map Sizes (Byte Counts) */
1349 #define PBA_SIZE 4
1350
1351 /* Collision related configuration parameters */
1352 #define E1000_COLLISION_THRESHOLD       16
1353 #define E1000_CT_SHIFT                  4
1354 #define E1000_COLLISION_DISTANCE        64
1355 #define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
1356 #define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
1357 #define E1000_GB_HDX_COLLISION_DISTANCE 512
1358 #define E1000_COLD_SHIFT                12
1359
1360 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1361 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
1362 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
1363
1364 /* Default values for the transmit IPG register */
1365 #define DEFAULT_82542_TIPG_IPGT        10
1366 #define DEFAULT_82543_TIPG_IPGT_FIBER  9
1367 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
1368
1369 #define E1000_TIPG_IPGT_MASK  0x000003FF
1370 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
1371 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
1372
1373 #define DEFAULT_82542_TIPG_IPGR1 2
1374 #define DEFAULT_82543_TIPG_IPGR1 8
1375 #define E1000_TIPG_IPGR1_SHIFT  10
1376
1377 #define DEFAULT_82542_TIPG_IPGR2 10
1378 #define DEFAULT_82543_TIPG_IPGR2 6
1379 #define E1000_TIPG_IPGR2_SHIFT  20
1380
1381 #define E1000_TXDMAC_DPP 0x00000001
1382
1383 /* Adaptive IFS defines */
1384 #define TX_THRESHOLD_START     8
1385 #define TX_THRESHOLD_INCREMENT 10
1386 #define TX_THRESHOLD_DECREMENT 1
1387 #define TX_THRESHOLD_STOP      190
1388 #define TX_THRESHOLD_DISABLE   0
1389 #define TX_THRESHOLD_TIMER_MS  10000
1390 #define MIN_NUM_XMITS          1000
1391 #define IFS_MAX                80
1392 #define IFS_STEP               10
1393 #define IFS_MIN                40
1394 #define IFS_RATIO              4
1395
1396 /* PBA constants */
1397 #define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
1398 #define E1000_PBA_24K 0x0018
1399 #define E1000_PBA_40K 0x0028
1400 #define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
1401
1402 /* Flow Control Constants */
1403 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
1404 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1405 #define FLOW_CONTROL_TYPE         0x8808
1406
1407 /* The historical defaults for the flow control values are given below. */
1408 #define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
1409 #define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
1410 #define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
1411
1412 /* Flow Control High-Watermark: 43464 bytes */
1413 #define E1000_FC_HIGH_THRESH 0xA9C8
1414 /* Flow Control Low-Watermark: 43456 bytes */
1415 #define E1000_FC_LOW_THRESH 0xA9C0
1416 /* Flow Control Pause Time: 858 usec */
1417 #define E1000_FC_PAUSE_TIME 0x0680
1418
1419 /* PCIX Config space */
1420 #define PCIX_COMMAND_REGISTER    0xE6
1421 #define PCIX_STATUS_REGISTER_LO  0xE8
1422 #define PCIX_STATUS_REGISTER_HI  0xEA
1423
1424 #define PCIX_COMMAND_MMRBC_MASK      0x000C
1425 #define PCIX_COMMAND_MMRBC_SHIFT     0x2
1426 #define PCIX_STATUS_HI_MMRBC_MASK    0x0060
1427 #define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
1428 #define PCIX_STATUS_HI_MMRBC_4K      0x3
1429 #define PCIX_STATUS_HI_MMRBC_2K      0x2
1430
1431 /* The number of bits that we need to shift right to move the "pause"
1432  * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
1433  * in the TXCW register
1434  */
1435 #define PAUSE_SHIFT 5
1436
1437 /* The number of bits that we need to shift left to move the "SWDPIO"
1438  * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
1439  * in the CTRL register
1440  */
1441 #define SWDPIO_SHIFT 17
1442
1443 /* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1444  * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1445  * Extended CTRL register.
1446  * in the CTRL register
1447  */
1448 #define SWDPIO__EXT_SHIFT 4
1449
1450 /* The number of bits that we need to shift left to move the "ILOS"
1451  * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
1452  * in the CTRL register
1453  */
1454 #define ILOS_SHIFT  3
1455
1456 #define RECEIVE_BUFFER_ALIGN_SIZE  (256)
1457
1458 /* The number of milliseconds we wait for auto-negotiation to complete */
1459 #define LINK_UP_TIMEOUT             500
1460
1461 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1462
1463 /* The carrier extension symbol, as received by the NIC. */
1464 #define CARRIER_EXTENSION   0x0F
1465
1466 /* TBI_ACCEPT macro definition:
1467  *
1468  * This macro requires:
1469  *      adapter = a pointer to struct e1000_hw
1470  *      status = the 8 bit status field of the RX descriptor with EOP set
1471  *      error = the 8 bit error field of the RX descriptor with EOP set
1472  *      length = the sum of all the length fields of the RX descriptors that
1473  *               make up the current frame
1474  *      last_byte = the last byte of the frame DMAed by the hardware
1475  *      max_frame_length = the maximum frame length we want to accept.
1476  *      min_frame_length = the minimum frame length we want to accept.
1477  *
1478  * This macro is a conditional that should be used in the interrupt
1479  * handler's Rx processing routine when RxErrors have been detected.
1480  *
1481  * Typical use:
1482  *  ...
1483  *  if (TBI_ACCEPT) {
1484  *      accept_frame = TRUE;
1485  *      e1000_tbi_adjust_stats(adapter, MacAddress);
1486  *      frame_length--;
1487  *  } else {
1488  *      accept_frame = FALSE;
1489  *  }
1490  *  ...
1491  */
1492
1493 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1494     ((adapter)->tbi_compatibility_on && \
1495      (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1496      ((last_byte) == CARRIER_EXTENSION) && \
1497      (((status) & E1000_RXD_STAT_VP) ? \
1498           (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1499            ((length) <= ((adapter)->max_frame_size + 1))) : \
1500           (((length) > (adapter)->min_frame_size) && \
1501            ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1502
1503 /* Structures, enums, and macros for the PHY */
1504
1505 /* Bit definitions for the Management Data IO (MDIO) and Management Data
1506  * Clock (MDC) pins in the Device Control Register.
1507  */
1508 #define E1000_CTRL_PHY_RESET_DIR        E1000_CTRL_SWDPIO0
1509 #define E1000_CTRL_PHY_RESET            E1000_CTRL_SWDPIN0
1510 #define E1000_CTRL_MDIO_DIR             E1000_CTRL_SWDPIO2
1511 #define E1000_CTRL_MDIO                 E1000_CTRL_SWDPIN2
1512 #define E1000_CTRL_MDC_DIR              E1000_CTRL_SWDPIO3
1513 #define E1000_CTRL_MDC                  E1000_CTRL_SWDPIN3
1514 #define E1000_CTRL_PHY_RESET_DIR4       E1000_CTRL_EXT_SDP4_DIR
1515 #define E1000_CTRL_PHY_RESET4           E1000_CTRL_EXT_SDP4_DATA
1516
1517 /* PHY 1000 MII Register/Bit Definitions */
1518 /* PHY Registers defined by IEEE */
1519 #define PHY_CTRL                        0x00    /* Control Register */
1520 #define PHY_STATUS                      0x01    /* Status Regiser */
1521 #define PHY_ID1                         0x02    /* Phy Id Reg (word 1) */
1522 #define PHY_ID2                         0x03    /* Phy Id Reg (word 2) */
1523 #define PHY_AUTONEG_ADV         0x04    /* Autoneg Advertisement */
1524 #define PHY_LP_ABILITY                  0x05    /* Link Partner Ability (Base Page) */
1525 #define PHY_AUTONEG_EXP         0x06    /* Autoneg Expansion Reg */
1526 #define PHY_NEXT_PAGE_TX                0x07    /* Next Page TX */
1527 #define PHY_LP_NEXT_PAGE                0x08    /* Link Partner Next Page */
1528 #define PHY_1000T_CTRL                  0x09    /* 1000Base-T Control Reg */
1529 #define PHY_1000T_STATUS                0x0A    /* 1000Base-T Status Reg */
1530 #define PHY_EXT_STATUS                  0x0F    /* Extended Status Reg */
1531
1532 /* M88E1000 Specific Registers */
1533 #define M88E1000_PHY_SPEC_CTRL          0x10    /* PHY Specific Control Register */
1534 #define M88E1000_PHY_SPEC_STATUS        0x11    /* PHY Specific Status Register */
1535 #define M88E1000_INT_ENABLE             0x12    /* Interrupt Enable Register */
1536 #define M88E1000_INT_STATUS             0x13    /* Interrupt Status Register */
1537 #define M88E1000_EXT_PHY_SPEC_CTRL      0x14    /* Extended PHY Specific Control */
1538 #define M88E1000_RX_ERR_CNTR            0x15    /* Receive Error Counter */
1539
1540 #define MAX_PHY_REG_ADDRESS             0x1F    /* 5 bit address bus (0-0x1F) */
1541
1542 /* IGP01E1000 specifics */
1543 #define IGP01E1000_IEEE_REGS_PAGE       0x0000
1544 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1545 #define IGP01E1000_IEEE_FORCE_GIGA      0x0140
1546
1547 /* IGP01E1000 Specific Registers */
1548 #define IGP01E1000_PHY_PORT_CONFIG      0x10 /* PHY Specific Port Config Register */
1549 #define IGP01E1000_PHY_PORT_STATUS      0x11 /* PHY Specific Status Register */
1550 #define IGP01E1000_PHY_PORT_CTRL        0x12 /* PHY Specific Control Register */
1551 #define IGP01E1000_PHY_LINK_HEALTH      0x13 /* PHY Link Health Register */
1552 #define IGP01E1000_GMII_FIFO            0x14 /* GMII FIFO Register */
1553 #define IGP01E1000_PHY_CHANNEL_QUALITY  0x15 /* PHY Channel Quality Register */
1554 #define IGP02E1000_PHY_POWER_MGMT       0x19
1555 #define IGP01E1000_PHY_PAGE_SELECT      0x1F /* PHY Page Select Core Register */
1556
1557 /* PHY Control Register */
1558 #define MII_CR_SPEED_SELECT_MSB         0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
1559 #define MII_CR_COLL_TEST_ENABLE         0x0080  /* Collision test enable */
1560 #define MII_CR_FULL_DUPLEX              0x0100  /* FDX =1, half duplex =0 */
1561 #define MII_CR_RESTART_AUTO_NEG         0x0200  /* Restart auto negotiation */
1562 #define MII_CR_ISOLATE                  0x0400  /* Isolate PHY from MII */
1563 #define MII_CR_POWER_DOWN               0x0800  /* Power down */
1564 #define MII_CR_AUTO_NEG_EN              0x1000  /* Auto Neg Enable */
1565 #define MII_CR_SPEED_SELECT_LSB         0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
1566 #define MII_CR_LOOPBACK                 0x4000  /* 0 = normal, 1 = loopback */
1567 #define MII_CR_RESET                    0x8000  /* 0 = normal, 1 = PHY reset */
1568
1569 /* PHY Status Register */
1570 #define MII_SR_EXTENDED_CAPS            0x0001  /* Extended register capabilities */
1571 #define MII_SR_JABBER_DETECT            0x0002  /* Jabber Detected */
1572 #define MII_SR_LINK_STATUS              0x0004  /* Link Status 1 = link */
1573 #define MII_SR_AUTONEG_CAPS             0x0008  /* Auto Neg Capable */
1574 #define MII_SR_REMOTE_FAULT             0x0010  /* Remote Fault Detect */
1575 #define MII_SR_AUTONEG_COMPLETE         0x0020  /* Auto Neg Complete */
1576 #define MII_SR_PREAMBLE_SUPPRESS        0x0040  /* Preamble may be suppressed */
1577 #define MII_SR_EXTENDED_STATUS          0x0100  /* Ext. status info in Reg 0x0F */
1578 #define MII_SR_100T2_HD_CAPS            0x0200  /* 100T2 Half Duplex Capable */
1579 #define MII_SR_100T2_FD_CAPS            0x0400  /* 100T2 Full Duplex Capable */
1580 #define MII_SR_10T_HD_CAPS              0x0800  /* 10T   Half Duplex Capable */
1581 #define MII_SR_10T_FD_CAPS              0x1000  /* 10T   Full Duplex Capable */
1582 #define MII_SR_100X_HD_CAPS             0x2000  /* 100X  Half Duplex Capable */
1583 #define MII_SR_100X_FD_CAPS             0x4000  /* 100X  Full Duplex Capable */
1584 #define MII_SR_100T4_CAPS               0x8000  /* 100T4 Capable */
1585
1586 /* Autoneg Advertisement Register */
1587 #define NWAY_AR_SELECTOR_FIELD          0x0001  /* indicates IEEE 802.3 CSMA/CD */
1588 #define NWAY_AR_10T_HD_CAPS             0x0020  /* 10T   Half Duplex Capable */
1589 #define NWAY_AR_10T_FD_CAPS             0x0040  /* 10T   Full Duplex Capable */
1590 #define NWAY_AR_100TX_HD_CAPS           0x0080  /* 100TX Half Duplex Capable */
1591 #define NWAY_AR_100TX_FD_CAPS           0x0100  /* 100TX Full Duplex Capable */
1592 #define NWAY_AR_100T4_CAPS              0x0200  /* 100T4 Capable */
1593 #define NWAY_AR_PAUSE                   0x0400  /* Pause operation desired */
1594 #define NWAY_AR_ASM_DIR         0x0800  /* Asymmetric Pause Direction bit */
1595 #define NWAY_AR_REMOTE_FAULT            0x2000  /* Remote Fault detected */
1596 #define NWAY_AR_NEXT_PAGE               0x8000  /* Next Page ability supported */
1597
1598 /* Link Partner Ability Register (Base Page) */
1599 #define NWAY_LPAR_SELECTOR_FIELD        0x0000  /* LP protocol selector field */
1600 #define NWAY_LPAR_10T_HD_CAPS           0x0020  /* LP is 10T   Half Duplex Capable */
1601 #define NWAY_LPAR_10T_FD_CAPS           0x0040  /* LP is 10T   Full Duplex Capable */
1602 #define NWAY_LPAR_100TX_HD_CAPS 0x0080  /* LP is 100TX Half Duplex Capable */
1603 #define NWAY_LPAR_100TX_FD_CAPS 0x0100  /* LP is 100TX Full Duplex Capable */
1604 #define NWAY_LPAR_100T4_CAPS            0x0200  /* LP is 100T4 Capable */
1605 #define NWAY_LPAR_PAUSE                 0x0400  /* LP Pause operation desired */
1606 #define NWAY_LPAR_ASM_DIR               0x0800  /* LP Asymmetric Pause Direction bit */
1607 #define NWAY_LPAR_REMOTE_FAULT          0x2000  /* LP has detected Remote Fault */
1608 #define NWAY_LPAR_ACKNOWLEDGE           0x4000  /* LP has rx'd link code word */
1609 #define NWAY_LPAR_NEXT_PAGE             0x8000  /* Next Page ability supported */
1610
1611 /* Autoneg Expansion Register */
1612 #define NWAY_ER_LP_NWAY_CAPS            0x0001  /* LP has Auto Neg Capability */
1613 #define NWAY_ER_PAGE_RXD                0x0002  /* LP is 10T   Half Duplex Capable */
1614 #define NWAY_ER_NEXT_PAGE_CAPS          0x0004  /* LP is 10T   Full Duplex Capable */
1615 #define NWAY_ER_LP_NEXT_PAGE_CAPS       0x0008  /* LP is 100TX Half Duplex Capable */
1616 #define NWAY_ER_PAR_DETECT_FAULT        0x0100  /* LP is 100TX Full Duplex Capable */
1617
1618 /* Next Page TX Register */
1619 #define NPTX_MSG_CODE_FIELD             0x0001  /* NP msg code or unformatted data */
1620 #define NPTX_TOGGLE                     0x0800  /* Toggles between exchanges
1621                                                  * of different NP
1622                                                  */
1623 #define NPTX_ACKNOWLDGE2                0x1000  /* 1 = will comply with msg
1624                                                  * 0 = cannot comply with msg
1625                                                  */
1626 #define NPTX_MSG_PAGE                   0x2000  /* formatted(1)/unformatted(0) pg */
1627 #define NPTX_NEXT_PAGE                  0x8000  /* 1 = addition NP will follow
1628                                                  * 0 = sending last NP
1629                                                  */
1630
1631 /* Link Partner Next Page Register */
1632 #define LP_RNPR_MSG_CODE_FIELD          0x0001  /* NP msg code or unformatted data */
1633 #define LP_RNPR_TOGGLE                  0x0800  /* Toggles between exchanges
1634                                                  * of different NP
1635                                                  */
1636 #define LP_RNPR_ACKNOWLDGE2             0x1000  /* 1 = will comply with msg
1637                                                  * 0 = cannot comply with msg
1638                                                  */
1639 #define LP_RNPR_MSG_PAGE                0x2000  /* formatted(1)/unformatted(0) pg */
1640 #define LP_RNPR_ACKNOWLDGE              0x4000  /* 1 = ACK / 0 = NO ACK */
1641 #define LP_RNPR_NEXT_PAGE               0x8000  /* 1 = addition NP will follow
1642                                                  * 0 = sending last NP
1643                                                  */
1644
1645 /* 1000BASE-T Control Register */
1646 #define CR_1000T_ASYM_PAUSE             0x0080  /* Advertise asymmetric pause bit */
1647 #define CR_1000T_HD_CAPS                0x0100  /* Advertise 1000T HD capability */
1648 #define CR_1000T_FD_CAPS                0x0200  /* Advertise 1000T FD capability  */
1649 #define CR_1000T_REPEATER_DTE           0x0400  /* 1=Repeater/switch device port */
1650                                                 /* 0=DTE device */
1651 #define CR_1000T_MS_VALUE               0x0800  /* 1=Configure PHY as Master */
1652                                                 /* 0=Configure PHY as Slave */
1653 #define CR_1000T_MS_ENABLE              0x1000  /* 1=Master/Slave manual config value */
1654                                                 /* 0=Automatic Master/Slave config */
1655 #define CR_1000T_TEST_MODE_NORMAL       0x0000  /* Normal Operation */
1656 #define CR_1000T_TEST_MODE_1            0x2000  /* Transmit Waveform test */
1657 #define CR_1000T_TEST_MODE_2            0x4000  /* Master Transmit Jitter test */
1658 #define CR_1000T_TEST_MODE_3            0x6000  /* Slave Transmit Jitter test */
1659 #define CR_1000T_TEST_MODE_4            0x8000  /* Transmitter Distortion test */
1660
1661 /* 1000BASE-T Status Register */
1662 #define SR_1000T_IDLE_ERROR_CNT 0x00FF  /* Num idle errors since last read */
1663 #define SR_1000T_ASYM_PAUSE_DIR 0x0100  /* LP asymmetric pause direction bit */
1664 #define SR_1000T_LP_HD_CAPS             0x0400  /* LP is 1000T HD capable */
1665 #define SR_1000T_LP_FD_CAPS             0x0800  /* LP is 1000T FD capable */
1666 #define SR_1000T_REMOTE_RX_STATUS       0x1000  /* Remote receiver OK */
1667 #define SR_1000T_LOCAL_RX_STATUS        0x2000  /* Local receiver OK */
1668 #define SR_1000T_MS_CONFIG_RES          0x4000  /* 1=Local TX is Master, 0=Slave */
1669 #define SR_1000T_MS_CONFIG_FAULT        0x8000  /* Master/Slave config fault */
1670 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1671 #define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
1672
1673 /* Extended Status Register */
1674 #define IEEE_ESR_1000T_HD_CAPS          0x1000  /* 1000T HD capable */
1675 #define IEEE_ESR_1000T_FD_CAPS          0x2000  /* 1000T FD capable */
1676 #define IEEE_ESR_1000X_HD_CAPS          0x4000  /* 1000X HD capable */
1677 #define IEEE_ESR_1000X_FD_CAPS          0x8000  /* 1000X FD capable */
1678
1679 #define PHY_TX_POLARITY_MASK            0x0100  /* register 10h bit 8 (polarity bit) */
1680 #define PHY_TX_NORMAL_POLARITY          0       /* register 10h bit 8 (normal polarity) */
1681
1682 #define AUTO_POLARITY_DISABLE           0x0010  /* register 11h bit 4 */
1683                                                 /* (0=enable, 1=disable) */
1684
1685 /* M88E1000 PHY Specific Control Register */
1686 #define M88E1000_PSCR_JABBER_DISABLE    0x0001  /* 1=Jabber Function disabled */
1687 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002  /* 1=Polarity Reversal enabled */
1688 #define M88E1000_PSCR_SQE_TEST          0x0004  /* 1=SQE Test enabled */
1689 #define M88E1000_PSCR_CLK125_DISABLE    0x0010  /* 1=CLK125 low,
1690                                                  * 0=CLK125 toggling
1691                                                  */
1692 #define M88E1000_PSCR_MDI_MANUAL_MODE   0x0000  /* MDI Crossover Mode bits 6:5 */
1693                                                 /* Manual MDI configuration */
1694 #define M88E1000_PSCR_MDIX_MANUAL_MODE  0x0020  /* Manual MDIX configuration */
1695 #define M88E1000_PSCR_AUTO_X_1000T      0x0040  /* 1000BASE-T: Auto crossover,
1696                                                  *  100BASE-TX/10BASE-T:
1697                                                  *  MDI Mode
1698                                                  */
1699 #define M88E1000_PSCR_AUTO_X_MODE       0x0060  /* Auto crossover enabled
1700                                                  * all speeds.
1701                                                  */
1702 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1703                                                 /* 1=Enable Extended 10BASE-T distance
1704                                                  * (Lower 10BASE-T RX Threshold)
1705                                                  * 0=Normal 10BASE-T RX Threshold */
1706 #define M88E1000_PSCR_MII_5BIT_ENABLE   0x0100
1707                                                 /* 1=5-Bit interface in 100BASE-TX
1708                                                  * 0=MII interface in 100BASE-TX */
1709 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200  /* 1=Scrambler disable */
1710 #define M88E1000_PSCR_FORCE_LINK_GOOD   0x0400  /* 1=Force link good */
1711 #define M88E1000_PSCR_ASSERT_CRS_ON_TX  0x0800  /* 1=Assert CRS on Transmit */
1712
1713 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
1714 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
1715 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1716
1717 /* M88E1000 PHY Specific Status Register */
1718 #define M88E1000_PSSR_JABBER            0x0001  /* 1=Jabber */
1719 #define M88E1000_PSSR_REV_POLARITY      0x0002  /* 1=Polarity reversed */
1720 #define M88E1000_PSSR_MDIX              0x0040  /* 1=MDIX; 0=MDI */
1721 #define M88E1000_PSSR_CABLE_LENGTH      0x0380  /* 0=<50M;1=50-80M;2=80-110M;
1722                                                  * 3=110-140M;4=>140M */
1723 #define M88E1000_PSSR_LINK              0x0400  /* 1=Link up, 0=Link down */
1724 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800  /* 1=Speed & Duplex resolved */
1725 #define M88E1000_PSSR_PAGE_RCVD         0x1000  /* 1=Page received */
1726 #define M88E1000_PSSR_DPLX              0x2000  /* 1=Duplex 0=Half Duplex */
1727 #define M88E1000_PSSR_SPEED             0xC000  /* Speed, bits 14:15 */
1728 #define M88E1000_PSSR_10MBS             0x0000  /* 00=10Mbs */
1729 #define M88E1000_PSSR_100MBS            0x4000  /* 01=100Mbs */
1730 #define M88E1000_PSSR_1000MBS           0x8000  /* 10=1000Mbs */
1731
1732 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1733 #define M88E1000_PSSR_MDIX_SHIFT         6
1734 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1735
1736 /* M88E1000 Extended PHY Specific Control Register */
1737 #define M88E1000_EPSCR_FIBER_LOOPBACK   0x4000  /* 1=Fiber loopback */
1738 #define M88E1000_EPSCR_DOWN_NO_IDLE     0x8000  /* 1=Lost lock detect enabled.
1739                                                  * Will assert lost lock and bring
1740                                                  * link down if idle not seen
1741                                                  * within 1ms in 1000BASE-T
1742                                                  */
1743 /* Number of times we will attempt to autonegotiate before downshifting if we
1744  * are the master */
1745 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1746 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
1747 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
1748 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
1749 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
1750 /* Number of times we will attempt to autonegotiate before downshifting if we
1751  * are the slave */
1752 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
1753 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
1754 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
1755 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
1756 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
1757 #define M88E1000_EPSCR_TX_CLK_2_5       0x0060  /* 2.5 MHz TX_CLK */
1758 #define M88E1000_EPSCR_TX_CLK_25        0x0070  /* 25  MHz TX_CLK */
1759 #define M88E1000_EPSCR_TX_CLK_0 0x0000  /* NO  TX_CLK */
1760
1761 /* Bit definitions for valid PHY IDs. */
1762 #define M88E1000_E_PHY_ID               0x01410C50
1763 #define M88E1000_I_PHY_ID               0x01410C30
1764 #define M88E1011_I_PHY_ID               0x01410C20
1765 #define M88E1000_12_PHY_ID              M88E1000_E_PHY_ID
1766 #define M88E1000_14_PHY_ID              M88E1000_E_PHY_ID
1767 #define IGP01E1000_I_PHY_ID             0x02A80380
1768
1769 /* Miscellaneous PHY bit definitions. */
1770 #define PHY_PREAMBLE                    0xFFFFFFFF
1771 #define PHY_SOF                         0x01
1772 #define PHY_OP_READ                     0x02
1773 #define PHY_OP_WRITE                    0x01
1774 #define PHY_TURNAROUND                  0x02
1775 #define PHY_PREAMBLE_SIZE               32
1776 #define MII_CR_SPEED_1000               0x0040
1777 #define MII_CR_SPEED_100                0x2000
1778 #define MII_CR_SPEED_10         0x0000
1779 #define E1000_PHY_ADDRESS               0x01
1780 #define PHY_AUTO_NEG_TIME               45      /* 4.5 Seconds */
1781 #define PHY_FORCE_TIME                  20      /* 2.0 Seconds */
1782 #define PHY_REVISION_MASK               0xFFFFFFF0
1783 #define DEVICE_SPEED_MASK               0x00000300      /* Device Ctrl Reg Speed Mask */
1784 #define REG4_SPEED_MASK         0x01E0
1785 #define REG9_SPEED_MASK         0x0300
1786 #define ADVERTISE_10_HALF               0x0001
1787 #define ADVERTISE_10_FULL               0x0002
1788 #define ADVERTISE_100_HALF              0x0004
1789 #define ADVERTISE_100_FULL              0x0008
1790 #define ADVERTISE_1000_HALF             0x0010
1791 #define ADVERTISE_1000_FULL             0x0020
1792 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
1793
1794 #endif  /* _E1000_HW_H_ */