drivers/net/ethoc.c

   1 /*
   2  * Opencore 10/100 ethernet mac driver
   3  *
   4  * Copyright (C) 2007-2008 Avionic Design Development GmbH
   5  * Copyright (C) 2008-2009 Avionic Design GmbH
   6  *   Thierry Reding <thierry.reding@avionic-design.de>
   7  * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
   8  * Copyright (C) 2016 Cadence Design Systems Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #include <common.h>
  14 #include <dm/device.h>
  15 #include <dm/platform_data/net_ethoc.h>
  16 #include <linux/io.h>
  17 #include <malloc.h>
  18 #include <net.h>
  19 #include <miiphy.h>
  20 #include <asm/cache.h>
  21
  22 /* register offsets */
  23 #define MODER           0x00
  24 #define INT_SOURCE      0x04
  25 #define INT_MASK        0x08
  26 #define IPGT            0x0c
  27 #define IPGR1           0x10
  28 #define IPGR2           0x14
  29 #define PACKETLEN       0x18
  30 #define COLLCONF        0x1c
  31 #define TX_BD_NUM       0x20
  32 #define CTRLMODER       0x24
  33 #define MIIMODER        0x28
  34 #define MIICOMMAND      0x2c
  35 #define MIIADDRESS      0x30
  36 #define MIITX_DATA      0x34
  37 #define MIIRX_DATA      0x38
  38 #define MIISTATUS       0x3c
  39 #define MAC_ADDR0       0x40
  40 #define MAC_ADDR1       0x44
  41 #define ETH_HASH0       0x48
  42 #define ETH_HASH1       0x4c
  43 #define ETH_TXCTRL      0x50
  44
  45 /* mode register */
  46 #define MODER_RXEN      (1 <<  0)       /* receive enable */
  47 #define MODER_TXEN      (1 <<  1)       /* transmit enable */
  48 #define MODER_NOPRE     (1 <<  2)       /* no preamble */
  49 #define MODER_BRO       (1 <<  3)       /* broadcast address */
  50 #define MODER_IAM       (1 <<  4)       /* individual address mode */
  51 #define MODER_PRO       (1 <<  5)       /* promiscuous mode */
  52 #define MODER_IFG       (1 <<  6)       /* interframe gap for incoming frames */
  53 #define MODER_LOOP      (1 <<  7)       /* loopback */
  54 #define MODER_NBO       (1 <<  8)       /* no back-off */
  55 #define MODER_EDE       (1 <<  9)       /* excess defer enable */
  56 #define MODER_FULLD     (1 << 10)       /* full duplex */
  57 #define MODER_RESET     (1 << 11)       /* FIXME: reset (undocumented) */
  58 #define MODER_DCRC      (1 << 12)       /* delayed CRC enable */
  59 #define MODER_CRC       (1 << 13)       /* CRC enable */
  60 #define MODER_HUGE      (1 << 14)       /* huge packets enable */
  61 #define MODER_PAD       (1 << 15)       /* padding enabled */
  62 #define MODER_RSM       (1 << 16)       /* receive small packets */
  63
  64 /* interrupt source and mask registers */
  65 #define INT_MASK_TXF    (1 << 0)        /* transmit frame */
  66 #define INT_MASK_TXE    (1 << 1)        /* transmit error */
  67 #define INT_MASK_RXF    (1 << 2)        /* receive frame */
  68 #define INT_MASK_RXE    (1 << 3)        /* receive error */
  69 #define INT_MASK_BUSY   (1 << 4)
  70 #define INT_MASK_TXC    (1 << 5)        /* transmit control frame */
  71 #define INT_MASK_RXC    (1 << 6)        /* receive control frame */
  72
  73 #define INT_MASK_TX     (INT_MASK_TXF | INT_MASK_TXE)
  74 #define INT_MASK_RX     (INT_MASK_RXF | INT_MASK_RXE)
  75
  76 #define INT_MASK_ALL ( \
  77                 INT_MASK_TXF | INT_MASK_TXE | \
  78                 INT_MASK_RXF | INT_MASK_RXE | \
  79                 INT_MASK_TXC | INT_MASK_RXC | \
  80                 INT_MASK_BUSY \
  81         )
  82
  83 /* packet length register */
  84 #define PACKETLEN_MIN(min)              (((min) & 0xffff) << 16)
  85 #define PACKETLEN_MAX(max)              (((max) & 0xffff) <<  0)
  86 #define PACKETLEN_MIN_MAX(min, max)     (PACKETLEN_MIN(min) | \
  87                                         PACKETLEN_MAX(max))
  88
  89 /* transmit buffer number register */
  90 #define TX_BD_NUM_VAL(x)        (((x) <= 0x80) ? (x) : 0x80)
  91
  92 /* control module mode register */
  93 #define CTRLMODER_PASSALL       (1 << 0)        /* pass all receive frames */
  94 #define CTRLMODER_RXFLOW        (1 << 1)        /* receive control flow */
  95 #define CTRLMODER_TXFLOW        (1 << 2)        /* transmit control flow */
  96
  97 /* MII mode register */
  98 #define MIIMODER_CLKDIV(x)      ((x) & 0xfe)    /* needs to be an even number */
  99 #define MIIMODER_NOPRE          (1 << 8)        /* no preamble */
 100
 101 /* MII command register */
 102 #define MIICOMMAND_SCAN         (1 << 0)        /* scan status */
 103 #define MIICOMMAND_READ         (1 << 1)        /* read status */
 104 #define MIICOMMAND_WRITE        (1 << 2)        /* write control data */
 105
 106 /* MII address register */
 107 #define MIIADDRESS_FIAD(x)              (((x) & 0x1f) << 0)
 108 #define MIIADDRESS_RGAD(x)              (((x) & 0x1f) << 8)
 109 #define MIIADDRESS_ADDR(phy, reg)       (MIIADDRESS_FIAD(phy) | \
 110                                         MIIADDRESS_RGAD(reg))
 111
 112 /* MII transmit data register */
 113 #define MIITX_DATA_VAL(x)       ((x) & 0xffff)
 114
 115 /* MII receive data register */
 116 #define MIIRX_DATA_VAL(x)       ((x) & 0xffff)
 117
 118 /* MII status register */
 119 #define MIISTATUS_LINKFAIL      (1 << 0)
 120 #define MIISTATUS_BUSY          (1 << 1)
 121 #define MIISTATUS_INVALID       (1 << 2)
 122
 123 /* TX buffer descriptor */
 124 #define TX_BD_CS                (1 <<  0)       /* carrier sense lost */
 125 #define TX_BD_DF                (1 <<  1)       /* defer indication */
 126 #define TX_BD_LC                (1 <<  2)       /* late collision */
 127 #define TX_BD_RL                (1 <<  3)       /* retransmission limit */
 128 #define TX_BD_RETRY_MASK        (0x00f0)
 129 #define TX_BD_RETRY(x)          (((x) & 0x00f0) >>  4)
 130 #define TX_BD_UR                (1 <<  8)       /* transmitter underrun */
 131 #define TX_BD_CRC               (1 << 11)       /* TX CRC enable */
 132 #define TX_BD_PAD               (1 << 12)       /* pad enable */
 133 #define TX_BD_WRAP              (1 << 13)
 134 #define TX_BD_IRQ               (1 << 14)       /* interrupt request enable */
 135 #define TX_BD_READY             (1 << 15)       /* TX buffer ready */
 136 #define TX_BD_LEN(x)            (((x) & 0xffff) << 16)
 137 #define TX_BD_LEN_MASK          (0xffff << 16)
 138
 139 #define TX_BD_STATS             (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
 140                                 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
 141
 142 /* RX buffer descriptor */
 143 #define RX_BD_LC        (1 <<  0)       /* late collision */
 144 #define RX_BD_CRC       (1 <<  1)       /* RX CRC error */
 145 #define RX_BD_SF        (1 <<  2)       /* short frame */
 146 #define RX_BD_TL        (1 <<  3)       /* too long */
 147 #define RX_BD_DN        (1 <<  4)       /* dribble nibble */
 148 #define RX_BD_IS        (1 <<  5)       /* invalid symbol */
 149 #define RX_BD_OR        (1 <<  6)       /* receiver overrun */
 150 #define RX_BD_MISS      (1 <<  7)
 151 #define RX_BD_CF        (1 <<  8)       /* control frame */
 152 #define RX_BD_WRAP      (1 << 13)
 153 #define RX_BD_IRQ       (1 << 14)       /* interrupt request enable */
 154 #define RX_BD_EMPTY     (1 << 15)
 155 #define RX_BD_LEN(x)    (((x) & 0xffff) << 16)
 156
 157 #define RX_BD_STATS     (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
 158                         RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
 159
 160 #define ETHOC_BUFSIZ            1536
 161 #define ETHOC_ZLEN              64
 162 #define ETHOC_BD_BASE           0x400
 163 #define ETHOC_TIMEOUT           (HZ / 2)
 164 #define ETHOC_MII_TIMEOUT       (1 + (HZ / 5))
 165 #define ETHOC_IOSIZE            0x54
 166
 167 /**
 168  * struct ethoc - driver-private device structure
 169  * @num_tx:     number of send buffers
 170  * @cur_tx:     last send buffer written
 171  * @dty_tx:     last buffer actually sent
 172  * @num_rx:     number of receive buffers
 173  * @cur_rx:     current receive buffer
 174  */
 175 struct ethoc {
 176         u32 num_tx;
 177         u32 cur_tx;
 178         u32 dty_tx;
 179         u32 num_rx;
 180         u32 cur_rx;
 181         void __iomem *iobase;
 182 };
 183
 184 /**
 185  * struct ethoc_bd - buffer descriptor
 186  * @stat:       buffer statistics
 187  * @addr:       physical memory address
 188  */
 189 struct ethoc_bd {
 190         u32 stat;
 191         u32 addr;
 192 };
 193
 194 static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
 195 {
 196         return readl(priv->iobase + offset);
 197 }
 198
 199 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
 200 {
 201         writel(data, priv->iobase + offset);
 202 }
 203
 204 static inline void ethoc_read_bd(struct ethoc *priv, int index,
 205                                  struct ethoc_bd *bd)
 206 {
 207         size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 208         bd->stat = ethoc_read(priv, offset + 0);
 209         bd->addr = ethoc_read(priv, offset + 4);
 210 }
 211
 212 static inline void ethoc_write_bd(struct ethoc *priv, int index,
 213                                   const struct ethoc_bd *bd)
 214 {
 215         size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 216         ethoc_write(priv, offset + 0, bd->stat);
 217         ethoc_write(priv, offset + 4, bd->addr);
 218 }
 219
 220 static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
 221 {
 222         ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
 223                     (mac[4] << 8) | (mac[5] << 0));
 224         ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
 225         return 0;
 226 }
 227
 228 static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
 229 {
 230         ethoc_write(priv, INT_SOURCE, mask);
 231 }
 232
 233 static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
 234 {
 235         u32 mode = ethoc_read(priv, MODER);
 236         mode |= MODER_RXEN | MODER_TXEN;
 237         ethoc_write(priv, MODER, mode);
 238 }
 239
 240 static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
 241 {
 242         u32 mode = ethoc_read(priv, MODER);
 243         mode &= ~(MODER_RXEN | MODER_TXEN);
 244         ethoc_write(priv, MODER, mode);
 245 }
 246
 247 static int ethoc_init_ring(struct ethoc *priv)
 248 {
 249         struct ethoc_bd bd;
 250         int i;
 251
 252         priv->cur_tx = 0;
 253         priv->dty_tx = 0;
 254         priv->cur_rx = 0;
 255
 256         /* setup transmission buffers */
 257         bd.stat = TX_BD_IRQ | TX_BD_CRC;
 258
 259         for (i = 0; i < priv->num_tx; i++) {
 260                 if (i == priv->num_tx - 1)
 261                         bd.stat |= TX_BD_WRAP;
 262
 263                 ethoc_write_bd(priv, i, &bd);
 264         }
 265
 266         bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 267
 268         for (i = 0; i < priv->num_rx; i++) {
 269                 bd.addr = (u32)net_rx_packets[i];
 270                 if (i == priv->num_rx - 1)
 271                         bd.stat |= RX_BD_WRAP;
 272
 273                 flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
 274                 ethoc_write_bd(priv, priv->num_tx + i, &bd);
 275         }
 276
 277         return 0;
 278 }
 279
 280 static int ethoc_reset(struct ethoc *priv)
 281 {
 282         u32 mode;
 283
 284         /* TODO: reset controller? */
 285
 286         ethoc_disable_rx_and_tx(priv);
 287
 288         /* TODO: setup registers */
 289
 290         /* enable FCS generation and automatic padding */
 291         mode = ethoc_read(priv, MODER);
 292         mode |= MODER_CRC | MODER_PAD;
 293         ethoc_write(priv, MODER, mode);
 294
 295         /* set full-duplex mode */
 296         mode = ethoc_read(priv, MODER);
 297         mode |= MODER_FULLD;
 298         ethoc_write(priv, MODER, mode);
 299         ethoc_write(priv, IPGT, 0x15);
 300
 301         ethoc_ack_irq(priv, INT_MASK_ALL);
 302         ethoc_enable_rx_and_tx(priv);
 303         return 0;
 304 }
 305
 306 static int ethoc_init_common(struct ethoc *priv)
 307 {
 308         priv->num_tx = 1;
 309         priv->num_rx = PKTBUFSRX;
 310         ethoc_write(priv, TX_BD_NUM, priv->num_tx);
 311         ethoc_init_ring(priv);
 312         ethoc_reset(priv);
 313
 314         return 0;
 315 }
 316
 317 static int ethoc_update_rx_stats(struct ethoc_bd *bd)
 318 {
 319         int ret = 0;
 320
 321         if (bd->stat & RX_BD_TL) {
 322                 debug("ETHOC: " "RX: frame too long\n");
 323                 ret++;
 324         }
 325
 326         if (bd->stat & RX_BD_SF) {
 327                 debug("ETHOC: " "RX: frame too short\n");
 328                 ret++;
 329         }
 330
 331         if (bd->stat & RX_BD_DN)
 332                 debug("ETHOC: " "RX: dribble nibble\n");
 333
 334         if (bd->stat & RX_BD_CRC) {
 335                 debug("ETHOC: " "RX: wrong CRC\n");
 336                 ret++;
 337         }
 338
 339         if (bd->stat & RX_BD_OR) {
 340                 debug("ETHOC: " "RX: overrun\n");
 341                 ret++;
 342         }
 343
 344         if (bd->stat & RX_BD_LC) {
 345                 debug("ETHOC: " "RX: late collision\n");
 346                 ret++;
 347         }
 348
 349         return ret;
 350 }
 351
 352 static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
 353 {
 354         u32 entry;
 355         struct ethoc_bd bd;
 356
 357         entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
 358         ethoc_read_bd(priv, entry, &bd);
 359         if (bd.stat & RX_BD_EMPTY)
 360                 return -EAGAIN;
 361
 362         debug("%s(): RX buffer %d, %x received\n",
 363               __func__, priv->cur_rx, bd.stat);
 364         if (ethoc_update_rx_stats(&bd) == 0) {
 365                 int size = bd.stat >> 16;
 366
 367                 size -= 4;      /* strip the CRC */
 368                 *packetp = (void *)bd.addr;
 369                 return size;
 370         } else {
 371                 return 0;
 372         }
 373 }
 374
 375 static int ethoc_is_new_packet_received(struct ethoc *priv)
 376 {
 377         u32 pending;
 378
 379         pending = ethoc_read(priv, INT_SOURCE);
 380         ethoc_ack_irq(priv, pending);
 381         if (pending & INT_MASK_BUSY)
 382                 debug("%s(): packet dropped\n", __func__);
 383         if (pending & INT_MASK_RX) {
 384                 debug("%s(): rx irq\n", __func__);
 385                 return 1;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int ethoc_update_tx_stats(struct ethoc_bd *bd)
 392 {
 393         if (bd->stat & TX_BD_LC)
 394                 debug("ETHOC: " "TX: late collision\n");
 395
 396         if (bd->stat & TX_BD_RL)
 397                 debug("ETHOC: " "TX: retransmit limit\n");
 398
 399         if (bd->stat & TX_BD_UR)
 400                 debug("ETHOC: " "TX: underrun\n");
 401
 402         if (bd->stat & TX_BD_CS)
 403                 debug("ETHOC: " "TX: carrier sense lost\n");
 404
 405         return 0;
 406 }
 407
 408 static void ethoc_tx(struct ethoc *priv)
 409 {
 410         u32 entry = priv->dty_tx % priv->num_tx;
 411         struct ethoc_bd bd;
 412
 413         ethoc_read_bd(priv, entry, &bd);
 414         if ((bd.stat & TX_BD_READY) == 0)
 415                 (void)ethoc_update_tx_stats(&bd);
 416 }
 417
 418 static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
 419 {
 420         struct ethoc_bd bd;
 421         u32 entry;
 422         u32 pending;
 423         int tmo;
 424
 425         entry = priv->cur_tx % priv->num_tx;
 426         ethoc_read_bd(priv, entry, &bd);
 427         if (unlikely(length < ETHOC_ZLEN))
 428                 bd.stat |= TX_BD_PAD;
 429         else
 430                 bd.stat &= ~TX_BD_PAD;
 431         bd.addr = (u32)packet;
 432
 433         flush_dcache_range(bd.addr, bd.addr + length);
 434         bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
 435         bd.stat |= TX_BD_LEN(length);
 436         ethoc_write_bd(priv, entry, &bd);
 437
 438         /* start transmit */
 439         bd.stat |= TX_BD_READY;
 440         ethoc_write_bd(priv, entry, &bd);
 441
 442         /* wait for transfer to succeed */
 443         tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
 444         while (1) {
 445                 pending = ethoc_read(priv, INT_SOURCE);
 446                 ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
 447                 if (pending & INT_MASK_BUSY)
 448                         debug("%s(): packet dropped\n", __func__);
 449
 450                 if (pending & INT_MASK_TX) {
 451                         ethoc_tx(priv);
 452                         break;
 453                 }
 454                 if (get_timer(0) >= tmo) {
 455                         debug("%s(): timed out\n", __func__);
 456                         return -1;
 457                 }
 458         }
 459
 460         debug("%s(): packet sent\n", __func__);
 461         return 0;
 462 }
 463
 464 static int ethoc_free_pkt_common(struct ethoc *priv)
 465 {
 466         u32 entry;
 467         struct ethoc_bd bd;
 468
 469         entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
 470         ethoc_read_bd(priv, entry, &bd);
 471
 472         /* clear the buffer descriptor so it can be reused */
 473         flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
 474         bd.stat &= ~RX_BD_STATS;
 475         bd.stat |= RX_BD_EMPTY;
 476         ethoc_write_bd(priv, entry, &bd);
 477         priv->cur_rx++;
 478
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_DM_ETH
 483
 484 static int ethoc_write_hwaddr(struct udevice *dev)
 485 {
 486         struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
 487         struct ethoc *priv = dev_get_priv(dev);
 488         u8 *mac = pdata->eth_pdata.enetaddr;
 489
 490         return ethoc_write_hwaddr_common(priv, mac);
 491 }
 492
 493 static int ethoc_send(struct udevice *dev, void *packet, int length)
 494 {
 495         return ethoc_send_common(dev_get_priv(dev), packet, length);
 496 }
 497
 498 static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
 499 {
 500         return ethoc_free_pkt_common(dev_get_priv(dev));
 501 }
 502
 503 static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
 504 {
 505         struct ethoc *priv = dev_get_priv(dev);
 506
 507         if (flags & ETH_RECV_CHECK_DEVICE)
 508                 if (!ethoc_is_new_packet_received(priv))
 509                         return -EAGAIN;
 510
 511         return ethoc_rx_common(priv, packetp);
 512 }
 513
 514 static int ethoc_start(struct udevice *dev)
 515 {
 516         return ethoc_init_common(dev_get_priv(dev));
 517 }
 518
 519 static void ethoc_stop(struct udevice *dev)
 520 {
 521         struct ethoc *priv = dev_get_priv(dev);
 522
 523         ethoc_disable_rx_and_tx(priv);
 524 }
 525
 526 static int ethoc_probe(struct udevice *dev)
 527 {
 528         struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
 529         struct ethoc *priv = dev_get_priv(dev);
 530
 531         priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
 532         return 0;
 533 }
 534
 535 static int ethoc_remove(struct udevice *dev)
 536 {
 537         struct ethoc *priv = dev_get_priv(dev);
 538
 539         iounmap(priv->iobase);
 540         return 0;
 541 }
 542
 543 static const struct eth_ops ethoc_ops = {
 544         .start          = ethoc_start,
 545         .stop           = ethoc_stop,
 546         .send           = ethoc_send,
 547         .recv           = ethoc_recv,
 548         .free_pkt       = ethoc_free_pkt,
 549         .write_hwaddr   = ethoc_write_hwaddr,
 550 };
 551
 552 U_BOOT_DRIVER(ethoc) = {
 553         .name                           = "ethoc",
 554         .id                             = UCLASS_ETH,
 555         .probe                          = ethoc_probe,
 556         .remove                         = ethoc_remove,
 557         .ops                            = &ethoc_ops,
 558         .priv_auto_alloc_size           = sizeof(struct ethoc),
 559         .platdata_auto_alloc_size       = sizeof(struct ethoc_eth_pdata),
 560 };
 561
 562 #else
 563
 564 static int ethoc_init(struct eth_device *dev, bd_t *bd)
 565 {
 566         struct ethoc *priv = (struct ethoc *)dev->priv;
 567
 568         return ethoc_init_common(priv);
 569 }
 570
 571 static int ethoc_write_hwaddr(struct eth_device *dev)
 572 {
 573         struct ethoc *priv = (struct ethoc *)dev->priv;
 574         u8 *mac = dev->enetaddr;
 575
 576         return ethoc_write_hwaddr_common(priv, mac);
 577 }
 578
 579 static int ethoc_send(struct eth_device *dev, void *packet, int length)
 580 {
 581         return ethoc_send_common(dev->priv, packet, length);
 582 }
 583
 584 static void ethoc_halt(struct eth_device *dev)
 585 {
 586         ethoc_disable_rx_and_tx(dev->priv);
 587 }
 588
 589 static int ethoc_recv(struct eth_device *dev)
 590 {
 591         struct ethoc *priv = (struct ethoc *)dev->priv;
 592         int count;
 593
 594         if (!ethoc_is_new_packet_received(priv))
 595                 return 0;
 596
 597         for (count = 0; count < PKTBUFSRX; ++count) {
 598                 uchar *packetp;
 599                 int size = ethoc_rx_common(priv, &packetp);
 600
 601                 if (size < 0)
 602                         break;
 603                 if (size > 0)
 604                         net_process_received_packet(packetp, size);
 605                 ethoc_free_pkt_common(priv);
 606         }
 607         return 0;
 608 }
 609
 610 int ethoc_initialize(u8 dev_num, int base_addr)
 611 {
 612         struct ethoc *priv;
 613         struct eth_device *dev;
 614
 615         priv = malloc(sizeof(*priv));
 616         if (!priv)
 617                 return 0;
 618         dev = malloc(sizeof(*dev));
 619         if (!dev) {
 620                 free(priv);
 621                 return 0;
 622         }
 623
 624         memset(dev, 0, sizeof(*dev));
 625         dev->priv = priv;
 626         dev->iobase = base_addr;
 627         dev->init = ethoc_init;
 628         dev->halt = ethoc_halt;
 629         dev->send = ethoc_send;
 630         dev->recv = ethoc_recv;
 631         dev->write_hwaddr = ethoc_write_hwaddr;
 632         sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
 633         priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
 634
 635         eth_register(dev);
 636         return 1;
 637 }
 638
 639 #endif