2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
11 #include <fsl-mc/fsl_mc.h>
12 #include <fsl-mc/fsl_mc_sys.h>
13 #include <fsl-mc/fsl_mc_private.h>
14 #include <fsl-mc/fsl_dpmng.h>
15 #include <fsl-mc/fsl_dprc.h>
16 #include <fsl-mc/fsl_dpio.h>
17 #include <fsl-mc/fsl_dpni.h>
18 #include <fsl-mc/fsl_qbman_portal.h>
19 #include <fsl-mc/ldpaa_wriop.h>
21 #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
22 #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
23 #define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
25 #define MC_MEM_SIZE_ENV_VAR "mcmemsize"
26 #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
28 DECLARE_GLOBAL_DATA_PTR
;
29 static int mc_boot_status
= -1;
30 static int mc_dpl_applied
= -1;
31 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
32 static int mc_aiop_applied
= -1;
34 struct fsl_mc_io
*root_mc_io
= NULL
;
35 struct fsl_mc_io
*dflt_mc_io
= NULL
; /* child container */
36 uint16_t root_dprc_handle
= 0;
37 uint16_t dflt_dprc_handle
= 0;
39 struct fsl_dpbp_obj
*dflt_dpbp
= NULL
;
40 struct fsl_dpio_obj
*dflt_dpio
= NULL
;
41 struct fsl_dpni_obj
*dflt_dpni
= NULL
;
44 void dump_ram_words(const char *title
, void *addr
)
47 uint32_t *words
= addr
;
49 printf("Dumping beginning of %s (%p):\n", title
, addr
);
50 for (i
= 0; i
< 16; i
++)
51 printf("%#x ", words
[i
]);
56 void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem
*mc_ccsr_regs
)
58 printf("MC CCSR registers:\n"
68 mc_ccsr_regs
->reg_gcr1
,
69 mc_ccsr_regs
->reg_gsr
,
70 mc_ccsr_regs
->reg_sicbalr
,
71 mc_ccsr_regs
->reg_sicbahr
,
72 mc_ccsr_regs
->reg_sicapr
,
73 mc_ccsr_regs
->reg_mcfbalr
,
74 mc_ccsr_regs
->reg_mcfbahr
,
75 mc_ccsr_regs
->reg_mcfapr
,
76 mc_ccsr_regs
->reg_psr
);
80 #define dump_ram_words(title, addr)
81 #define dump_mc_ccsr_regs(mc_ccsr_regs)
85 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
87 * Copying MC firmware or DPL image to DDR
89 static int mc_copy_image(const char *title
,
90 u64 image_addr
, u32 image_size
, u64 mc_ram_addr
)
92 debug("%s copied to address %p\n", title
, (void *)mc_ram_addr
);
93 memcpy((void *)mc_ram_addr
, (void *)image_addr
, image_size
);
94 flush_dcache_range(mc_ram_addr
, mc_ram_addr
+ image_size
);
99 * MC firmware FIT image parser checks if the image is in FIT
100 * format, verifies integrity of the image and calculates
101 * raw image address and size values.
102 * Returns 0 on success and a negative errno on error.
105 int parse_mc_firmware_fit_image(u64 mc_fw_addr
,
106 const void **raw_image_addr
,
107 size_t *raw_image_size
)
114 const char *uname
= "firmware";
116 fit_hdr
= (void *)mc_fw_addr
;
118 /* Check if Image is in FIT format */
119 format
= genimg_get_format(fit_hdr
);
121 if (format
!= IMAGE_FORMAT_FIT
) {
122 printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
126 if (!fit_check_format(fit_hdr
)) {
127 printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
131 node_offset
= fit_image_get_node(fit_hdr
, uname
);
133 if (node_offset
< 0) {
134 printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
138 /* Verify MC firmware image */
139 if (!(fit_image_verify(fit_hdr
, node_offset
))) {
140 printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
144 /* Get address and size of raw image */
145 fit_image_get_data(fit_hdr
, node_offset
, &data
, &size
);
147 *raw_image_addr
= data
;
148 *raw_image_size
= size
;
155 * Calculates the values to be used to specify the address range
156 * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
157 * It returns the highest 512MB-aligned address within the given
158 * address range, in '*aligned_base_addr', and the number of 256 MiB
159 * blocks in it, in 'num_256mb_blocks'.
161 static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr
,
163 u64
*aligned_base_addr
,
164 u8
*num_256mb_blocks
)
169 if (mc_ram_size
% MC_RAM_SIZE_ALIGNMENT
!= 0) {
170 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
175 num_blocks
= mc_ram_size
/ MC_RAM_SIZE_ALIGNMENT
;
176 if (num_blocks
< 1 || num_blocks
> 0xff) {
177 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
182 addr
= (mc_private_ram_start_addr
+ mc_ram_size
- 1) &
183 MC_RAM_BASE_ADDR_ALIGNMENT_MASK
;
185 if (addr
< mc_private_ram_start_addr
) {
186 printf("fsl-mc: ERROR: bad start address %#llx\n",
187 mc_private_ram_start_addr
);
191 *aligned_base_addr
= addr
;
192 *num_256mb_blocks
= num_blocks
;
196 static int mc_fixup_dpc(u64 dpc_addr
)
198 void *blob
= (void *)dpc_addr
;
201 /* delete any existing ICID pools */
202 nodeoffset
= fdt_path_offset(blob
, "/resources/icid_pools");
203 if (fdt_del_node(blob
, nodeoffset
) < 0)
204 printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
207 nodeoffset
= fdt_path_offset(blob
, "/resources");
208 if (nodeoffset
< 0) {
209 printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
212 nodeoffset
= fdt_add_subnode(blob
, nodeoffset
, "icid_pools");
213 nodeoffset
= fdt_add_subnode(blob
, nodeoffset
, "icid_pool@0");
214 do_fixup_by_path_u32(blob
, "/resources/icid_pools/icid_pool@0",
215 "base_icid", FSL_DPAA2_STREAM_ID_START
, 1);
216 do_fixup_by_path_u32(blob
, "/resources/icid_pools/icid_pool@0",
218 FSL_DPAA2_STREAM_ID_END
-
219 FSL_DPAA2_STREAM_ID_START
+ 1, 1);
221 flush_dcache_range(dpc_addr
, dpc_addr
+ fdt_totalsize(blob
));
226 static int load_mc_dpc(u64 mc_ram_addr
, size_t mc_ram_size
, u64 mc_dpc_addr
)
229 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
235 #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
236 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
& 0x3) != 0 ||
237 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
> 0xffffffff);
239 mc_dpc_offset
= CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
;
241 #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
245 * Load the MC DPC blob in the MC private DRAM block:
247 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
248 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr
+ mc_dpc_offset
);
251 * Get address and size of the DPC blob stored in flash:
253 dpc_fdt_hdr
= (void *)mc_dpc_addr
;
255 error
= fdt_check_header(dpc_fdt_hdr
);
258 * Don't return with error here, since the MC firmware can
259 * still boot without a DPC
261 printf("\nfsl-mc: WARNING: No DPC image found");
265 dpc_size
= fdt_totalsize(dpc_fdt_hdr
);
266 if (dpc_size
> CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
) {
267 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
272 mc_copy_image("MC DPC blob",
273 (u64
)dpc_fdt_hdr
, dpc_size
, mc_ram_addr
+ mc_dpc_offset
);
274 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
276 if (mc_fixup_dpc(mc_ram_addr
+ mc_dpc_offset
))
279 dump_ram_words("DPC", (void *)(mc_ram_addr
+ mc_dpc_offset
));
283 static int load_mc_dpl(u64 mc_ram_addr
, size_t mc_ram_size
, u64 mc_dpl_addr
)
286 #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
292 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
293 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
& 0x3) != 0 ||
294 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
> 0xffffffff);
296 mc_dpl_offset
= CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
;
298 #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
302 * Load the MC DPL blob in the MC private DRAM block:
304 #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
305 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr
+ mc_dpl_offset
);
308 * Get address and size of the DPL blob stored in flash:
310 dpl_fdt_hdr
= (void *)mc_dpl_addr
;
312 error
= fdt_check_header(dpl_fdt_hdr
);
314 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
318 dpl_size
= fdt_totalsize(dpl_fdt_hdr
);
319 if (dpl_size
> CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
) {
320 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
325 mc_copy_image("MC DPL blob",
326 (u64
)dpl_fdt_hdr
, dpl_size
, mc_ram_addr
+ mc_dpl_offset
);
327 #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
329 dump_ram_words("DPL", (void *)(mc_ram_addr
+ mc_dpl_offset
));
334 * Return the MC boot timeout value in milliseconds
336 static unsigned long get_mc_boot_timeout_ms(void)
338 unsigned long timeout_ms
= CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
;
340 char *timeout_ms_env_var
= getenv(MC_BOOT_TIMEOUT_ENV_VAR
);
342 if (timeout_ms_env_var
) {
343 timeout_ms
= simple_strtoul(timeout_ms_env_var
, NULL
, 10);
344 if (timeout_ms
== 0) {
345 printf("fsl-mc: WARNING: Invalid value for \'"
346 MC_BOOT_TIMEOUT_ENV_VAR
347 "\' environment variable: %lu\n",
350 timeout_ms
= CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
;
357 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
358 static int load_mc_aiop_img(u64 aiop_fw_addr
)
360 u64 mc_ram_addr
= mc_get_dram_addr();
361 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
366 * Load the MC AIOP image in the MC private DRAM block:
369 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
370 printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr
+
371 CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
);
373 aiop_img
= (void *)aiop_fw_addr
;
374 mc_copy_image("MC AIOP image",
375 (u64
)aiop_img
, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
,
376 mc_ram_addr
+ CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
);
384 static int wait_for_mc(bool booting_mc
, u32
*final_reg_gsr
)
387 u32 mc_fw_boot_status
;
388 unsigned long timeout_ms
= get_mc_boot_timeout_ms();
389 struct mc_ccsr_registers __iomem
*mc_ccsr_regs
= MC_CCSR_BASE_ADDR
;
392 assert(timeout_ms
> 0);
394 udelay(1000); /* throttle polling */
395 reg_gsr
= in_le32(&mc_ccsr_regs
->reg_gsr
);
396 mc_fw_boot_status
= (reg_gsr
& GSR_FS_MASK
);
397 if (mc_fw_boot_status
& 0x1)
405 if (timeout_ms
== 0) {
406 printf("ERROR: timeout\n");
408 /* TODO: Get an error status from an MC CCSR register */
412 if (mc_fw_boot_status
!= 0x1) {
414 * TODO: Identify critical errors from the GSR register's FS
415 * field and for those errors, set error to -ENODEV or other
416 * appropriate errno, so that the status property is set to
417 * failure in the fsl,dprc device tree node.
419 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
426 *final_reg_gsr
= reg_gsr
;
430 int mc_init(u64 mc_fw_addr
, u64 mc_dpc_addr
)
434 struct mc_ccsr_registers __iomem
*mc_ccsr_regs
= MC_CCSR_BASE_ADDR
;
435 u64 mc_ram_addr
= mc_get_dram_addr();
438 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
439 const void *raw_image_addr
;
440 size_t raw_image_size
= 0;
442 struct mc_version mc_ver_info
;
443 u64 mc_ram_aligned_base_addr
;
444 u8 mc_ram_num_256mb_blocks
;
445 size_t mc_ram_size
= mc_get_dram_block_size();
448 error
= calculate_mc_private_ram_params(mc_ram_addr
,
450 &mc_ram_aligned_base_addr
,
451 &mc_ram_num_256mb_blocks
);
456 * Management Complex cores should be held at reset out of POR.
457 * U-boot should be the first software to touch MC. To be safe,
458 * we reset all cores again by setting GCR1 to 0. It doesn't do
459 * anything if they are held at reset. After we setup the firmware
460 * we kick off MC by deasserting the reset bit for core 0, and
461 * deasserting the reset bits for Command Portal Managers.
462 * The stop bits are not touched here. They are used to stop the
463 * cores when they are active. Setting stop bits doesn't stop the
464 * cores from fetching instructions when they are released from
467 out_le32(&mc_ccsr_regs
->reg_gcr1
, 0);
470 #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
471 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr
);
473 error
= parse_mc_firmware_fit_image(mc_fw_addr
, &raw_image_addr
,
478 * Load the MC FW at the beginning of the MC private DRAM block:
480 mc_copy_image("MC Firmware",
481 (u64
)raw_image_addr
, raw_image_size
, mc_ram_addr
);
483 dump_ram_words("firmware", (void *)mc_ram_addr
);
485 error
= load_mc_dpc(mc_ram_addr
, mc_ram_size
, mc_dpc_addr
);
489 debug("mc_ccsr_regs %p\n", mc_ccsr_regs
);
490 dump_mc_ccsr_regs(mc_ccsr_regs
);
493 * Tell MC what is the address range of the DRAM block assigned to it:
495 reg_mcfbalr
= (u32
)mc_ram_aligned_base_addr
|
496 (mc_ram_num_256mb_blocks
- 1);
497 out_le32(&mc_ccsr_regs
->reg_mcfbalr
, reg_mcfbalr
);
498 out_le32(&mc_ccsr_regs
->reg_mcfbahr
,
499 (u32
)(mc_ram_aligned_base_addr
>> 32));
500 out_le32(&mc_ccsr_regs
->reg_mcfapr
, FSL_BYPASS_AMQ
);
503 * Tell the MC that we want delayed DPL deployment.
505 out_le32(&mc_ccsr_regs
->reg_gsr
, 0xDD00);
507 printf("\nfsl-mc: Booting Management Complex ... ");
510 * Deassert reset and release MC core 0 to run
512 out_le32(&mc_ccsr_regs
->reg_gcr1
, GCR1_P1_DE_RST
| GCR1_M_ALL_DE_RST
);
513 error
= wait_for_mc(true, ®_gsr
);
518 * TODO: need to obtain the portal_id for the root container from the
524 * Initialize the global default MC portal
525 * And check that the MC firmware is responding portal commands:
527 root_mc_io
= (struct fsl_mc_io
*)malloc(sizeof(struct fsl_mc_io
));
529 printf(" No memory: malloc() failed\n");
533 root_mc_io
->mmio_regs
= SOC_MC_PORTAL_ADDR(portal_id
);
534 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
535 portal_id
, root_mc_io
->mmio_regs
);
537 error
= mc_get_version(root_mc_io
, MC_CMD_NO_FLAGS
, &mc_ver_info
);
539 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
544 if (MC_VER_MAJOR
!= mc_ver_info
.major
) {
545 printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
546 mc_ver_info
.major
, MC_VER_MAJOR
);
547 printf("fsl-mc: Update the Management Complex firmware\n");
553 if (MC_VER_MINOR
!= mc_ver_info
.minor
)
554 printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
555 mc_ver_info
.minor
, MC_VER_MINOR
);
557 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
558 mc_ver_info
.major
, mc_ver_info
.minor
, mc_ver_info
.revision
,
559 reg_gsr
& GSR_FS_MASK
);
563 mc_boot_status
= error
;
570 int mc_apply_dpl(u64 mc_dpl_addr
)
572 struct mc_ccsr_registers __iomem
*mc_ccsr_regs
= MC_CCSR_BASE_ADDR
;
575 u64 mc_ram_addr
= mc_get_dram_addr();
576 size_t mc_ram_size
= mc_get_dram_block_size();
578 error
= load_mc_dpl(mc_ram_addr
, mc_ram_size
, mc_dpl_addr
);
583 * Tell the MC to deploy the DPL:
585 out_le32(&mc_ccsr_regs
->reg_gsr
, 0x0);
586 printf("fsl-mc: Deploying data path layout ... ");
587 error
= wait_for_mc(false, ®_gsr
);
595 int get_mc_boot_status(void)
597 return mc_boot_status
;
600 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
601 int get_aiop_apply_status(void)
603 return mc_aiop_applied
;
607 int get_dpl_apply_status(void)
609 return mc_dpl_applied
;
613 * Return the MC address of private DRAM block.
615 u64
mc_get_dram_addr(void)
620 * The MC private DRAM block was already carved at the end of DRAM
621 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
623 if (gd
->bd
->bi_dram
[1].start
) {
625 gd
->bd
->bi_dram
[1].start
+ gd
->bd
->bi_dram
[1].size
;
628 gd
->bd
->bi_dram
[0].start
+ gd
->bd
->bi_dram
[0].size
;
635 * Return the actual size of the MC private DRAM block.
637 unsigned long mc_get_dram_block_size(void)
639 unsigned long dram_block_size
= CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
;
641 char *dram_block_size_env_var
= getenv(MC_MEM_SIZE_ENV_VAR
);
643 if (dram_block_size_env_var
) {
644 dram_block_size
= simple_strtoul(dram_block_size_env_var
, NULL
,
647 if (dram_block_size
< CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
) {
648 printf("fsl-mc: WARNING: Invalid value for \'"
650 "\' environment variable: %lu\n",
653 dram_block_size
= CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
;
657 return dram_block_size
;
660 int fsl_mc_ldpaa_init(bd_t
*bis
)
664 for (i
= WRIOP1_DPMAC1
; i
< NUM_WRIOP_PORTS
; i
++)
665 if ((wriop_is_enabled_dpmac(i
) == 1) &&
666 (wriop_get_phy_address(i
) != -1))
667 ldpaa_eth_init(i
, wriop_get_enet_if(i
));
671 static int dpio_init(void)
673 struct qbman_swp_desc p_des
;
674 struct dpio_attr attr
;
675 struct dpio_cfg dpio_cfg
;
678 dflt_dpio
= (struct fsl_dpio_obj
*)malloc(sizeof(struct fsl_dpio_obj
));
680 printf("No memory: malloc() failed\n");
685 dpio_cfg
.channel_mode
= DPIO_LOCAL_CHANNEL
;
686 dpio_cfg
.num_priorities
= 8;
688 err
= dpio_create(dflt_mc_io
, MC_CMD_NO_FLAGS
, &dpio_cfg
,
689 &dflt_dpio
->dpio_handle
);
691 printf("dpio_create() failed: %d\n", err
);
696 memset(&attr
, 0, sizeof(struct dpio_attr
));
697 err
= dpio_get_attributes(dflt_mc_io
, MC_CMD_NO_FLAGS
,
698 dflt_dpio
->dpio_handle
, &attr
);
700 printf("dpio_get_attributes() failed: %d\n", err
);
704 dflt_dpio
->dpio_id
= attr
.id
;
706 printf("Init: DPIO id=0x%d\n", dflt_dpio
->dpio_id
);
709 err
= dpio_enable(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
711 printf("dpio_enable() failed %d\n", err
);
714 debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
715 attr
.qbman_portal_ce_offset
,
716 attr
.qbman_portal_ci_offset
,
717 attr
.qbman_portal_id
,
718 attr
.num_priorities
);
720 p_des
.cena_bar
= (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
721 + attr
.qbman_portal_ce_offset
);
722 p_des
.cinh_bar
= (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
723 + attr
.qbman_portal_ci_offset
);
725 dflt_dpio
->sw_portal
= qbman_swp_init(&p_des
);
726 if (dflt_dpio
->sw_portal
== NULL
) {
727 printf("qbman_swp_init() failed\n");
728 goto err_get_swp_init
;
733 dpio_disable(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
737 dpio_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
738 dpio_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
744 static int dpio_exit(void)
748 err
= dpio_disable(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
750 printf("dpio_disable() failed: %d\n", err
);
754 err
= dpio_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpio
->dpio_handle
);
756 printf("dpio_destroy() failed: %d\n", err
);
761 printf("Exit: DPIO id=0x%d\n", dflt_dpio
->dpio_id
);
772 static int dprc_init(void)
774 int err
, child_portal_id
, container_id
;
776 uint64_t mc_portal_offset
;
778 /* Open root container */
779 err
= dprc_get_container_id(root_mc_io
, MC_CMD_NO_FLAGS
, &container_id
);
781 printf("dprc_get_container_id(): Root failed: %d\n", err
);
782 goto err_root_container_id
;
786 printf("Root container id = %d\n", container_id
);
788 err
= dprc_open(root_mc_io
, MC_CMD_NO_FLAGS
, container_id
,
791 printf("dprc_open(): Root Container failed: %d\n", err
);
795 if (!root_dprc_handle
) {
796 printf("dprc_open(): Root Container Handle is not valid\n");
800 cfg
.options
= DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED
|
801 DPRC_CFG_OPT_OBJ_CREATE_ALLOWED
|
802 DPRC_CFG_OPT_ALLOC_ALLOWED
;
803 cfg
.icid
= DPRC_GET_ICID_FROM_POOL
;
805 err
= dprc_create_container(root_mc_io
, MC_CMD_NO_FLAGS
,
811 printf("dprc_create_container() failed: %d\n", err
);
815 dflt_mc_io
= (struct fsl_mc_io
*)malloc(sizeof(struct fsl_mc_io
));
818 printf(" No memory: malloc() failed\n");
822 child_portal_id
= MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset
);
823 dflt_mc_io
->mmio_regs
= SOC_MC_PORTAL_ADDR(child_portal_id
);
825 printf("MC portal of child DPRC container: %d, physical addr %p)\n",
826 child_dprc_id
, dflt_mc_io
->mmio_regs
);
829 err
= dprc_open(dflt_mc_io
, MC_CMD_NO_FLAGS
, child_dprc_id
,
832 printf("dprc_open(): Child container failed: %d\n", err
);
836 if (!dflt_dprc_handle
) {
837 printf("dprc_open(): Child container Handle is not valid\n");
845 dprc_destroy_container(root_mc_io
, MC_CMD_NO_FLAGS
,
846 root_dprc_handle
, child_dprc_id
);
848 dprc_close(root_mc_io
, MC_CMD_NO_FLAGS
, root_dprc_handle
);
850 err_root_container_id
:
854 static int dprc_exit(void)
858 err
= dprc_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dprc_handle
);
860 printf("dprc_close(): Child failed: %d\n", err
);
864 err
= dprc_destroy_container(root_mc_io
, MC_CMD_NO_FLAGS
,
865 root_dprc_handle
, child_dprc_id
);
867 printf("dprc_destroy_container() failed: %d\n", err
);
871 err
= dprc_close(root_mc_io
, MC_CMD_NO_FLAGS
, root_dprc_handle
);
873 printf("dprc_close(): Root failed: %d\n", err
);
889 static int dpbp_init(void)
892 struct dpbp_attr dpbp_attr
;
893 struct dpbp_cfg dpbp_cfg
;
895 dflt_dpbp
= (struct fsl_dpbp_obj
*)malloc(sizeof(struct fsl_dpbp_obj
));
897 printf("No memory: malloc() failed\n");
902 dpbp_cfg
.options
= 512;
904 err
= dpbp_create(dflt_mc_io
, MC_CMD_NO_FLAGS
, &dpbp_cfg
,
905 &dflt_dpbp
->dpbp_handle
);
909 printf("dpbp_create() failed: %d\n", err
);
913 memset(&dpbp_attr
, 0, sizeof(struct dpbp_attr
));
914 err
= dpbp_get_attributes(dflt_mc_io
, MC_CMD_NO_FLAGS
,
915 dflt_dpbp
->dpbp_handle
,
918 printf("dpbp_get_attributes() failed: %d\n", err
);
922 dflt_dpbp
->dpbp_attr
.id
= dpbp_attr
.id
;
924 printf("Init: DPBP id=0x%d\n", dflt_dpbp
->dpbp_attr
.id
);
927 err
= dpbp_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpbp
->dpbp_handle
);
929 printf("dpbp_close() failed: %d\n", err
);
938 dpbp_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpbp
->dpbp_handle
);
939 dpbp_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpbp
->dpbp_handle
);
945 static int dpbp_exit(void)
949 err
= dpbp_open(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpbp
->dpbp_attr
.id
,
950 &dflt_dpbp
->dpbp_handle
);
952 printf("dpbp_open() failed: %d\n", err
);
956 err
= dpbp_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
,
957 dflt_dpbp
->dpbp_handle
);
959 printf("dpbp_destroy() failed: %d\n", err
);
964 printf("Exit: DPBP id=0x%d\n", dflt_dpbp
->dpbp_attr
.id
);
975 static int dpni_init(void)
978 struct dpni_attr dpni_attr
;
979 struct dpni_cfg dpni_cfg
;
981 dflt_dpni
= (struct fsl_dpni_obj
*)malloc(sizeof(struct fsl_dpni_obj
));
983 printf("No memory: malloc() failed\n");
988 memset(&dpni_cfg
, 0, sizeof(dpni_cfg
));
989 dpni_cfg
.adv
.options
= DPNI_OPT_UNICAST_FILTER
|
990 DPNI_OPT_MULTICAST_FILTER
;
992 err
= dpni_create(dflt_mc_io
, MC_CMD_NO_FLAGS
, &dpni_cfg
,
993 &dflt_dpni
->dpni_handle
);
997 printf("dpni_create() failed: %d\n", err
);
1001 memset(&dpni_attr
, 0, sizeof(struct dpni_attr
));
1002 err
= dpni_get_attributes(dflt_mc_io
, MC_CMD_NO_FLAGS
,
1003 dflt_dpni
->dpni_handle
,
1006 printf("dpni_get_attributes() failed: %d\n", err
);
1010 dflt_dpni
->dpni_id
= dpni_attr
.id
;
1012 printf("Init: DPNI id=0x%d\n", dflt_dpni
->dpni_id
);
1015 err
= dpni_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpni
->dpni_handle
);
1017 printf("dpni_close() failed: %d\n", err
);
1026 dpni_close(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpni
->dpni_handle
);
1027 dpni_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpni
->dpni_handle
);
1033 static int dpni_exit(void)
1037 err
= dpni_open(dflt_mc_io
, MC_CMD_NO_FLAGS
, dflt_dpni
->dpni_id
,
1038 &dflt_dpni
->dpni_handle
);
1040 printf("dpni_open() failed: %d\n", err
);
1044 err
= dpni_destroy(dflt_mc_io
, MC_CMD_NO_FLAGS
,
1045 dflt_dpni
->dpni_handle
);
1047 printf("dpni_destroy() failed: %d\n", err
);
1052 printf("Exit: DPNI id=0x%d\n", dflt_dpni
->dpni_id
);
1063 static int mc_init_object(void)
1069 printf("dprc_init() failed: %d\n", err
);
1075 printf("dpbp_init() failed: %d\n", err
);
1081 printf("dpio_init() failed: %d\n", err
);
1087 printf("dpni_init() failed: %d\n", err
);
1096 int fsl_mc_ldpaa_exit(bd_t
*bd
)
1100 if (bd
&& get_mc_boot_status() == -1)
1103 if (bd
&& !get_mc_boot_status() && get_dpl_apply_status() == -1) {
1104 printf("ERROR: fsl-mc: DPL is not applied\n");
1109 if (bd
&& !get_mc_boot_status() && !get_dpl_apply_status())
1114 printf("dpni_exit() failed: %d\n", err
);
1120 printf("dpio_exit() failed: %d\n", err
);
1126 printf("dpni_exit() failed: %d\n", err
);
1132 printf("dprc_exit() failed: %d\n", err
);
1141 static int do_fsl_mc(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
1147 switch (argv
[1][0]) {
1150 u64 mc_fw_addr
, mc_dpc_addr
;
1151 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1155 sub_cmd
= argv
[2][0];
1161 if (get_mc_boot_status() == 0) {
1162 printf("fsl-mc: MC is already booted");
1166 mc_fw_addr
= simple_strtoull(argv
[3], NULL
, 16);
1167 mc_dpc_addr
= simple_strtoull(argv
[4], NULL
,
1170 if (!mc_init(mc_fw_addr
, mc_dpc_addr
))
1171 err
= mc_init_object();
1174 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1178 if (get_aiop_apply_status() == 0) {
1179 printf("fsl-mc: AIOP FW is already");
1180 printf(" applied\n");
1184 aiop_fw_addr
= simple_strtoull(argv
[3], NULL
,
1187 err
= load_mc_aiop_img(aiop_fw_addr
);
1189 printf("fsl-mc: AIOP FW applied\n");
1193 printf("Invalid option: %s\n", argv
[2]);
1207 if (get_dpl_apply_status() == 0) {
1208 printf("fsl-mc: DPL already applied\n");
1212 mc_dpl_addr
= simple_strtoull(argv
[3], NULL
,
1215 if (get_mc_boot_status() != 0) {
1216 printf("fsl-mc: Deploying data path layout ..");
1217 printf("ERROR (MC is not booted)\n");
1221 if (!fsl_mc_ldpaa_exit(NULL
))
1222 err
= mc_apply_dpl(mc_dpl_addr
);
1226 printf("Invalid option: %s\n", argv
[1]);
1232 return CMD_RET_USAGE
;
1236 fsl_mc
, CONFIG_SYS_MAXARGS
, 1, do_fsl_mc
,
1237 "DPAA2 command to manage Management Complex (MC)",
1238 "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
1239 "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
1240 "fsl_mc start aiop [FW_addr] - Start AIOP\n"