drivers/net/fsl_mdio.c

   1 /*
   2  * Copyright 2009-2010 Freescale Semiconductor, Inc.
   3  *      Jun-jie Zhang <b18070@freescale.com>
   4  *      Mingkai Hu <Mingkai.hu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #include <common.h>
   9 #include <miiphy.h>
  10 #include <phy.h>
  11 #include <fsl_mdio.h>
  12 #include <asm/io.h>
  13 #include <asm/errno.h>
  14 #include <asm/fsl_enet.h>
  15
  16 void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
  17                 int dev_addr, int regnum, int value)
  18 {
  19         int timeout = 1000000;
  20
  21         out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
  22         out_be32(&phyregs->miimcon, value);
  23         asm("sync");
  24
  25         while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
  26                 ;
  27 }
  28
  29 int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
  30                 int dev_addr, int regnum)
  31 {
  32         int value;
  33         int timeout = 1000000;
  34
  35         /* Put the address of the phy, and the register
  36          * number into MIIMADD */
  37         out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
  38
  39         /* Clear the command register, and wait */
  40         out_be32(&phyregs->miimcom, 0);
  41         asm("sync");
  42
  43         /* Initiate a read command, and wait */
  44         out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
  45         asm("sync");
  46
  47         /* Wait for the the indication that the read is done */
  48         while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
  49                         && timeout--)
  50                 ;
  51
  52         /* Grab the value read from the PHY */
  53         value = in_be32(&phyregs->miimstat);
  54
  55         return value;
  56 }
  57
  58 static int fsl_pq_mdio_reset(struct mii_dev *bus)
  59 {
  60         struct tsec_mii_mng *regs = bus->priv;
  61
  62         /* Reset MII (due to new addresses) */
  63         out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
  64
  65         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
  66
  67         while (in_be32(&regs->miimind) & MIIMIND_BUSY)
  68                 ;
  69
  70         return 0;
  71 }
  72
  73 int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
  74 {
  75         struct tsec_mii_mng *phyregs = bus->priv;
  76
  77         return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
  78 }
  79
  80 int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
  81                         u16 value)
  82 {
  83         struct tsec_mii_mng *phyregs = bus->priv;
  84
  85         tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
  86
  87         return 0;
  88 }
  89
  90 int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
  91 {
  92         struct mii_dev *bus = mdio_alloc();
  93
  94         if (!bus) {
  95                 printf("Failed to allocate FSL MDIO bus\n");
  96                 return -1;
  97         }
  98
  99         bus->read = tsec_phy_read;
 100         bus->write = tsec_phy_write;
 101         bus->reset = fsl_pq_mdio_reset;
 102         sprintf(bus->name, info->name);
 103
 104         bus->priv = info->regs;
 105
 106         return mdio_register(bus);
 107 }