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Merge branch 'master' of git://git.denx.de/u-boot-video
[people/ms/u-boot.git] / drivers / net / keystone_net.c
1 /*
2 * Ethernet driver for TI K2HK EVM.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9 #include <common.h>
10 #include <command.h>
11 #include <console.h>
12
13 #include <dm.h>
14
15 #include <net.h>
16 #include <phy.h>
17 #include <errno.h>
18 #include <miiphy.h>
19 #include <malloc.h>
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
23 #include <asm/arch/psc_defs.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #ifndef CONFIG_DM_ETH
28 unsigned int emac_open;
29 static struct mii_dev *mdio_bus;
30 static unsigned int sys_has_mdio = 1;
31 #endif
32
33 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
34 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
35 #else
36 #define emac_gigabit_enable(x) /* no gigabit to enable */
37 #endif
38
39 #define RX_BUFF_NUMS 24
40 #define RX_BUFF_LEN 1520
41 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
42 #define SGMII_ANEG_TIMEOUT 4000
43
44 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
45
46 #ifndef CONFIG_DM_ETH
47 struct rx_buff_desc net_rx_buffs = {
48 .buff_ptr = rx_buffs,
49 .num_buffs = RX_BUFF_NUMS,
50 .buff_len = RX_BUFF_LEN,
51 .rx_flow = 22,
52 };
53 #endif
54
55 #ifdef CONFIG_DM_ETH
56
57 enum link_type {
58 LINK_TYPE_MAC_TO_MAC_AUTO = 0,
59 LINK_TYPE_MAC_TO_PHY_MODE = 1,
60 LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2,
61 LINK_TYPE_MAC_TO_FIBRE_MODE = 3,
62 LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4,
63 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
64 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
65 };
66
67 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
68 ((mac)[2] << 16) | ((mac)[3] << 24))
69 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
70
71 #ifdef CONFIG_KSNET_NETCP_V1_0
72
73 #define EMAC_EMACSW_BASE_OFS 0x90800
74 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
75
76 /* CPSW Switch slave registers */
77 #define CPGMACSL_REG_SA_LO 0x10
78 #define CPGMACSL_REG_SA_HI 0x14
79
80 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
81 (x) * 0x30)
82
83 #elif defined CONFIG_KSNET_NETCP_V1_5
84
85 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
86
87 /* CPSW Switch slave registers */
88 #define CPGMACSL_REG_SA_LO 0x308
89 #define CPGMACSL_REG_SA_HI 0x30c
90
91 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
92 (x) * 0x1000)
93
94 #endif
95
96
97 struct ks2_eth_priv {
98 struct udevice *dev;
99 struct phy_device *phydev;
100 struct mii_dev *mdio_bus;
101 int phy_addr;
102 phy_interface_t phy_if;
103 int sgmii_link_type;
104 void *mdio_base;
105 struct rx_buff_desc net_rx_buffs;
106 struct pktdma_cfg *netcp_pktdma;
107 void *hd;
108 int slave_port;
109 enum link_type link_type;
110 bool emac_open;
111 bool has_mdio;
112 };
113 #endif
114
115 /* MDIO */
116
117 static int keystone2_mdio_reset(struct mii_dev *bus)
118 {
119 u_int32_t clkdiv;
120 struct mdio_regs *adap_mdio = bus->priv;
121
122 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
123
124 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
125 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
126 &adap_mdio->control);
127
128 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
129 ;
130
131 return 0;
132 }
133
134 /**
135 * keystone2_mdio_read - read a PHY register via MDIO interface.
136 * Blocks until operation is complete.
137 */
138 static int keystone2_mdio_read(struct mii_dev *bus,
139 int addr, int devad, int reg)
140 {
141 int tmp;
142 struct mdio_regs *adap_mdio = bus->priv;
143
144 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
145 ;
146
147 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
148 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
149 &adap_mdio->useraccess0);
150
151 /* Wait for command to complete */
152 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
153 ;
154
155 if (tmp & MDIO_USERACCESS0_ACK)
156 return tmp & 0xffff;
157
158 return -1;
159 }
160
161 /**
162 * keystone2_mdio_write - write to a PHY register via MDIO interface.
163 * Blocks until operation is complete.
164 */
165 static int keystone2_mdio_write(struct mii_dev *bus,
166 int addr, int devad, int reg, u16 val)
167 {
168 struct mdio_regs *adap_mdio = bus->priv;
169
170 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
171 ;
172
173 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
174 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
175 (val & 0xffff), &adap_mdio->useraccess0);
176
177 /* Wait for command to complete */
178 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
179 ;
180
181 return 0;
182 }
183
184 #ifndef CONFIG_DM_ETH
185 static void __attribute__((unused))
186 keystone2_eth_gigabit_enable(struct eth_device *dev)
187 {
188 u_int16_t data;
189 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
190
191 if (sys_has_mdio) {
192 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
193 MDIO_DEVAD_NONE, 0);
194 /* speed selection MSB */
195 if (!(data & (1 << 6)))
196 return;
197 }
198
199 /*
200 * Check if link detected is giga-bit
201 * If Gigabit mode detected, enable gigbit in MAC
202 */
203 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
204 CPGMACSL_REG_CTL) |
205 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
206 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
207 }
208 #else
209 static void __attribute__((unused))
210 keystone2_eth_gigabit_enable(struct udevice *dev)
211 {
212 struct ks2_eth_priv *priv = dev_get_priv(dev);
213 u_int16_t data;
214
215 if (priv->has_mdio) {
216 data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
217 MDIO_DEVAD_NONE, 0);
218 /* speed selection MSB */
219 if (!(data & (1 << 6)))
220 return;
221 }
222
223 /*
224 * Check if link detected is giga-bit
225 * If Gigabit mode detected, enable gigbit in MAC
226 */
227 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
228 CPGMACSL_REG_CTL) |
229 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
230 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
231 }
232 #endif
233
234 #ifdef CONFIG_SOC_K2G
235 int keystone_rgmii_config(struct phy_device *phy_dev)
236 {
237 unsigned int i, status;
238
239 i = 0;
240 do {
241 if (i > SGMII_ANEG_TIMEOUT) {
242 puts(" TIMEOUT !\n");
243 phy_dev->link = 0;
244 return 0;
245 }
246
247 if (ctrlc()) {
248 puts("user interrupt!\n");
249 phy_dev->link = 0;
250 return -EINTR;
251 }
252
253 if ((i++ % 500) == 0)
254 printf(".");
255
256 udelay(1000); /* 1 ms */
257 status = readl(RGMII_STATUS_REG);
258 } while (!(status & RGMII_REG_STATUS_LINK));
259
260 puts(" done\n");
261
262 return 0;
263 }
264 #else
265 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
266 {
267 unsigned int i, status, mask;
268 unsigned int mr_adv_ability, control;
269
270 switch (interface) {
271 case SGMII_LINK_MAC_MAC_AUTONEG:
272 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
273 SGMII_REG_MR_ADV_LINK |
274 SGMII_REG_MR_ADV_FULL_DUPLEX |
275 SGMII_REG_MR_ADV_GIG_MODE);
276 control = (SGMII_REG_CONTROL_MASTER |
277 SGMII_REG_CONTROL_AUTONEG);
278
279 break;
280 case SGMII_LINK_MAC_PHY:
281 case SGMII_LINK_MAC_PHY_FORCED:
282 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
283 control = SGMII_REG_CONTROL_AUTONEG;
284
285 break;
286 case SGMII_LINK_MAC_MAC_FORCED:
287 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
288 SGMII_REG_MR_ADV_LINK |
289 SGMII_REG_MR_ADV_FULL_DUPLEX |
290 SGMII_REG_MR_ADV_GIG_MODE);
291 control = SGMII_REG_CONTROL_MASTER;
292
293 break;
294 case SGMII_LINK_MAC_FIBER:
295 mr_adv_ability = 0x20;
296 control = SGMII_REG_CONTROL_AUTONEG;
297
298 break;
299 default:
300 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
301 control = SGMII_REG_CONTROL_AUTONEG;
302 }
303
304 __raw_writel(0, SGMII_CTL_REG(port));
305
306 /*
307 * Wait for the SerDes pll to lock,
308 * but don't trap if lock is never read
309 */
310 for (i = 0; i < 1000; i++) {
311 udelay(2000);
312 status = __raw_readl(SGMII_STATUS_REG(port));
313 if ((status & SGMII_REG_STATUS_LOCK) != 0)
314 break;
315 }
316
317 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
318 __raw_writel(control, SGMII_CTL_REG(port));
319
320
321 mask = SGMII_REG_STATUS_LINK;
322
323 if (control & SGMII_REG_CONTROL_AUTONEG)
324 mask |= SGMII_REG_STATUS_AUTONEG;
325
326 status = __raw_readl(SGMII_STATUS_REG(port));
327 if ((status & mask) == mask)
328 return 0;
329
330 printf("\n%s Waiting for SGMII auto negotiation to complete",
331 phy_dev->dev->name);
332 while ((status & mask) != mask) {
333 /*
334 * Timeout reached ?
335 */
336 if (i > SGMII_ANEG_TIMEOUT) {
337 puts(" TIMEOUT !\n");
338 phy_dev->link = 0;
339 return 0;
340 }
341
342 if (ctrlc()) {
343 puts("user interrupt!\n");
344 phy_dev->link = 0;
345 return -EINTR;
346 }
347
348 if ((i++ % 500) == 0)
349 printf(".");
350
351 udelay(1000); /* 1 ms */
352 status = __raw_readl(SGMII_STATUS_REG(port));
353 }
354 puts(" done\n");
355
356 return 0;
357 }
358 #endif
359
360 int mac_sl_reset(u32 port)
361 {
362 u32 i, v;
363
364 if (port >= DEVICE_N_GMACSL_PORTS)
365 return GMACSL_RET_INVALID_PORT;
366
367 /* Set the soft reset bit */
368 writel(CPGMAC_REG_RESET_VAL_RESET,
369 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
370
371 /* Wait for the bit to clear */
372 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
373 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
374 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
375 CPGMAC_REG_RESET_VAL_RESET)
376 return GMACSL_RET_OK;
377 }
378
379 /* Timeout on the reset */
380 return GMACSL_RET_WARN_RESET_INCOMPLETE;
381 }
382
383 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
384 {
385 u32 v, i;
386 int ret = GMACSL_RET_OK;
387
388 if (port >= DEVICE_N_GMACSL_PORTS)
389 return GMACSL_RET_INVALID_PORT;
390
391 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
392 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
393 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
394 }
395
396 /* Must wait if the device is undergoing reset */
397 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
398 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
399 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
400 CPGMAC_REG_RESET_VAL_RESET)
401 break;
402 }
403
404 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
405 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
406
407 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
408 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
409
410 #ifndef CONFIG_SOC_K2HK
411 /* Map RX packet flow priority to 0 */
412 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
413 #endif
414
415 return ret;
416 }
417
418 int ethss_config(u32 ctl, u32 max_pkt_size)
419 {
420 u32 i;
421
422 /* Max length register */
423 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
424
425 /* Control register */
426 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
427
428 /* All statistics enabled by default */
429 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
430 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
431
432 /* Reset and enable the ALE */
433 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
434 CPSW_REG_VAL_ALE_CTL_BYPASS,
435 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
436
437 /* All ports put into forward mode */
438 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
439 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
440 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
441
442 return 0;
443 }
444
445 int ethss_start(void)
446 {
447 int i;
448 struct mac_sl_cfg cfg;
449
450 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
451 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
452
453 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
454 mac_sl_reset(i);
455 mac_sl_config(i, &cfg);
456 }
457
458 return 0;
459 }
460
461 int ethss_stop(void)
462 {
463 int i;
464
465 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
466 mac_sl_reset(i);
467
468 return 0;
469 }
470
471 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
472 .clk = SERDES_CLOCK_156P25M,
473 .rate = SERDES_RATE_5G,
474 .rate_mode = SERDES_QUARTER_RATE,
475 .intf = SERDES_PHY_SGMII,
476 .loopback = 0,
477 };
478
479 #ifndef CONFIG_SOC_K2G
480 static void keystone2_net_serdes_setup(void)
481 {
482 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
483 &ks2_serdes_sgmii_156p25mhz,
484 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
485
486 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
487 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
488 &ks2_serdes_sgmii_156p25mhz,
489 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
490 #endif
491
492 /* wait till setup */
493 udelay(5000);
494 }
495 #endif
496
497 #ifndef CONFIG_DM_ETH
498
499 int keystone2_eth_read_mac_addr(struct eth_device *dev)
500 {
501 struct eth_priv_t *eth_priv;
502 u32 maca = 0;
503 u32 macb = 0;
504
505 eth_priv = (struct eth_priv_t *)dev->priv;
506
507 /* Read the e-fuse mac address */
508 if (eth_priv->slave_port == 1) {
509 maca = __raw_readl(MAC_ID_BASE_ADDR);
510 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
511 }
512
513 dev->enetaddr[0] = (macb >> 8) & 0xff;
514 dev->enetaddr[1] = (macb >> 0) & 0xff;
515 dev->enetaddr[2] = (maca >> 24) & 0xff;
516 dev->enetaddr[3] = (maca >> 16) & 0xff;
517 dev->enetaddr[4] = (maca >> 8) & 0xff;
518 dev->enetaddr[5] = (maca >> 0) & 0xff;
519
520 return 0;
521 }
522
523 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
524 {
525 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
526 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
527
528 return ksnav_send(&netcp_pktdma, buffer,
529 num_bytes, (slave_port_num) << 16);
530 }
531
532 /* Eth device open */
533 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
534 {
535 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
536 struct phy_device *phy_dev = eth_priv->phy_dev;
537
538 debug("+ emac_open\n");
539
540 net_rx_buffs.rx_flow = eth_priv->rx_flow;
541
542 sys_has_mdio =
543 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
544
545 if (sys_has_mdio)
546 keystone2_mdio_reset(mdio_bus);
547
548 #ifdef CONFIG_SOC_K2G
549 keystone_rgmii_config(phy_dev);
550 #else
551 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
552 eth_priv->sgmii_link_type);
553 #endif
554
555 udelay(10000);
556
557 /* On chip switch configuration */
558 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
559
560 /* TODO: add error handling code */
561 if (qm_init()) {
562 printf("ERROR: qm_init()\n");
563 return -1;
564 }
565 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
566 qm_close();
567 printf("ERROR: netcp_init()\n");
568 return -1;
569 }
570
571 /*
572 * Streaming switch configuration. If not present this
573 * statement is defined to void in target.h.
574 * If present this is usually defined to a series of register writes
575 */
576 hw_config_streaming_switch();
577
578 if (sys_has_mdio) {
579 keystone2_mdio_reset(mdio_bus);
580
581 phy_startup(phy_dev);
582 if (phy_dev->link == 0) {
583 ksnav_close(&netcp_pktdma);
584 qm_close();
585 return -1;
586 }
587 }
588
589 emac_gigabit_enable(dev);
590
591 ethss_start();
592
593 debug("- emac_open\n");
594
595 emac_open = 1;
596
597 return 0;
598 }
599
600 /* Eth device close */
601 void keystone2_eth_close(struct eth_device *dev)
602 {
603 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
604 struct phy_device *phy_dev = eth_priv->phy_dev;
605
606 debug("+ emac_close\n");
607
608 if (!emac_open)
609 return;
610
611 ethss_stop();
612
613 ksnav_close(&netcp_pktdma);
614 qm_close();
615 phy_shutdown(phy_dev);
616
617 emac_open = 0;
618
619 debug("- emac_close\n");
620 }
621
622 /*
623 * This function sends a single packet on the network and returns
624 * positive number (number of bytes transmitted) or negative for error
625 */
626 static int keystone2_eth_send_packet(struct eth_device *dev,
627 void *packet, int length)
628 {
629 int ret_status = -1;
630 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
631 struct phy_device *phy_dev = eth_priv->phy_dev;
632
633 genphy_update_link(phy_dev);
634 if (phy_dev->link == 0)
635 return -1;
636
637 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
638 return ret_status;
639
640 return length;
641 }
642
643 /*
644 * This function handles receipt of a packet from the network
645 */
646 static int keystone2_eth_rcv_packet(struct eth_device *dev)
647 {
648 void *hd;
649 int pkt_size;
650 u32 *pkt;
651
652 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
653 if (hd == NULL)
654 return 0;
655
656 net_process_received_packet((uchar *)pkt, pkt_size);
657
658 ksnav_release_rxhd(&netcp_pktdma, hd);
659
660 return pkt_size;
661 }
662
663 #ifdef CONFIG_MCAST_TFTP
664 static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
665 {
666 return 0;
667 }
668 #endif
669
670 /*
671 * This function initializes the EMAC hardware.
672 */
673 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
674 {
675 int res;
676 struct eth_device *dev;
677 struct phy_device *phy_dev;
678 struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
679
680 dev = malloc(sizeof(struct eth_device));
681 if (dev == NULL)
682 return -1;
683
684 memset(dev, 0, sizeof(struct eth_device));
685
686 strcpy(dev->name, eth_priv->int_name);
687 dev->priv = eth_priv;
688
689 keystone2_eth_read_mac_addr(dev);
690
691 dev->iobase = 0;
692 dev->init = keystone2_eth_open;
693 dev->halt = keystone2_eth_close;
694 dev->send = keystone2_eth_send_packet;
695 dev->recv = keystone2_eth_rcv_packet;
696 #ifdef CONFIG_MCAST_TFTP
697 dev->mcast = keystone2_eth_bcast_addr;
698 #endif
699
700 eth_register(dev);
701
702 /* Register MDIO bus if it's not registered yet */
703 if (!mdio_bus) {
704 mdio_bus = mdio_alloc();
705 mdio_bus->read = keystone2_mdio_read;
706 mdio_bus->write = keystone2_mdio_write;
707 mdio_bus->reset = keystone2_mdio_reset;
708 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
709 strcpy(mdio_bus->name, "ethernet-mdio");
710
711 res = mdio_register(mdio_bus);
712 if (res)
713 return res;
714 }
715
716 #ifndef CONFIG_SOC_K2G
717 keystone2_net_serdes_setup();
718 #endif
719
720 /* Create phy device and bind it with driver */
721 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
722 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
723 dev, eth_priv->phy_if);
724 phy_config(phy_dev);
725 #else
726 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
727 eth_priv->phy_if);
728 phy_dev->dev = dev;
729 #endif
730 eth_priv->phy_dev = phy_dev;
731
732 return 0;
733 }
734
735 #else
736
737 static int ks2_eth_start(struct udevice *dev)
738 {
739 struct ks2_eth_priv *priv = dev_get_priv(dev);
740
741 #ifdef CONFIG_SOC_K2G
742 keystone_rgmii_config(priv->phydev);
743 #else
744 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
745 priv->sgmii_link_type);
746 #endif
747
748 udelay(10000);
749
750 /* On chip switch configuration */
751 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
752
753 qm_init();
754
755 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
756 error("ksnav_init failed\n");
757 goto err_knav_init;
758 }
759
760 /*
761 * Streaming switch configuration. If not present this
762 * statement is defined to void in target.h.
763 * If present this is usually defined to a series of register writes
764 */
765 hw_config_streaming_switch();
766
767 if (priv->has_mdio) {
768 phy_startup(priv->phydev);
769 if (priv->phydev->link == 0) {
770 error("phy startup failed\n");
771 goto err_phy_start;
772 }
773 }
774
775 emac_gigabit_enable(dev);
776
777 ethss_start();
778
779 priv->emac_open = true;
780
781 return 0;
782
783 err_phy_start:
784 ksnav_close(priv->netcp_pktdma);
785 err_knav_init:
786 qm_close();
787
788 return -EFAULT;
789 }
790
791 static int ks2_eth_send(struct udevice *dev, void *packet, int length)
792 {
793 struct ks2_eth_priv *priv = dev_get_priv(dev);
794
795 genphy_update_link(priv->phydev);
796 if (priv->phydev->link == 0)
797 return -1;
798
799 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
800 length = EMAC_MIN_ETHERNET_PKT_SIZE;
801
802 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
803 length, (priv->slave_port) << 16);
804 }
805
806 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
807 {
808 struct ks2_eth_priv *priv = dev_get_priv(dev);
809 int pkt_size;
810 u32 *pkt = NULL;
811
812 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
813 if (priv->hd == NULL)
814 return -EAGAIN;
815
816 *packetp = (uchar *)pkt;
817
818 return pkt_size;
819 }
820
821 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
822 int length)
823 {
824 struct ks2_eth_priv *priv = dev_get_priv(dev);
825
826 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
827
828 return 0;
829 }
830
831 static void ks2_eth_stop(struct udevice *dev)
832 {
833 struct ks2_eth_priv *priv = dev_get_priv(dev);
834
835 if (!priv->emac_open)
836 return;
837 ethss_stop();
838
839 ksnav_close(priv->netcp_pktdma);
840 qm_close();
841 phy_shutdown(priv->phydev);
842 priv->emac_open = false;
843 }
844
845 int ks2_eth_read_rom_hwaddr(struct udevice *dev)
846 {
847 struct ks2_eth_priv *priv = dev_get_priv(dev);
848 struct eth_pdata *pdata = dev_get_platdata(dev);
849 u32 maca = 0;
850 u32 macb = 0;
851
852 /* Read the e-fuse mac address */
853 if (priv->slave_port == 1) {
854 maca = __raw_readl(MAC_ID_BASE_ADDR);
855 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
856 }
857
858 pdata->enetaddr[0] = (macb >> 8) & 0xff;
859 pdata->enetaddr[1] = (macb >> 0) & 0xff;
860 pdata->enetaddr[2] = (maca >> 24) & 0xff;
861 pdata->enetaddr[3] = (maca >> 16) & 0xff;
862 pdata->enetaddr[4] = (maca >> 8) & 0xff;
863 pdata->enetaddr[5] = (maca >> 0) & 0xff;
864
865 return 0;
866 }
867
868 int ks2_eth_write_hwaddr(struct udevice *dev)
869 {
870 struct ks2_eth_priv *priv = dev_get_priv(dev);
871 struct eth_pdata *pdata = dev_get_platdata(dev);
872
873 writel(mac_hi(pdata->enetaddr),
874 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
875 CPGMACSL_REG_SA_HI);
876 writel(mac_lo(pdata->enetaddr),
877 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
878 CPGMACSL_REG_SA_LO);
879
880 return 0;
881 }
882
883 static int ks2_eth_probe(struct udevice *dev)
884 {
885 struct ks2_eth_priv *priv = dev_get_priv(dev);
886 struct mii_dev *mdio_bus;
887 int ret;
888
889 priv->dev = dev;
890
891 /* These clock enables has to be moved to common location */
892 if (cpu_is_k2g())
893 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
894
895 /* By default, select PA PLL clock as PA clock source */
896 #ifndef CONFIG_SOC_K2G
897 if (psc_enable_module(KS2_LPSC_PA))
898 return -EACCES;
899 #endif
900 if (psc_enable_module(KS2_LPSC_CPGMAC))
901 return -EACCES;
902 if (psc_enable_module(KS2_LPSC_CRYPTO))
903 return -EACCES;
904
905 if (cpu_is_k2e() || cpu_is_k2l())
906 pll_pa_clk_sel();
907
908
909 priv->net_rx_buffs.buff_ptr = rx_buffs,
910 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS,
911 priv->net_rx_buffs.buff_len = RX_BUFF_LEN,
912
913 /* Register MDIO bus */
914 mdio_bus = mdio_alloc();
915 if (!mdio_bus) {
916 error("MDIO alloc failed\n");
917 return -ENOMEM;
918 }
919 priv->mdio_bus = mdio_bus;
920 mdio_bus->read = keystone2_mdio_read;
921 mdio_bus->write = keystone2_mdio_write;
922 mdio_bus->reset = keystone2_mdio_reset;
923 mdio_bus->priv = priv->mdio_base;
924 sprintf(mdio_bus->name, "ethernet-mdio");
925
926 ret = mdio_register(mdio_bus);
927 if (ret) {
928 error("MDIO bus register failed\n");
929 return ret;
930 }
931
932 #ifndef CONFIG_SOC_K2G
933 keystone2_net_serdes_setup();
934 #endif
935
936 priv->netcp_pktdma = &netcp_pktdma;
937
938 priv->phydev = phy_connect(mdio_bus, priv->phy_addr, dev, priv->phy_if);
939 phy_config(priv->phydev);
940
941 return 0;
942 }
943
944 int ks2_eth_remove(struct udevice *dev)
945 {
946 struct ks2_eth_priv *priv = dev_get_priv(dev);
947
948 free(priv->phydev);
949 mdio_unregister(priv->mdio_bus);
950 mdio_free(priv->mdio_bus);
951
952 return 0;
953 }
954
955 static const struct eth_ops ks2_eth_ops = {
956 .start = ks2_eth_start,
957 .send = ks2_eth_send,
958 .recv = ks2_eth_recv,
959 .free_pkt = ks2_eth_free_pkt,
960 .stop = ks2_eth_stop,
961 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
962 .write_hwaddr = ks2_eth_write_hwaddr,
963 };
964
965
966 static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
967 {
968 struct ks2_eth_priv *priv = dev_get_priv(dev);
969 struct eth_pdata *pdata = dev_get_platdata(dev);
970 const void *fdt = gd->fdt_blob;
971 int interfaces;
972 int interface_0;
973 int netcp_gbe_0;
974 int phy;
975 int mdio;
976 u32 dma_channel[6];
977
978 interfaces = fdt_subnode_offset(fdt, dev->of_offset,
979 "netcp-interfaces");
980 interface_0 = fdt_subnode_offset(fdt, interfaces, "interface-0");
981
982 netcp_gbe_0 = fdtdec_lookup_phandle(fdt, interface_0, "netcp-gbe");
983 priv->link_type = fdtdec_get_int(fdt, netcp_gbe_0,
984 "link-interface", -1);
985 priv->slave_port = fdtdec_get_int(fdt, netcp_gbe_0, "slave-port", -1);
986 /* U-Boot slave port number starts with 1 instead of 0 */
987 priv->slave_port += 1;
988
989 phy = fdtdec_lookup_phandle(fdt, netcp_gbe_0, "phy-handle");
990 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
991
992 mdio = fdt_parent_offset(fdt, phy);
993 if (mdio < 0) {
994 error("mdio dt not found\n");
995 return -ENODEV;
996 }
997 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
998
999 if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) {
1000 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
1001 pdata->phy_interface = priv->phy_if;
1002 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
1003 priv->has_mdio = true;
1004 }
1005 pdata->iobase = dev_get_addr(dev);
1006
1007 fdtdec_get_int_array(fdt, dev->of_offset, "ti,navigator-dmas",
1008 dma_channel, 6);
1009 priv->net_rx_buffs.rx_flow = dma_channel[1];
1010
1011 return 0;
1012 }
1013
1014 static const struct udevice_id ks2_eth_ids[] = {
1015 { .compatible = "ti,netcp-1.0" },
1016 { }
1017 };
1018
1019
1020 U_BOOT_DRIVER(eth_ks2) = {
1021 .name = "eth_ks2",
1022 .id = UCLASS_ETH,
1023 .of_match = ks2_eth_ids,
1024 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
1025 .probe = ks2_eth_probe,
1026 .remove = ks2_eth_remove,
1027 .ops = &ks2_eth_ops,
1028 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1029 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1030 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1031 };
1032 #endif
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