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net: removed board-specific CONFIGs from MPC5xxx FEC driver
[people/ms/u-boot.git] / drivers / net / mpc5xxx_fec.c
1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <mpc5xxx_sdma.h>
12 #include <malloc.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <miiphy.h>
16 #include "mpc5xxx_fec.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* #define DEBUG 0x28 */
21
22 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
23 #error "CONFIG_MII has to be defined!"
24 #endif
25
26 #if (DEBUG & 0x60)
27 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
29 #endif /* DEBUG */
30
31 #if (DEBUG & 0x40)
32 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
33 #endif
34
35 typedef struct {
36 uint8 data[1500]; /* actual data */
37 int length; /* actual length */
38 int used; /* buffer in use or not */
39 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
40 } NBUF;
41
42 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
43 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
44
45 /********************************************************************/
46 #if (DEBUG & 0x2)
47 static void mpc5xxx_fec_phydump (char *devname)
48 {
49 uint16 phyStatus, i;
50 uint8 phyAddr = CONFIG_PHY_ADDR;
51 uint8 reg_mask[] = {
52 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
53 /* regs to print: 0...7, 16...19, 21, 23, 24 */
54 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
55 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
56 #else
57 /* regs to print: 0...8, 16...20 */
58 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
60 #endif
61 };
62
63 for (i = 0; i < 32; i++) {
64 if (reg_mask[i]) {
65 miiphy_read(devname, phyAddr, i, &phyStatus);
66 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
67 }
68 }
69 }
70 #endif
71
72 /********************************************************************/
73 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
74 {
75 int ix;
76 char *data;
77 static int once = 0;
78
79 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
80 if (!once) {
81 data = (char *)malloc(FEC_MAX_PKT_SIZE);
82 if (data == NULL) {
83 printf ("RBD INIT FAILED\n");
84 return -1;
85 }
86 fec->rbdBase[ix].dataPointer = (uint32)data;
87 }
88 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
89 fec->rbdBase[ix].dataLength = 0;
90 }
91 once ++;
92
93 /*
94 * have the last RBD to close the ring
95 */
96 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
97 fec->rbdIndex = 0;
98
99 return 0;
100 }
101
102 /********************************************************************/
103 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
104 {
105 int ix;
106
107 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
108 fec->tbdBase[ix].status = 0;
109 }
110
111 /*
112 * Have the last TBD to close the ring
113 */
114 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
115
116 /*
117 * Initialize some indices
118 */
119 fec->tbdIndex = 0;
120 fec->usedTbdIndex = 0;
121 fec->cleanTbdNum = FEC_TBD_NUM;
122 }
123
124 /********************************************************************/
125 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
126 {
127 /*
128 * Reset buffer descriptor as empty
129 */
130 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
131 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
132 else
133 pRbd->status = FEC_RBD_EMPTY;
134
135 pRbd->dataLength = 0;
136
137 /*
138 * Now, we have an empty RxBD, restart the SmartDMA receive task
139 */
140 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
141
142 /*
143 * Increment BD count
144 */
145 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
146 }
147
148 /********************************************************************/
149 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
150 {
151 volatile FEC_TBD *pUsedTbd;
152
153 #if (DEBUG & 0x1)
154 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
155 fec->cleanTbdNum, fec->usedTbdIndex);
156 #endif
157
158 /*
159 * process all the consumed TBDs
160 */
161 while (fec->cleanTbdNum < FEC_TBD_NUM) {
162 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
163 if (pUsedTbd->status & FEC_TBD_READY) {
164 #if (DEBUG & 0x20)
165 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
166 #endif
167 return;
168 }
169
170 /*
171 * clean this buffer descriptor
172 */
173 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
174 pUsedTbd->status = FEC_TBD_WRAP;
175 else
176 pUsedTbd->status = 0;
177
178 /*
179 * update some indeces for a correct handling of the TBD ring
180 */
181 fec->cleanTbdNum++;
182 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
183 }
184 }
185
186 /********************************************************************/
187 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
188 {
189 uint8 currByte; /* byte for which to compute the CRC */
190 int byte; /* loop - counter */
191 int bit; /* loop - counter */
192 uint32 crc = 0xffffffff; /* initial value */
193
194 /*
195 * The algorithm used is the following:
196 * we loop on each of the six bytes of the provided address,
197 * and we compute the CRC by left-shifting the previous
198 * value by one position, so that each bit in the current
199 * byte of the address may contribute the calculation. If
200 * the latter and the MSB in the CRC are different, then
201 * the CRC value so computed is also ex-ored with the
202 * "polynomium generator". The current byte of the address
203 * is also shifted right by one bit at each iteration.
204 * This is because the CRC generatore in hardware is implemented
205 * as a shift-register with as many ex-ores as the radixes
206 * in the polynomium. This suggests that we represent the
207 * polynomiumm itself as a 32-bit constant.
208 */
209 for (byte = 0; byte < 6; byte++) {
210 currByte = mac[byte];
211 for (bit = 0; bit < 8; bit++) {
212 if ((currByte & 0x01) ^ (crc & 0x01)) {
213 crc >>= 1;
214 crc = crc ^ 0xedb88320;
215 } else {
216 crc >>= 1;
217 }
218 currByte >>= 1;
219 }
220 }
221
222 crc = crc >> 26;
223
224 /*
225 * Set individual hash table register
226 */
227 if (crc >= 32) {
228 fec->eth->iaddr1 = (1 << (crc - 32));
229 fec->eth->iaddr2 = 0;
230 } else {
231 fec->eth->iaddr1 = 0;
232 fec->eth->iaddr2 = (1 << crc);
233 }
234
235 /*
236 * Set physical address
237 */
238 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
239 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
240 }
241
242 /********************************************************************/
243 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
244 {
245 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
246 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
247
248 #if (DEBUG & 0x1)
249 printf ("mpc5xxx_fec_init... Begin\n");
250 #endif
251
252 /*
253 * Initialize RxBD/TxBD rings
254 */
255 mpc5xxx_fec_rbd_init(fec);
256 mpc5xxx_fec_tbd_init(fec);
257
258 /*
259 * Clear FEC-Lite interrupt event register(IEVENT)
260 */
261 fec->eth->ievent = 0xffffffff;
262
263 /*
264 * Set interrupt mask register
265 */
266 fec->eth->imask = 0x00000000;
267
268 /*
269 * Set FEC-Lite receive control register(R_CNTRL):
270 */
271 if (fec->xcv_type == SEVENWIRE) {
272 /*
273 * Frame length=1518; 7-wire mode
274 */
275 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
276 } else {
277 /*
278 * Frame length=1518; MII mode;
279 */
280 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
281 }
282
283 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
284 if (fec->xcv_type != SEVENWIRE) {
285 /*
286 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
287 * and do not drop the Preamble.
288 */
289 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
290 }
291
292 /*
293 * Set Opcode/Pause Duration Register
294 */
295 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
296
297 /*
298 * Set Rx FIFO alarm and granularity value
299 */
300 fec->eth->rfifo_cntrl = 0x0c000000
301 | (fec->eth->rfifo_cntrl & ~0x0f000000);
302 fec->eth->rfifo_alarm = 0x0000030c;
303 #if (DEBUG & 0x22)
304 if (fec->eth->rfifo_status & 0x00700000 ) {
305 printf("mpc5xxx_fec_init() RFIFO error\n");
306 }
307 #endif
308
309 /*
310 * Set Tx FIFO granularity value
311 */
312 fec->eth->tfifo_cntrl = 0x0c000000
313 | (fec->eth->tfifo_cntrl & ~0x0f000000);
314 #if (DEBUG & 0x2)
315 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
316 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
317 #endif
318
319 /*
320 * Set transmit fifo watermark register(X_WMRK), default = 64
321 */
322 fec->eth->tfifo_alarm = 0x00000080;
323 fec->eth->x_wmrk = 0x2;
324
325 /*
326 * Set individual address filter for unicast address
327 * and set physical address registers.
328 */
329 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
330
331 /*
332 * Set multicast address filter
333 */
334 fec->eth->gaddr1 = 0x00000000;
335 fec->eth->gaddr2 = 0x00000000;
336
337 /*
338 * Turn ON cheater FSM: ????
339 */
340 fec->eth->xmit_fsm = 0x03000000;
341
342 #if defined(CONFIG_MPC5200)
343 /*
344 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
345 * work w/ the current receive task.
346 */
347 sdma->PtdCntrl |= 0x00000001;
348 #endif
349
350 /*
351 * Set priority of different initiators
352 */
353 sdma->IPR0 = 7; /* always */
354 sdma->IPR3 = 6; /* Eth RX */
355 sdma->IPR4 = 5; /* Eth Tx */
356
357 /*
358 * Clear SmartDMA task interrupt pending bits
359 */
360 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
361
362 /*
363 * Initialize SmartDMA parameters stored in SRAM
364 */
365 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
366 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
367 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
369
370 /*
371 * Enable FEC-Lite controller
372 */
373 fec->eth->ecntrl |= 0x00000006;
374
375 #if (DEBUG & 0x2)
376 if (fec->xcv_type != SEVENWIRE)
377 mpc5xxx_fec_phydump (dev->name);
378 #endif
379
380 /*
381 * Enable SmartDMA receive task
382 */
383 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
384
385 #if (DEBUG & 0x1)
386 printf("mpc5xxx_fec_init... Done \n");
387 #endif
388
389 return 1;
390 }
391
392 /********************************************************************/
393 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
394 {
395 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
396 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
397
398 #if (DEBUG & 0x1)
399 printf ("mpc5xxx_fec_init_phy... Begin\n");
400 #endif
401
402 /*
403 * Initialize GPIO pins
404 */
405 if (fec->xcv_type == SEVENWIRE) {
406 /* 10MBit with 7-wire operation */
407 #if defined(CONFIG_TOTAL5200)
408 /* 7-wire and USB2 on Ethernet */
409 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
410 #else /* !CONFIG_TOTAL5200 */
411 /* 7-wire only */
412 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
413 #endif /* CONFIG_TOTAL5200 */
414 } else {
415 /* 100MBit with MD operation */
416 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
417 }
418
419 /*
420 * Clear FEC-Lite interrupt event register(IEVENT)
421 */
422 fec->eth->ievent = 0xffffffff;
423
424 /*
425 * Set interrupt mask register
426 */
427 fec->eth->imask = 0x00000000;
428
429 /*
430 * In original Promess-provided code PHY initialization is disabled with the
431 * following comment: "Phy initialization is DISABLED for now. There was a
432 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
433 * PHY initialization for the Motion-PRO board, until a proper fix is found.
434 */
435
436 if (fec->xcv_type != SEVENWIRE) {
437 /*
438 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
439 * and do not drop the Preamble.
440 */
441 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
442 }
443
444 if (fec->xcv_type != SEVENWIRE) {
445 /*
446 * Initialize PHY(LXT971A):
447 *
448 * Generally, on power up, the LXT971A reads its configuration
449 * pins to check for forced operation, If not cofigured for
450 * forced operation, it uses auto-negotiation/parallel detection
451 * to automatically determine line operating conditions.
452 * If the PHY device on the other side of the link supports
453 * auto-negotiation, the LXT971A auto-negotiates with it
454 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
455 * support auto-negotiation, the LXT971A automatically detects
456 * the presence of either link pulses(10Mbps PHY) or Idle
457 * symbols(100Mbps) and sets its operating conditions accordingly.
458 *
459 * When auto-negotiation is controlled by software, the following
460 * steps are recommended.
461 *
462 * Note:
463 * The physical address is dependent on hardware configuration.
464 *
465 */
466 int timeout = 1;
467 uint16 phyStatus;
468
469 /*
470 * Reset PHY, then delay 300ns
471 */
472 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
473 udelay(1000);
474
475 #if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
476 /* Set the LED configuration Register for the UC101
477 and MUCMC52 Board */
478 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
479 #endif
480 if (fec->xcv_type == MII10) {
481 /*
482 * Force 10Base-T, FDX operation
483 */
484 #if (DEBUG & 0x2)
485 printf("Forcing 10 Mbps ethernet link... ");
486 #endif
487 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
488 /*
489 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
490 */
491 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
492
493 timeout = 20;
494 do { /* wait for link status to go down */
495 udelay(10000);
496 if ((timeout--) == 0) {
497 #if (DEBUG & 0x2)
498 printf("hmmm, should not have waited...");
499 #endif
500 break;
501 }
502 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
503 #if (DEBUG & 0x2)
504 printf("=");
505 #endif
506 } while ((phyStatus & 0x0004)); /* !link up */
507
508 timeout = 1000;
509 do { /* wait for link status to come back up */
510 udelay(10000);
511 if ((timeout--) == 0) {
512 printf("failed. Link is down.\n");
513 break;
514 }
515 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
516 #if (DEBUG & 0x2)
517 printf("+");
518 #endif
519 } while (!(phyStatus & 0x0004)); /* !link up */
520
521 #if (DEBUG & 0x2)
522 printf ("done.\n");
523 #endif
524 } else { /* MII100 */
525 /*
526 * Set the auto-negotiation advertisement register bits
527 */
528 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
529
530 /*
531 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
532 */
533 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
534
535 /*
536 * Wait for AN completion
537 */
538 timeout = 5000;
539 do {
540 udelay(1000);
541
542 if ((timeout--) == 0) {
543 #if (DEBUG & 0x2)
544 printf("PHY auto neg 0 failed...\n");
545 #endif
546 return -1;
547 }
548
549 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
550 #if (DEBUG & 0x2)
551 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
552 #endif
553 return -1;
554 }
555 } while (!(phyStatus & 0x0004));
556
557 #if (DEBUG & 0x2)
558 printf("PHY auto neg complete! \n");
559 #endif
560 }
561
562 }
563
564 #if (DEBUG & 0x2)
565 if (fec->xcv_type != SEVENWIRE)
566 mpc5xxx_fec_phydump (dev->name);
567 #endif
568
569
570 #if (DEBUG & 0x1)
571 printf("mpc5xxx_fec_init_phy... Done \n");
572 #endif
573
574 return 1;
575 }
576
577 /********************************************************************/
578 static void mpc5xxx_fec_halt(struct eth_device *dev)
579 {
580 #if defined(CONFIG_MPC5200)
581 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
582 #endif
583 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
584 int counter = 0xffff;
585
586 #if (DEBUG & 0x2)
587 if (fec->xcv_type != SEVENWIRE)
588 mpc5xxx_fec_phydump (dev->name);
589 #endif
590
591 /*
592 * mask FEC chip interrupts
593 */
594 fec->eth->imask = 0;
595
596 /*
597 * issue graceful stop command to the FEC transmitter if necessary
598 */
599 fec->eth->x_cntrl |= 0x00000001;
600
601 /*
602 * wait for graceful stop to register
603 */
604 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
605
606 /*
607 * Disable SmartDMA tasks
608 */
609 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
610 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
611
612 #if defined(CONFIG_MPC5200)
613 /*
614 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
615 * done. It doesn't work w/ the current receive task.
616 */
617 sdma->PtdCntrl &= ~0x00000001;
618 #endif
619
620 /*
621 * Disable the Ethernet Controller
622 */
623 fec->eth->ecntrl &= 0xfffffffd;
624
625 /*
626 * Clear FIFO status registers
627 */
628 fec->eth->rfifo_status &= 0x00700000;
629 fec->eth->tfifo_status &= 0x00700000;
630
631 fec->eth->reset_cntrl = 0x01000000;
632
633 /*
634 * Issue a reset command to the FEC chip
635 */
636 fec->eth->ecntrl |= 0x1;
637
638 /*
639 * wait at least 16 clock cycles
640 */
641 udelay(10);
642
643 #if (DEBUG & 0x3)
644 printf("Ethernet task stopped\n");
645 #endif
646 }
647
648 #if (DEBUG & 0x60)
649 /********************************************************************/
650
651 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
652 {
653 uint16 phyAddr = CONFIG_PHY_ADDR;
654 uint16 phyStatus;
655
656 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
657 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
658
659 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
660 printf("\nphyStatus: 0x%04x\n", phyStatus);
661 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
662 printf("ievent: 0x%08x\n", fec->eth->ievent);
663 printf("x_status: 0x%08x\n", fec->eth->x_status);
664 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
665
666 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
667 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
668 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
669 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
670 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
671 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
672 }
673 }
674
675 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
676 {
677 uint16 phyAddr = CONFIG_PHY_ADDR;
678 uint16 phyStatus;
679
680 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
681 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
682
683 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
684 printf("\nphyStatus: 0x%04x\n", phyStatus);
685 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
686 printf("ievent: 0x%08x\n", fec->eth->ievent);
687 printf("x_status: 0x%08x\n", fec->eth->x_status);
688 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
689
690 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
691 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
692 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
693 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
694 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
695 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
696 }
697 }
698 #endif /* DEBUG */
699
700 /********************************************************************/
701
702 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
703 int data_length)
704 {
705 /*
706 * This routine transmits one frame. This routine only accepts
707 * 6-byte Ethernet addresses.
708 */
709 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
710 volatile FEC_TBD *pTbd;
711
712 #if (DEBUG & 0x20)
713 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
714 tfifo_print(dev->name, fec);
715 #endif
716
717 /*
718 * Clear Tx BD ring at first
719 */
720 mpc5xxx_fec_tbd_scrub(fec);
721
722 /*
723 * Check for valid length of data.
724 */
725 if ((data_length > 1500) || (data_length <= 0)) {
726 return -1;
727 }
728
729 /*
730 * Check the number of vacant TxBDs.
731 */
732 if (fec->cleanTbdNum < 1) {
733 #if (DEBUG & 0x20)
734 printf("No available TxBDs ...\n");
735 #endif
736 return -1;
737 }
738
739 /*
740 * Get the first TxBD to send the mac header
741 */
742 pTbd = &fec->tbdBase[fec->tbdIndex];
743 pTbd->dataLength = data_length;
744 pTbd->dataPointer = (uint32)eth_data;
745 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
746 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
747
748 #if (DEBUG & 0x100)
749 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
750 #endif
751
752 /*
753 * Kick the MII i/f
754 */
755 if (fec->xcv_type != SEVENWIRE) {
756 uint16 phyStatus;
757 miiphy_read(dev->name, 0, 0x1, &phyStatus);
758 }
759
760 /*
761 * Enable SmartDMA transmit task
762 */
763
764 #if (DEBUG & 0x20)
765 tfifo_print(dev->name, fec);
766 #endif
767 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
768 #if (DEBUG & 0x20)
769 tfifo_print(dev->name, fec);
770 #endif
771 #if (DEBUG & 0x8)
772 printf( "+" );
773 #endif
774
775 fec->cleanTbdNum -= 1;
776
777 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
778 printf ("smartDMA ethernet Tx task enabled\n");
779 #endif
780 /*
781 * wait until frame is sent .
782 */
783 while (pTbd->status & FEC_TBD_READY) {
784 udelay(10);
785 #if (DEBUG & 0x8)
786 printf ("TDB status = %04x\n", pTbd->status);
787 #endif
788 }
789
790 return 0;
791 }
792
793
794 /********************************************************************/
795 static int mpc5xxx_fec_recv(struct eth_device *dev)
796 {
797 /*
798 * This command pulls one frame from the card
799 */
800 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
801 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
802 unsigned long ievent;
803 int frame_length, len = 0;
804 NBUF *frame;
805 uchar buff[FEC_MAX_PKT_SIZE];
806
807 #if (DEBUG & 0x1)
808 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
809 #endif
810 #if (DEBUG & 0x8)
811 printf( "-" );
812 #endif
813
814 /*
815 * Check if any critical events have happened
816 */
817 ievent = fec->eth->ievent;
818 fec->eth->ievent = ievent;
819 if (ievent & 0x20060000) {
820 /* BABT, Rx/Tx FIFO errors */
821 mpc5xxx_fec_halt(dev);
822 mpc5xxx_fec_init(dev, NULL);
823 return 0;
824 }
825 if (ievent & 0x80000000) {
826 /* Heartbeat error */
827 fec->eth->x_cntrl |= 0x00000001;
828 }
829 if (ievent & 0x10000000) {
830 /* Graceful stop complete */
831 if (fec->eth->x_cntrl & 0x00000001) {
832 mpc5xxx_fec_halt(dev);
833 fec->eth->x_cntrl &= ~0x00000001;
834 mpc5xxx_fec_init(dev, NULL);
835 }
836 }
837
838 if (!(pRbd->status & FEC_RBD_EMPTY)) {
839 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
840 ((pRbd->dataLength - 4) > 14)) {
841
842 /*
843 * Get buffer address and size
844 */
845 frame = (NBUF *)pRbd->dataPointer;
846 frame_length = pRbd->dataLength - 4;
847
848 #if (DEBUG & 0x20)
849 {
850 int i;
851 printf("recv data hdr:");
852 for (i = 0; i < 14; i++)
853 printf("%x ", *(frame->head + i));
854 printf("\n");
855 }
856 #endif
857 /*
858 * Fill the buffer and pass it to upper layers
859 */
860 memcpy(buff, frame->head, 14);
861 memcpy(buff + 14, frame->data, frame_length);
862 NetReceive(buff, frame_length);
863 len = frame_length;
864 }
865 /*
866 * Reset buffer descriptor as empty
867 */
868 mpc5xxx_fec_rbd_clean(fec, pRbd);
869 }
870 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
871 return len;
872 }
873
874
875 /********************************************************************/
876 int mpc5xxx_fec_initialize(bd_t * bis)
877 {
878 mpc5xxx_fec_priv *fec;
879 struct eth_device *dev;
880 char *tmp, *end;
881 char env_enetaddr[6];
882 int i;
883
884 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
885 dev = (struct eth_device *)malloc(sizeof(*dev));
886 memset(dev, 0, sizeof *dev);
887
888 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
889 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
890 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
891 #if defined(CONFIG_MPC5xxx_FEC_MII100)
892 fec->xcv_type = MII100;
893 #elif defined(CONFIG_MPC5xxx_FEC_MII10)
894 fec->xcv_type = MII10;
895 #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
896 fec->xcv_type = SEVENWIRE;
897 #else
898 #error fec->xcv_type not initialized.
899 #endif
900
901 dev->priv = (void *)fec;
902 dev->iobase = MPC5XXX_FEC;
903 dev->init = mpc5xxx_fec_init;
904 dev->halt = mpc5xxx_fec_halt;
905 dev->send = mpc5xxx_fec_send;
906 dev->recv = mpc5xxx_fec_recv;
907
908 sprintf(dev->name, "FEC ETHERNET");
909 eth_register(dev);
910
911 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
912 miiphy_register (dev->name,
913 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
914 #endif
915
916 /*
917 * Try to set the mac address now. The fec mac address is
918 * a garbage after reset. When not using fec for booting
919 * the Linux fec driver will try to work with this garbage.
920 */
921 tmp = getenv("ethaddr");
922 if (tmp) {
923 for (i=0; i<6; i++) {
924 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
925 if (tmp)
926 tmp = (*end) ? end+1 : end;
927 }
928 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
929 }
930
931 mpc5xxx_fec_init_phy(dev, bis);
932
933 return 1;
934 }
935
936 /* MII-interface related functions */
937 /********************************************************************/
938 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
939 {
940 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
941 uint32 reg; /* convenient holder for the PHY register */
942 uint32 phy; /* convenient holder for the PHY */
943 int timeout = 0xffff;
944
945 /*
946 * reading from any PHY's register is done by properly
947 * programming the FEC's MII data register.
948 */
949 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
950 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
951
952 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
953
954 /*
955 * wait for the related interrupt
956 */
957 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
958
959 if (timeout == 0) {
960 #if (DEBUG & 0x2)
961 printf ("Read MDIO failed...\n");
962 #endif
963 return -1;
964 }
965
966 /*
967 * clear mii interrupt bit
968 */
969 eth->ievent = 0x00800000;
970
971 /*
972 * it's now safe to read the PHY's register
973 */
974 *retVal = (uint16) eth->mii_data;
975
976 return 0;
977 }
978
979 /********************************************************************/
980 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
981 {
982 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
983 uint32 reg; /* convenient holder for the PHY register */
984 uint32 phy; /* convenient holder for the PHY */
985 int timeout = 0xffff;
986
987 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
988 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
989
990 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
991 FEC_MII_DATA_TA | phy | reg | data);
992
993 /*
994 * wait for the MII interrupt
995 */
996 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
997
998 if (timeout == 0) {
999 #if (DEBUG & 0x2)
1000 printf ("Write MDIO failed...\n");
1001 #endif
1002 return -1;
1003 }
1004
1005 /*
1006 * clear MII interrupt bit
1007 */
1008 eth->ievent = 0x00800000;
1009
1010 return 0;
1011 }
1012
1013 #if (DEBUG & 0x40)
1014 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1015 {
1016 int i;
1017 char c;
1018 unsigned int crc, count;
1019
1020 /*
1021 * crc32 algorithm
1022 */
1023 /*
1024 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1025 */
1026 crc = crc_value;
1027
1028 for (i = len; --i >= 0;) {
1029 c = *string++;
1030 for (count = 0; count < 8; count++) {
1031 if ((c & 0x01) ^ (crc & 0x01)) {
1032 crc >>= 1;
1033 crc = crc ^ 0xedb88320;
1034 } else {
1035 crc >>= 1;
1036 }
1037 c >>= 1;
1038 }
1039 }
1040
1041 /*
1042 * In big endian system, do byte swaping for crc value
1043 */
1044 /**/ return crc;
1045 }
1046 #endif /* DEBUG */
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