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[people/ms/u-boot.git] / drivers / net / mpc5xxx_fec.c
1 /*
2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <mpc5xxx_sdma.h>
12 #include <malloc.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <miiphy.h>
16 #include "mpc5xxx_fec.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* #define DEBUG 0x28 */
21
22 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
23 #error "CONFIG_MII has to be defined!"
24 #endif
25
26 #if (DEBUG & 0x60)
27 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
29 #endif /* DEBUG */
30
31 typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36 } NBUF;
37
38 int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
39 int regAddr);
40 int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
41 int regAddr, u16 data);
42
43 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
44
45 /********************************************************************/
46 #if (DEBUG & 0x2)
47 static void mpc5xxx_fec_phydump (char *devname)
48 {
49 uint16 phyStatus, i;
50 uint8 phyAddr = CONFIG_PHY_ADDR;
51 uint8 reg_mask[] = {
52 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
53 /* regs to print: 0...7, 16...19, 21, 23, 24 */
54 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
55 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
56 #else
57 /* regs to print: 0...8, 16...20 */
58 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
60 #endif
61 };
62
63 for (i = 0; i < 32; i++) {
64 if (reg_mask[i]) {
65 miiphy_read(devname, phyAddr, i, &phyStatus);
66 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
67 }
68 }
69 }
70 #endif
71
72 /********************************************************************/
73 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
74 {
75 int ix;
76 char *data;
77 static int once = 0;
78
79 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
80 if (!once) {
81 data = (char *)malloc(FEC_MAX_PKT_SIZE);
82 if (data == NULL) {
83 printf ("RBD INIT FAILED\n");
84 return -1;
85 }
86 fec->rbdBase[ix].dataPointer = (uint32)data;
87 }
88 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
89 fec->rbdBase[ix].dataLength = 0;
90 }
91 once ++;
92
93 /*
94 * have the last RBD to close the ring
95 */
96 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
97 fec->rbdIndex = 0;
98
99 return 0;
100 }
101
102 /********************************************************************/
103 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
104 {
105 int ix;
106
107 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
108 fec->tbdBase[ix].status = 0;
109 }
110
111 /*
112 * Have the last TBD to close the ring
113 */
114 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
115
116 /*
117 * Initialize some indices
118 */
119 fec->tbdIndex = 0;
120 fec->usedTbdIndex = 0;
121 fec->cleanTbdNum = FEC_TBD_NUM;
122 }
123
124 /********************************************************************/
125 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
126 {
127 /*
128 * Reset buffer descriptor as empty
129 */
130 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
131 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
132 else
133 pRbd->status = FEC_RBD_EMPTY;
134
135 pRbd->dataLength = 0;
136
137 /*
138 * Now, we have an empty RxBD, restart the SmartDMA receive task
139 */
140 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
141
142 /*
143 * Increment BD count
144 */
145 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
146 }
147
148 /********************************************************************/
149 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
150 {
151 volatile FEC_TBD *pUsedTbd;
152
153 #if (DEBUG & 0x1)
154 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
155 fec->cleanTbdNum, fec->usedTbdIndex);
156 #endif
157
158 /*
159 * process all the consumed TBDs
160 */
161 while (fec->cleanTbdNum < FEC_TBD_NUM) {
162 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
163 if (pUsedTbd->status & FEC_TBD_READY) {
164 #if (DEBUG & 0x20)
165 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
166 #endif
167 return;
168 }
169
170 /*
171 * clean this buffer descriptor
172 */
173 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
174 pUsedTbd->status = FEC_TBD_WRAP;
175 else
176 pUsedTbd->status = 0;
177
178 /*
179 * update some indeces for a correct handling of the TBD ring
180 */
181 fec->cleanTbdNum++;
182 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
183 }
184 }
185
186 /********************************************************************/
187 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
188 {
189 uint8 currByte; /* byte for which to compute the CRC */
190 int byte; /* loop - counter */
191 int bit; /* loop - counter */
192 uint32 crc = 0xffffffff; /* initial value */
193
194 /*
195 * The algorithm used is the following:
196 * we loop on each of the six bytes of the provided address,
197 * and we compute the CRC by left-shifting the previous
198 * value by one position, so that each bit in the current
199 * byte of the address may contribute the calculation. If
200 * the latter and the MSB in the CRC are different, then
201 * the CRC value so computed is also ex-ored with the
202 * "polynomium generator". The current byte of the address
203 * is also shifted right by one bit at each iteration.
204 * This is because the CRC generatore in hardware is implemented
205 * as a shift-register with as many ex-ores as the radixes
206 * in the polynomium. This suggests that we represent the
207 * polynomiumm itself as a 32-bit constant.
208 */
209 for (byte = 0; byte < 6; byte++) {
210 currByte = mac[byte];
211 for (bit = 0; bit < 8; bit++) {
212 if ((currByte & 0x01) ^ (crc & 0x01)) {
213 crc >>= 1;
214 crc = crc ^ 0xedb88320;
215 } else {
216 crc >>= 1;
217 }
218 currByte >>= 1;
219 }
220 }
221
222 crc = crc >> 26;
223
224 /*
225 * Set individual hash table register
226 */
227 if (crc >= 32) {
228 fec->eth->iaddr1 = (1 << (crc - 32));
229 fec->eth->iaddr2 = 0;
230 } else {
231 fec->eth->iaddr1 = 0;
232 fec->eth->iaddr2 = (1 << crc);
233 }
234
235 /*
236 * Set physical address
237 */
238 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
239 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
240 }
241
242 /********************************************************************/
243 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
244 {
245 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
246 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
247
248 #if (DEBUG & 0x1)
249 printf ("mpc5xxx_fec_init... Begin\n");
250 #endif
251
252 mpc5xxx_fec_init_phy(dev, bis);
253
254 /*
255 * Call board-specific PHY fixups (if any)
256 */
257 #ifdef CONFIG_RESET_PHY_R
258 reset_phy();
259 #endif
260
261 /*
262 * Initialize RxBD/TxBD rings
263 */
264 mpc5xxx_fec_rbd_init(fec);
265 mpc5xxx_fec_tbd_init(fec);
266
267 /*
268 * Clear FEC-Lite interrupt event register(IEVENT)
269 */
270 fec->eth->ievent = 0xffffffff;
271
272 /*
273 * Set interrupt mask register
274 */
275 fec->eth->imask = 0x00000000;
276
277 /*
278 * Set FEC-Lite receive control register(R_CNTRL):
279 */
280 if (fec->xcv_type == SEVENWIRE) {
281 /*
282 * Frame length=1518; 7-wire mode
283 */
284 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
285 } else {
286 /*
287 * Frame length=1518; MII mode;
288 */
289 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
290 }
291
292 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
293
294 /*
295 * Set Opcode/Pause Duration Register
296 */
297 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
298
299 /*
300 * Set Rx FIFO alarm and granularity value
301 */
302 fec->eth->rfifo_cntrl = 0x0c000000
303 | (fec->eth->rfifo_cntrl & ~0x0f000000);
304 fec->eth->rfifo_alarm = 0x0000030c;
305 #if (DEBUG & 0x22)
306 if (fec->eth->rfifo_status & 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
308 }
309 #endif
310
311 /*
312 * Set Tx FIFO granularity value
313 */
314 fec->eth->tfifo_cntrl = 0x0c000000
315 | (fec->eth->tfifo_cntrl & ~0x0f000000);
316 #if (DEBUG & 0x2)
317 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
318 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
319 #endif
320
321 /*
322 * Set transmit fifo watermark register(X_WMRK), default = 64
323 */
324 fec->eth->tfifo_alarm = 0x00000080;
325 fec->eth->x_wmrk = 0x2;
326
327 /*
328 * Set individual address filter for unicast address
329 * and set physical address registers.
330 */
331 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
332
333 /*
334 * Set multicast address filter
335 */
336 fec->eth->gaddr1 = 0x00000000;
337 fec->eth->gaddr2 = 0x00000000;
338
339 /*
340 * Turn ON cheater FSM: ????
341 */
342 fec->eth->xmit_fsm = 0x03000000;
343
344 /*
345 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
346 * work w/ the current receive task.
347 */
348 sdma->PtdCntrl |= 0x00000001;
349
350 /*
351 * Set priority of different initiators
352 */
353 sdma->IPR0 = 7; /* always */
354 sdma->IPR3 = 6; /* Eth RX */
355 sdma->IPR4 = 5; /* Eth Tx */
356
357 /*
358 * Clear SmartDMA task interrupt pending bits
359 */
360 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
361
362 /*
363 * Initialize SmartDMA parameters stored in SRAM
364 */
365 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
366 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
367 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
369
370 /*
371 * Enable FEC-Lite controller
372 */
373 fec->eth->ecntrl |= 0x00000006;
374
375 #if (DEBUG & 0x2)
376 if (fec->xcv_type != SEVENWIRE)
377 mpc5xxx_fec_phydump (dev->name);
378 #endif
379
380 /*
381 * Enable SmartDMA receive task
382 */
383 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
384
385 #if (DEBUG & 0x1)
386 printf("mpc5xxx_fec_init... Done \n");
387 #endif
388
389 return 1;
390 }
391
392 /********************************************************************/
393 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
394 {
395 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
396 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
397 static int initialized = 0;
398
399 if(initialized)
400 return 0;
401 initialized = 1;
402
403 #if (DEBUG & 0x1)
404 printf ("mpc5xxx_fec_init_phy... Begin\n");
405 #endif
406
407 /*
408 * Initialize GPIO pins
409 */
410 if (fec->xcv_type == SEVENWIRE) {
411 /* 10MBit with 7-wire operation */
412 /* 7-wire only */
413 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
414 } else {
415 /* 100MBit with MD operation */
416 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
417 }
418
419 /*
420 * Clear FEC-Lite interrupt event register(IEVENT)
421 */
422 fec->eth->ievent = 0xffffffff;
423
424 /*
425 * Set interrupt mask register
426 */
427 fec->eth->imask = 0x00000000;
428
429 /*
430 * In original Promess-provided code PHY initialization is disabled with the
431 * following comment: "Phy initialization is DISABLED for now. There was a
432 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
433 * PHY initialization for the Motion-PRO board, until a proper fix is found.
434 */
435
436 if (fec->xcv_type != SEVENWIRE) {
437 /*
438 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
439 * and do not drop the Preamble.
440 * No MII for 7-wire mode
441 */
442 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
443 }
444
445 if (fec->xcv_type != SEVENWIRE) {
446 /*
447 * Initialize PHY(LXT971A):
448 *
449 * Generally, on power up, the LXT971A reads its configuration
450 * pins to check for forced operation, If not cofigured for
451 * forced operation, it uses auto-negotiation/parallel detection
452 * to automatically determine line operating conditions.
453 * If the PHY device on the other side of the link supports
454 * auto-negotiation, the LXT971A auto-negotiates with it
455 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
456 * support auto-negotiation, the LXT971A automatically detects
457 * the presence of either link pulses(10Mbps PHY) or Idle
458 * symbols(100Mbps) and sets its operating conditions accordingly.
459 *
460 * When auto-negotiation is controlled by software, the following
461 * steps are recommended.
462 *
463 * Note:
464 * The physical address is dependent on hardware configuration.
465 *
466 */
467 int timeout = 1;
468 uint16 phyStatus;
469
470 /*
471 * Reset PHY, then delay 300ns
472 */
473 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
474 udelay(1000);
475
476 if (fec->xcv_type == MII10) {
477 /*
478 * Force 10Base-T, FDX operation
479 */
480 #if (DEBUG & 0x2)
481 printf("Forcing 10 Mbps ethernet link... ");
482 #endif
483 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
484 /*
485 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
486 */
487 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
488
489 timeout = 20;
490 do { /* wait for link status to go down */
491 udelay(10000);
492 if ((timeout--) == 0) {
493 #if (DEBUG & 0x2)
494 printf("hmmm, should not have waited...");
495 #endif
496 break;
497 }
498 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
499 #if (DEBUG & 0x2)
500 printf("=");
501 #endif
502 } while ((phyStatus & 0x0004)); /* !link up */
503
504 timeout = 1000;
505 do { /* wait for link status to come back up */
506 udelay(10000);
507 if ((timeout--) == 0) {
508 printf("failed. Link is down.\n");
509 break;
510 }
511 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
512 #if (DEBUG & 0x2)
513 printf("+");
514 #endif
515 } while (!(phyStatus & 0x0004)); /* !link up */
516
517 #if (DEBUG & 0x2)
518 printf ("done.\n");
519 #endif
520 } else { /* MII100 */
521 /*
522 * Set the auto-negotiation advertisement register bits
523 */
524 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
525
526 /*
527 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
528 */
529 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
530
531 /*
532 * Wait for AN completion
533 */
534 timeout = 5000;
535 do {
536 udelay(1000);
537
538 if ((timeout--) == 0) {
539 #if (DEBUG & 0x2)
540 printf("PHY auto neg 0 failed...\n");
541 #endif
542 return -1;
543 }
544
545 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
546 #if (DEBUG & 0x2)
547 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
548 #endif
549 return -1;
550 }
551 } while (!(phyStatus & 0x0004));
552
553 #if (DEBUG & 0x2)
554 printf("PHY auto neg complete! \n");
555 #endif
556 }
557
558 }
559
560 #if (DEBUG & 0x2)
561 if (fec->xcv_type != SEVENWIRE)
562 mpc5xxx_fec_phydump (dev->name);
563 #endif
564
565
566 #if (DEBUG & 0x1)
567 printf("mpc5xxx_fec_init_phy... Done \n");
568 #endif
569
570 return 1;
571 }
572
573 /********************************************************************/
574 static void mpc5xxx_fec_halt(struct eth_device *dev)
575 {
576 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
577 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
578 int counter = 0xffff;
579
580 #if (DEBUG & 0x2)
581 if (fec->xcv_type != SEVENWIRE)
582 mpc5xxx_fec_phydump (dev->name);
583 #endif
584
585 /*
586 * mask FEC chip interrupts
587 */
588 fec->eth->imask = 0;
589
590 /*
591 * issue graceful stop command to the FEC transmitter if necessary
592 */
593 fec->eth->x_cntrl |= 0x00000001;
594
595 /*
596 * wait for graceful stop to register
597 */
598 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
599
600 /*
601 * Disable SmartDMA tasks
602 */
603 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
604 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
605
606 /*
607 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
608 * done. It doesn't work w/ the current receive task.
609 */
610 sdma->PtdCntrl &= ~0x00000001;
611
612 /*
613 * Disable the Ethernet Controller
614 */
615 fec->eth->ecntrl &= 0xfffffffd;
616
617 /*
618 * Clear FIFO status registers
619 */
620 fec->eth->rfifo_status &= 0x00700000;
621 fec->eth->tfifo_status &= 0x00700000;
622
623 fec->eth->reset_cntrl = 0x01000000;
624
625 /*
626 * Issue a reset command to the FEC chip
627 */
628 fec->eth->ecntrl |= 0x1;
629
630 /*
631 * wait at least 16 clock cycles
632 */
633 udelay(10);
634
635 /* don't leave the MII speed set to zero */
636 if (fec->xcv_type != SEVENWIRE) {
637 /*
638 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
639 * and do not drop the Preamble.
640 * No MII for 7-wire mode
641 */
642 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
643 }
644
645 #if (DEBUG & 0x3)
646 printf("Ethernet task stopped\n");
647 #endif
648 }
649
650 #if (DEBUG & 0x60)
651 /********************************************************************/
652
653 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
654 {
655 uint16 phyAddr = CONFIG_PHY_ADDR;
656 uint16 phyStatus;
657
658 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
659 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
660
661 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
662 printf("\nphyStatus: 0x%04x\n", phyStatus);
663 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
664 printf("ievent: 0x%08x\n", fec->eth->ievent);
665 printf("x_status: 0x%08x\n", fec->eth->x_status);
666 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
667
668 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
669 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
670 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
671 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
672 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
673 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
674 }
675 }
676
677 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
678 {
679 uint16 phyAddr = CONFIG_PHY_ADDR;
680 uint16 phyStatus;
681
682 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
683 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
684
685 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
686 printf("\nphyStatus: 0x%04x\n", phyStatus);
687 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
688 printf("ievent: 0x%08x\n", fec->eth->ievent);
689 printf("x_status: 0x%08x\n", fec->eth->x_status);
690 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
691
692 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
693 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
694 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
695 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
696 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
697 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
698 }
699 }
700 #endif /* DEBUG */
701
702 /********************************************************************/
703
704 static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
705 int data_length)
706 {
707 /*
708 * This routine transmits one frame. This routine only accepts
709 * 6-byte Ethernet addresses.
710 */
711 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
712 volatile FEC_TBD *pTbd;
713
714 #if (DEBUG & 0x20)
715 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
716 tfifo_print(dev->name, fec);
717 #endif
718
719 /*
720 * Clear Tx BD ring at first
721 */
722 mpc5xxx_fec_tbd_scrub(fec);
723
724 /*
725 * Check for valid length of data.
726 */
727 if ((data_length > 1500) || (data_length <= 0)) {
728 return -1;
729 }
730
731 /*
732 * Check the number of vacant TxBDs.
733 */
734 if (fec->cleanTbdNum < 1) {
735 #if (DEBUG & 0x20)
736 printf("No available TxBDs ...\n");
737 #endif
738 return -1;
739 }
740
741 /*
742 * Get the first TxBD to send the mac header
743 */
744 pTbd = &fec->tbdBase[fec->tbdIndex];
745 pTbd->dataLength = data_length;
746 pTbd->dataPointer = (uint32)eth_data;
747 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
748 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
749
750 #if (DEBUG & 0x100)
751 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
752 #endif
753
754 /*
755 * Kick the MII i/f
756 */
757 if (fec->xcv_type != SEVENWIRE) {
758 uint16 phyStatus;
759 miiphy_read(dev->name, 0, 0x1, &phyStatus);
760 }
761
762 /*
763 * Enable SmartDMA transmit task
764 */
765
766 #if (DEBUG & 0x20)
767 tfifo_print(dev->name, fec);
768 #endif
769 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
770 #if (DEBUG & 0x20)
771 tfifo_print(dev->name, fec);
772 #endif
773 #if (DEBUG & 0x8)
774 printf( "+" );
775 #endif
776
777 fec->cleanTbdNum -= 1;
778
779 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
780 printf ("smartDMA ethernet Tx task enabled\n");
781 #endif
782 /*
783 * wait until frame is sent .
784 */
785 while (pTbd->status & FEC_TBD_READY) {
786 udelay(10);
787 #if (DEBUG & 0x8)
788 printf ("TDB status = %04x\n", pTbd->status);
789 #endif
790 }
791
792 return 0;
793 }
794
795
796 /********************************************************************/
797 static int mpc5xxx_fec_recv(struct eth_device *dev)
798 {
799 /*
800 * This command pulls one frame from the card
801 */
802 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
803 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
804 unsigned long ievent;
805 int frame_length, len = 0;
806 NBUF *frame;
807 uchar buff[FEC_MAX_PKT_SIZE];
808
809 #if (DEBUG & 0x1)
810 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
811 #endif
812 #if (DEBUG & 0x8)
813 printf( "-" );
814 #endif
815
816 /*
817 * Check if any critical events have happened
818 */
819 ievent = fec->eth->ievent;
820 fec->eth->ievent = ievent;
821 if (ievent & 0x20060000) {
822 /* BABT, Rx/Tx FIFO errors */
823 mpc5xxx_fec_halt(dev);
824 mpc5xxx_fec_init(dev, NULL);
825 return 0;
826 }
827 if (ievent & 0x80000000) {
828 /* Heartbeat error */
829 fec->eth->x_cntrl |= 0x00000001;
830 }
831 if (ievent & 0x10000000) {
832 /* Graceful stop complete */
833 if (fec->eth->x_cntrl & 0x00000001) {
834 mpc5xxx_fec_halt(dev);
835 fec->eth->x_cntrl &= ~0x00000001;
836 mpc5xxx_fec_init(dev, NULL);
837 }
838 }
839
840 if (!(pRbd->status & FEC_RBD_EMPTY)) {
841 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
842 ((pRbd->dataLength - 4) > 14)) {
843
844 /*
845 * Get buffer address and size
846 */
847 frame = (NBUF *)pRbd->dataPointer;
848 frame_length = pRbd->dataLength - 4;
849
850 #if (DEBUG & 0x20)
851 {
852 int i;
853 printf("recv data hdr:");
854 for (i = 0; i < 14; i++)
855 printf("%x ", *(frame->head + i));
856 printf("\n");
857 }
858 #endif
859 /*
860 * Fill the buffer and pass it to upper layers
861 */
862 memcpy(buff, frame->head, 14);
863 memcpy(buff + 14, frame->data, frame_length);
864 net_process_received_packet(buff, frame_length);
865 len = frame_length;
866 }
867 /*
868 * Reset buffer descriptor as empty
869 */
870 mpc5xxx_fec_rbd_clean(fec, pRbd);
871 }
872 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
873 return len;
874 }
875
876
877 /********************************************************************/
878 int mpc5xxx_fec_initialize(bd_t * bis)
879 {
880 mpc5xxx_fec_priv *fec;
881 struct eth_device *dev;
882 char *tmp, *end;
883 char env_enetaddr[6];
884 int i;
885
886 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
887 dev = (struct eth_device *)malloc(sizeof(*dev));
888 memset(dev, 0, sizeof *dev);
889
890 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
891 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
892 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
893 #if defined(CONFIG_MPC5xxx_FEC_MII100)
894 fec->xcv_type = MII100;
895 #elif defined(CONFIG_MPC5xxx_FEC_MII10)
896 fec->xcv_type = MII10;
897 #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
898 fec->xcv_type = SEVENWIRE;
899 #else
900 #error fec->xcv_type not initialized.
901 #endif
902 if (fec->xcv_type != SEVENWIRE) {
903 /*
904 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
905 * and do not drop the Preamble.
906 * No MII for 7-wire mode
907 */
908 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
909 }
910
911 dev->priv = (void *)fec;
912 dev->iobase = MPC5XXX_FEC;
913 dev->init = mpc5xxx_fec_init;
914 dev->halt = mpc5xxx_fec_halt;
915 dev->send = mpc5xxx_fec_send;
916 dev->recv = mpc5xxx_fec_recv;
917
918 strcpy(dev->name, "FEC");
919 eth_register(dev);
920
921 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
922 int retval;
923 struct mii_dev *mdiodev = mdio_alloc();
924 if (!mdiodev)
925 return -ENOMEM;
926 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
927 mdiodev->read = fec5xxx_miiphy_read;
928 mdiodev->write = fec5xxx_miiphy_write;
929
930 retval = mdio_register(mdiodev);
931 if (retval < 0)
932 return retval;
933 #endif
934
935 /*
936 * Try to set the mac address now. The fec mac address is
937 * a garbage after reset. When not using fec for booting
938 * the Linux fec driver will try to work with this garbage.
939 */
940 tmp = getenv("ethaddr");
941 if (tmp) {
942 for (i=0; i<6; i++) {
943 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
944 if (tmp)
945 tmp = (*end) ? end+1 : end;
946 }
947 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
948 }
949
950 return 1;
951 }
952
953 /* MII-interface related functions */
954 /********************************************************************/
955 int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
956 int regAddr)
957 {
958 uint16 retVal = 0;
959 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
960 uint32 reg; /* convenient holder for the PHY register */
961 uint32 phy; /* convenient holder for the PHY */
962 int timeout = 0xffff;
963
964 /*
965 * reading from any PHY's register is done by properly
966 * programming the FEC's MII data register.
967 */
968 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
969 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
970
971 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
972
973 /*
974 * wait for the related interrupt
975 */
976 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
977
978 if (timeout == 0) {
979 #if (DEBUG & 0x2)
980 printf ("Read MDIO failed...\n");
981 #endif
982 return -1;
983 }
984
985 /*
986 * clear mii interrupt bit
987 */
988 eth->ievent = 0x00800000;
989
990 /*
991 * it's now safe to read the PHY's register
992 */
993 retVal = (uint16) eth->mii_data;
994
995 return retVal;
996 }
997
998 /********************************************************************/
999 int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
1000 int regAddr, u16 data)
1001 {
1002 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
1003 uint32 reg; /* convenient holder for the PHY register */
1004 uint32 phy; /* convenient holder for the PHY */
1005 int timeout = 0xffff;
1006
1007 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
1008 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
1009
1010 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1011 FEC_MII_DATA_TA | phy | reg | data);
1012
1013 /*
1014 * wait for the MII interrupt
1015 */
1016 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1017
1018 if (timeout == 0) {
1019 #if (DEBUG & 0x2)
1020 printf ("Write MDIO failed...\n");
1021 #endif
1022 return -1;
1023 }
1024
1025 /*
1026 * clear MII interrupt bit
1027 */
1028 eth->ievent = 0x00800000;
1029
1030 return 0;
1031 }
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