drivers/net/phy/micrel.c

   1 /*
   2  * Micrel PHY drivers
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   7  * author Andy Fleming
   8  * (C) 2012 NetModule AG, David Andrey, added KSZ9031
   9  */
  10 #include <config.h>
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <fdtdec.h>
  15 #include <micrel.h>
  16 #include <phy.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct phy_driver KSZ804_driver = {
  21         .name = "Micrel KSZ804",
  22         .uid = 0x221510,
  23         .mask = 0xfffff0,
  24         .features = PHY_BASIC_FEATURES,
  25         .config = &genphy_config,
  26         .startup = &genphy_startup,
  27         .shutdown = &genphy_shutdown,
  28 };
  29
  30 #define MII_KSZPHY_OMSO         0x16
  31 #define KSZPHY_OMSO_B_CAST_OFF  (1 << 9)
  32
  33 static int ksz_genconfig_bcastoff(struct phy_device *phydev)
  34 {
  35         int ret;
  36
  37         ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
  38         if (ret < 0)
  39                 return ret;
  40
  41         ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
  42                         ret | KSZPHY_OMSO_B_CAST_OFF);
  43         if (ret < 0)
  44                 return ret;
  45
  46         return genphy_config(phydev);
  47 }
  48
  49 static struct phy_driver KSZ8031_driver = {
  50         .name = "Micrel KSZ8021/KSZ8031",
  51         .uid = 0x221550,
  52         .mask = 0xfffff0,
  53         .features = PHY_BASIC_FEATURES,
  54         .config = &ksz_genconfig_bcastoff,
  55         .startup = &genphy_startup,
  56         .shutdown = &genphy_shutdown,
  57 };
  58
  59 /**
  60  * KSZ8051
  61  */
  62 #define MII_KSZ8051_PHY_OMSO                    0x16
  63 #define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON       (1 << 5)
  64
  65 static int ksz8051_config(struct phy_device *phydev)
  66 {
  67         unsigned val;
  68
  69         /* Disable NAND-tree */
  70         val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
  71         val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
  72         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
  73
  74         return genphy_config(phydev);
  75 }
  76
  77 static struct phy_driver KSZ8051_driver = {
  78         .name = "Micrel KSZ8051",
  79         .uid = 0x221550,
  80         .mask = 0xfffff0,
  81         .features = PHY_BASIC_FEATURES,
  82         .config = &ksz8051_config,
  83         .startup = &genphy_startup,
  84         .shutdown = &genphy_shutdown,
  85 };
  86
  87 static struct phy_driver KSZ8081_driver = {
  88         .name = "Micrel KSZ8081",
  89         .uid = 0x221560,
  90         .mask = 0xfffff0,
  91         .features = PHY_BASIC_FEATURES,
  92         .config = &ksz_genconfig_bcastoff,
  93         .startup = &genphy_startup,
  94         .shutdown = &genphy_shutdown,
  95 };
  96
  97 /**
  98  * KSZ8895
  99  */
 100
 101 static unsigned short smireg_to_phy(unsigned short reg)
 102 {
 103         return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
 104 }
 105
 106 static unsigned short smireg_to_reg(unsigned short reg)
 107 {
 108         return reg & 0x1F;
 109 }
 110
 111 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
 112 {
 113         phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
 114                                                 smireg_to_reg(smireg), val);
 115 }
 116
 117 #if 0
 118 static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
 119 {
 120         return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
 121                                         MDIO_DEVAD_NONE, smireg_to_reg(smireg));
 122 }
 123 #endif
 124
 125 int ksz8895_config(struct phy_device *phydev)
 126 {
 127         /* we are connected directly to the switch without
 128          * dedicated PHY. SCONF1 == 001 */
 129         phydev->link = 1;
 130         phydev->duplex = DUPLEX_FULL;
 131         phydev->speed = SPEED_100;
 132
 133         /* Force the switch to start */
 134         ksz8895_write_smireg(phydev, 1, 1);
 135
 136         return 0;
 137 }
 138
 139 static int ksz8895_startup(struct phy_device *phydev)
 140 {
 141         return 0;
 142 }
 143
 144 static struct phy_driver ksz8895_driver = {
 145         .name = "Micrel KSZ8895/KSZ8864",
 146         .uid  = 0x221450,
 147         .mask = 0xffffe1,
 148         .features = PHY_BASIC_FEATURES,
 149         .config   = &ksz8895_config,
 150         .startup  = &ksz8895_startup,
 151         .shutdown = &genphy_shutdown,
 152 };
 153
 154 #ifndef CONFIG_PHY_MICREL_KSZ9021
 155 /*
 156  * I can't believe Micrel used the exact same part number
 157  * for the KSZ9021. Shame Micrel, Shame!
 158  */
 159 static struct phy_driver KS8721_driver = {
 160         .name = "Micrel KS8721BL",
 161         .uid = 0x221610,
 162         .mask = 0xfffff0,
 163         .features = PHY_BASIC_FEATURES,
 164         .config = &genphy_config,
 165         .startup = &genphy_startup,
 166         .shutdown = &genphy_shutdown,
 167 };
 168 #endif
 169
 170
 171 /*
 172  * KSZ9021 - KSZ9031 common
 173  */
 174
 175 #define MII_KSZ90xx_PHY_CTL             0x1f
 176 #define MIIM_KSZ90xx_PHYCTL_1000        (1 << 6)
 177 #define MIIM_KSZ90xx_PHYCTL_100         (1 << 5)
 178 #define MIIM_KSZ90xx_PHYCTL_10          (1 << 4)
 179 #define MIIM_KSZ90xx_PHYCTL_DUPLEX      (1 << 3)
 180
 181 static int ksz90xx_startup(struct phy_device *phydev)
 182 {
 183         unsigned phy_ctl;
 184         int ret;
 185
 186         ret = genphy_update_link(phydev);
 187         if (ret)
 188                 return ret;
 189
 190         phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
 191
 192         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
 193                 phydev->duplex = DUPLEX_FULL;
 194         else
 195                 phydev->duplex = DUPLEX_HALF;
 196
 197         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
 198                 phydev->speed = SPEED_1000;
 199         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
 200                 phydev->speed = SPEED_100;
 201         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
 202                 phydev->speed = SPEED_10;
 203         return 0;
 204 }
 205
 206 /* Common OF config bits for KSZ9021 and KSZ9031 */
 207 #if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
 208 #ifdef CONFIG_DM_ETH
 209 struct ksz90x1_reg_field {
 210         const char      *name;
 211         const u8        size;   /* Size of the bitfield, in bits */
 212         const u8        off;    /* Offset from bit 0 */
 213         const u8        dflt;   /* Default value */
 214 };
 215
 216 struct ksz90x1_ofcfg {
 217         const u16                       reg;
 218         const u16                       devad;
 219         const struct ksz90x1_reg_field  *grp;
 220         const u16                       grpsz;
 221 };
 222
 223 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
 224         { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
 225         { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
 226 };
 227
 228 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
 229         { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
 230         { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
 231 };
 232
 233 static int ksz90x1_of_config_group(struct phy_device *phydev,
 234                                    struct ksz90x1_ofcfg *ofcfg)
 235 {
 236         struct udevice *dev = phydev->dev;
 237         struct phy_driver *drv = phydev->drv;
 238         const int ps_to_regval = 60;
 239         int val[4];
 240         int i, changed = 0, offset, max;
 241         u16 regval = 0;
 242
 243         if (!drv || !drv->writeext)
 244                 return -EOPNOTSUPP;
 245
 246         for (i = 0; i < ofcfg->grpsz; i++) {
 247                 val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
 248                                          ofcfg->grp[i].name, -1);
 249                 offset = ofcfg->grp[i].off;
 250                 if (val[i] == -1) {
 251                         /* Default register value for KSZ9021 */
 252                         regval |= ofcfg->grp[i].dflt << offset;
 253                 } else {
 254                         changed = 1;    /* Value was changed in OF */
 255                         /* Calculate the register value and fix corner cases */
 256                         if (val[i] > ps_to_regval * 0xf) {
 257                                 max = (1 << ofcfg->grp[i].size) - 1;
 258                                 regval |= max << offset;
 259                         } else {
 260                                 regval |= (val[i] / ps_to_regval) << offset;
 261                         }
 262                 }
 263         }
 264
 265         if (!changed)
 266                 return 0;
 267
 268         return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
 269 }
 270 #endif
 271 #endif
 272
 273 #ifdef CONFIG_PHY_MICREL_KSZ9021
 274 /*
 275  * KSZ9021
 276  */
 277
 278 /* PHY Registers */
 279 #define MII_KSZ9021_EXTENDED_CTRL       0x0b
 280 #define MII_KSZ9021_EXTENDED_DATAW      0x0c
 281 #define MII_KSZ9021_EXTENDED_DATAR      0x0d
 282
 283 #define CTRL1000_PREFER_MASTER          (1 << 10)
 284 #define CTRL1000_CONFIG_MASTER          (1 << 11)
 285 #define CTRL1000_MANUAL_CONFIG          (1 << 12)
 286
 287 #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
 288                                defined(CONFIG_PHY_MICREL_KSZ9031))
 289 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
 290         { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
 291         { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
 292 };
 293
 294 static int ksz9021_of_config(struct phy_device *phydev)
 295 {
 296         struct ksz90x1_ofcfg ofcfg[] = {
 297                 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
 298                 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
 299                 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
 300         };
 301         int i, ret = 0;
 302
 303         for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
 304                 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
 305                 if (ret)
 306                         return ret;
 307
 308         return 0;
 309 }
 310 #else
 311 static int ksz9021_of_config(struct phy_device *phydev)
 312 {
 313         return 0;
 314 }
 315 #endif
 316
 317 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 318 {
 319         /* extended registers */
 320         phy_write(phydev, MDIO_DEVAD_NONE,
 321                 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
 322         return phy_write(phydev, MDIO_DEVAD_NONE,
 323                 MII_KSZ9021_EXTENDED_DATAW, val);
 324 }
 325
 326 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
 327 {
 328         /* extended registers */
 329         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
 330         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
 331 }
 332
 333
 334 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 335                               int regnum)
 336 {
 337         return ksz9021_phy_extended_read(phydev, regnum);
 338 }
 339
 340 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
 341                                int devaddr, int regnum, u16 val)
 342 {
 343         return ksz9021_phy_extended_write(phydev, regnum, val);
 344 }
 345
 346 /* Micrel ksz9021 */
 347 static int ksz9021_config(struct phy_device *phydev)
 348 {
 349         unsigned ctrl1000 = 0;
 350         const unsigned master = CTRL1000_PREFER_MASTER |
 351                         CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 352         unsigned features = phydev->drv->features;
 353         int ret;
 354
 355         ret = ksz9021_of_config(phydev);
 356         if (ret)
 357                 return ret;
 358
 359         if (getenv("disable_giga"))
 360                 features &= ~(SUPPORTED_1000baseT_Half |
 361                                 SUPPORTED_1000baseT_Full);
 362         /* force master mode for 1000BaseT due to chip errata */
 363         if (features & SUPPORTED_1000baseT_Half)
 364                 ctrl1000 |= ADVERTISE_1000HALF | master;
 365         if (features & SUPPORTED_1000baseT_Full)
 366                 ctrl1000 |= ADVERTISE_1000FULL | master;
 367         phydev->advertising = phydev->supported = features;
 368         phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
 369         genphy_config_aneg(phydev);
 370         genphy_restart_aneg(phydev);
 371         return 0;
 372 }
 373
 374 static struct phy_driver ksz9021_driver = {
 375         .name = "Micrel ksz9021",
 376         .uid  = 0x221610,
 377         .mask = 0xfffff0,
 378         .features = PHY_GBIT_FEATURES,
 379         .config = &ksz9021_config,
 380         .startup = &ksz90xx_startup,
 381         .shutdown = &genphy_shutdown,
 382         .writeext = &ksz9021_phy_extwrite,
 383         .readext = &ksz9021_phy_extread,
 384 };
 385 #endif
 386
 387 /**
 388  * KSZ9031
 389  */
 390 /* PHY Registers */
 391 #define MII_KSZ9031_MMD_ACCES_CTRL      0x0d
 392 #define MII_KSZ9031_MMD_REG_DATA        0x0e
 393
 394 #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
 395                                defined(CONFIG_PHY_MICREL_KSZ9031))
 396 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
 397         { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
 398 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
 399         { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
 400
 401 static int ksz9031_of_config(struct phy_device *phydev)
 402 {
 403         struct ksz90x1_ofcfg ofcfg[] = {
 404                 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
 405                 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
 406                 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
 407                 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
 408         };
 409         int i, ret = 0;
 410
 411         for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
 412                 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
 413                 if (ret)
 414                         return ret;
 415
 416         return 0;
 417 }
 418 #else
 419 static int ksz9031_of_config(struct phy_device *phydev)
 420 {
 421         return 0;
 422 }
 423 #endif
 424
 425 /* Accessors to extended registers*/
 426 int ksz9031_phy_extended_write(struct phy_device *phydev,
 427                                int devaddr, int regnum, u16 mode, u16 val)
 428 {
 429         /*select register addr for mmd*/
 430         phy_write(phydev, MDIO_DEVAD_NONE,
 431                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 432         /*select register for mmd*/
 433         phy_write(phydev, MDIO_DEVAD_NONE,
 434                   MII_KSZ9031_MMD_REG_DATA, regnum);
 435         /*setup mode*/
 436         phy_write(phydev, MDIO_DEVAD_NONE,
 437                   MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
 438         /*write the value*/
 439         return  phy_write(phydev, MDIO_DEVAD_NONE,
 440                 MII_KSZ9031_MMD_REG_DATA, val);
 441 }
 442
 443 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 444                               int regnum, u16 mode)
 445 {
 446         phy_write(phydev, MDIO_DEVAD_NONE,
 447                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 448         phy_write(phydev, MDIO_DEVAD_NONE,
 449                   MII_KSZ9031_MMD_REG_DATA, regnum);
 450         phy_write(phydev, MDIO_DEVAD_NONE,
 451                   MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
 452         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
 453 }
 454
 455 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 456                                int regnum)
 457 {
 458         return ksz9031_phy_extended_read(phydev, devaddr, regnum,
 459                                          MII_KSZ9031_MOD_DATA_NO_POST_INC);
 460 };
 461
 462 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 463                                 int devaddr, int regnum, u16 val)
 464 {
 465         return ksz9031_phy_extended_write(phydev, devaddr, regnum,
 466                                          MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 467 };
 468
 469 static int ksz9031_config(struct phy_device *phydev)
 470 {
 471         int ret;
 472         ret = ksz9031_of_config(phydev);
 473         if (ret)
 474                 return ret;
 475         return genphy_config(phydev);
 476 }
 477
 478 static struct phy_driver ksz9031_driver = {
 479         .name = "Micrel ksz9031",
 480         .uid  = 0x221620,
 481         .mask = 0xfffff0,
 482         .features = PHY_GBIT_FEATURES,
 483         .config   = &ksz9031_config,
 484         .startup  = &ksz90xx_startup,
 485         .shutdown = &genphy_shutdown,
 486         .writeext = &ksz9031_phy_extwrite,
 487         .readext = &ksz9031_phy_extread,
 488 };
 489
 490 int phy_micrel_init(void)
 491 {
 492         phy_register(&KSZ804_driver);
 493         phy_register(&KSZ8031_driver);
 494         phy_register(&KSZ8051_driver);
 495         phy_register(&KSZ8081_driver);
 496 #ifdef CONFIG_PHY_MICREL_KSZ9021
 497         phy_register(&ksz9021_driver);
 498 #else
 499         phy_register(&KS8721_driver);
 500 #endif
 501         phy_register(&ksz9031_driver);
 502         phy_register(&ksz8895_driver);
 503         return 0;
 504 }