4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * Add vsc8662 phy support - Priyanka Jain
7 * SPDX-License-Identifier: GPL-2.0+
11 /* Cicada Auxiliary Control/Status Register */
12 #define MIIM_CIS82xx_AUX_CONSTAT 0x1c
13 #define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
14 #define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
15 #define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
16 #define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
17 #define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
19 /* Cicada Extended Control Register 1 */
20 #define MIIM_CIS82xx_EXT_CON1 0x17
21 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
23 /* Cicada 8204 Extended PHY Control Register 1 */
24 #define MIIM_CIS8204_EPHY_CON 0x17
25 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
26 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
28 /* Cicada 8204 Serial LED Control Register */
29 #define MIIM_CIS8204_SLED_CON 0x1b
30 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
32 /* Vitesse VSC8601 Extended PHY Control Register 1 */
33 #define MIIM_VSC8601_EPHY_CON 0x17
34 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
35 #define MIIM_VSC8601_SKEW_CTRL 0x1c
37 #define PHY_EXT_PAGE_ACCESS 0x1f
38 #define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
39 #define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
41 /* Vitesse VSC8574 control register */
42 #define MIIM_VSC8574_MAC_SERDES_CON 0x10
43 #define MIIM_VSC8574_MAC_SERDES_ANEG 0x80
44 #define MIIM_VSC8574_GENERAL18 0x12
45 #define MIIM_VSC8574_GENERAL19 0x13
47 /* Vitesse VSC8574 gerenal purpose register 18 */
48 #define MIIM_VSC8574_18G_SGMII 0x80f0
49 #define MIIM_VSC8574_18G_QSGMII 0x80e0
50 #define MIIM_VSC8574_18G_CMDSTAT 0x8000
52 /* Vitesse VSC8514 control register */
53 #define MIIM_VSC8514_GENERAL18 0x12
54 #define MIIM_VSC8514_GENERAL19 0x13
55 #define MIIM_VSC8514_GENERAL23 0x17
57 /* Vitesse VSC8514 gerenal purpose register 18 */
58 #define MIIM_VSC8514_18G_QSGMII 0x80e0
59 #define MIIM_VSC8514_18G_CMDSTAT 0x8000
61 /* Vitesse VSC8664 Control/Status Register */
62 #define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
63 #define MIIM_VSC8664_ADDITIONAL_DEV 0x16
64 #define MIIM_VSC8664_EPHY_CON 0x17
65 #define MIIM_VSC8664_LED_CON 0x1E
67 #define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
70 static int vitesse_config(struct phy_device
*phydev
)
72 /* Override PHY config settings */
73 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS82xx_AUX_CONSTAT
,
74 MIIM_CIS82xx_AUXCONSTAT_INIT
);
75 /* Set up the interface mode */
76 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS82xx_EXT_CON1
,
77 MIIM_CIS8201_EXTCON1_INIT
);
79 genphy_config_aneg(phydev
);
84 static int vitesse_parse_status(struct phy_device
*phydev
)
89 mii_reg
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS82xx_AUX_CONSTAT
);
91 if (mii_reg
& MIIM_CIS82xx_AUXCONSTAT_DUPLEX
)
92 phydev
->duplex
= DUPLEX_FULL
;
94 phydev
->duplex
= DUPLEX_HALF
;
96 speed
= mii_reg
& MIIM_CIS82xx_AUXCONSTAT_SPEED
;
98 case MIIM_CIS82xx_AUXCONSTAT_GBIT
:
99 phydev
->speed
= SPEED_1000
;
101 case MIIM_CIS82xx_AUXCONSTAT_100
:
102 phydev
->speed
= SPEED_100
;
105 phydev
->speed
= SPEED_10
;
112 static int vitesse_startup(struct phy_device
*phydev
)
114 genphy_update_link(phydev
);
115 vitesse_parse_status(phydev
);
120 static int cis8204_config(struct phy_device
*phydev
)
122 /* Override PHY config settings */
123 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS82xx_AUX_CONSTAT
,
124 MIIM_CIS82xx_AUXCONSTAT_INIT
);
126 genphy_config_aneg(phydev
);
128 if ((phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
129 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
130 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
131 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
))
132 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS8204_EPHY_CON
,
133 MIIM_CIS8204_EPHYCON_INIT
|
134 MIIM_CIS8204_EPHYCON_RGMII
);
136 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_CIS8204_EPHY_CON
,
137 MIIM_CIS8204_EPHYCON_INIT
);
142 /* Vitesse VSC8601 */
143 static int vsc8601_config(struct phy_device
*phydev
)
145 /* Configure some basic stuff */
146 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
147 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8601_EPHY_CON
,
148 MIIM_VSC8601_EPHY_CON_INIT_SKEW
);
149 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
150 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 1);
151 #define VSC8101_SKEW \
152 ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
153 | (CONFIG_SYS_VSC8601_SKEW_RX << 12))
154 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8601_SKEW_CTRL
,
156 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 0);
160 genphy_config_aneg(phydev
);
165 static int vsc8574_config(struct phy_device
*phydev
)
168 /* configure register 19G for MAC */
169 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
,
170 PHY_EXT_PAGE_ACCESS_GENERAL
);
172 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL19
);
173 if (phydev
->interface
== PHY_INTERFACE_MODE_QSGMII
) {
174 /* set bit 15:14 to '01' for QSGMII mode */
175 val
= (val
& 0x3fff) | (1 << 14);
176 phy_write(phydev
, MDIO_DEVAD_NONE
,
177 MIIM_VSC8574_GENERAL19
, val
);
178 /* Enable 4 ports MAC QSGMII */
179 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL18
,
180 MIIM_VSC8574_18G_QSGMII
);
182 /* set bit 15:14 to '00' for SGMII mode */
184 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL19
, val
);
185 /* Enable 4 ports MAC SGMII */
186 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL18
,
187 MIIM_VSC8574_18G_SGMII
);
189 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL18
);
190 /* When bit 15 is cleared the command has completed */
191 while (val
& MIIM_VSC8574_18G_CMDSTAT
)
192 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_GENERAL18
);
194 /* Enable Serdes Auto-negotiation */
195 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
,
196 PHY_EXT_PAGE_ACCESS_EXTENDED3
);
197 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_MAC_SERDES_CON
);
198 val
= val
| MIIM_VSC8574_MAC_SERDES_ANEG
;
199 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8574_MAC_SERDES_CON
, val
);
201 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 0);
203 genphy_config_aneg(phydev
);
208 static int vsc8514_config(struct phy_device
*phydev
)
211 int timeout
= 1000000;
213 /* configure register to access 19G */
214 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
,
215 PHY_EXT_PAGE_ACCESS_GENERAL
);
217 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL19
);
218 if (phydev
->interface
== PHY_INTERFACE_MODE_QSGMII
) {
219 /* set bit 15:14 to '01' for QSGMII mode */
220 val
= (val
& 0x3fff) | (1 << 14);
221 phy_write(phydev
, MDIO_DEVAD_NONE
,
222 MIIM_VSC8514_GENERAL19
, val
);
223 /* Enable 4 ports MAC QSGMII */
224 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL18
,
225 MIIM_VSC8514_18G_QSGMII
);
227 /*TODO Add SGMII functionality once spec sheet
228 * for VSC8514 defines complete functionality
232 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL18
);
233 /* When bit 15 is cleared the command has completed */
234 while ((val
& MIIM_VSC8514_18G_CMDSTAT
) && timeout
--)
235 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL18
);
238 printf("PHY 8514 config failed\n");
242 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 0);
244 /* configure register to access 23 */
245 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL23
);
246 /* set bits 10:8 to '000' */
247 val
= (val
& 0xf8ff);
248 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8514_GENERAL23
, val
);
250 genphy_config_aneg(phydev
);
255 static int vsc8664_config(struct phy_device
*phydev
)
259 /* Enable MAC interface auto-negotiation */
260 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 0);
261 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_EPHY_CON
);
263 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_EPHY_CON
, val
);
265 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
,
266 PHY_EXT_PAGE_ACCESS_EXTENDED
);
267 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_SERDES_AND_SIGDET
);
269 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_SERDES_AND_SIGDET
, val
);
270 phy_write(phydev
, MDIO_DEVAD_NONE
, PHY_EXT_PAGE_ACCESS
, 0);
272 /* Enable LED blink */
273 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_LED_CON
);
275 phy_write(phydev
, MDIO_DEVAD_NONE
, MIIM_VSC8664_LED_CON
, val
);
277 genphy_config_aneg(phydev
);
282 static struct phy_driver VSC8211_driver
= {
283 .name
= "Vitesse VSC8211",
286 .features
= PHY_GBIT_FEATURES
,
287 .config
= &vitesse_config
,
288 .startup
= &vitesse_startup
,
289 .shutdown
= &genphy_shutdown
,
292 static struct phy_driver VSC8221_driver
= {
293 .name
= "Vitesse VSC8221",
296 .features
= PHY_GBIT_FEATURES
,
297 .config
= &genphy_config_aneg
,
298 .startup
= &vitesse_startup
,
299 .shutdown
= &genphy_shutdown
,
302 static struct phy_driver VSC8244_driver
= {
303 .name
= "Vitesse VSC8244",
306 .features
= PHY_GBIT_FEATURES
,
307 .config
= &genphy_config_aneg
,
308 .startup
= &vitesse_startup
,
309 .shutdown
= &genphy_shutdown
,
312 static struct phy_driver VSC8234_driver
= {
313 .name
= "Vitesse VSC8234",
316 .features
= PHY_GBIT_FEATURES
,
317 .config
= &genphy_config_aneg
,
318 .startup
= &vitesse_startup
,
319 .shutdown
= &genphy_shutdown
,
322 static struct phy_driver VSC8574_driver
= {
323 .name
= "Vitesse VSC8574",
326 .features
= PHY_GBIT_FEATURES
,
327 .config
= &vsc8574_config
,
328 .startup
= &vitesse_startup
,
329 .shutdown
= &genphy_shutdown
,
332 static struct phy_driver VSC8514_driver
= {
333 .name
= "Vitesse VSC8514",
336 .features
= PHY_GBIT_FEATURES
,
337 .config
= &vsc8514_config
,
338 .startup
= &vitesse_startup
,
339 .shutdown
= &genphy_shutdown
,
342 static struct phy_driver VSC8601_driver
= {
343 .name
= "Vitesse VSC8601",
346 .features
= PHY_GBIT_FEATURES
,
347 .config
= &vsc8601_config
,
348 .startup
= &vitesse_startup
,
349 .shutdown
= &genphy_shutdown
,
352 static struct phy_driver VSC8641_driver
= {
353 .name
= "Vitesse VSC8641",
356 .features
= PHY_GBIT_FEATURES
,
357 .config
= &genphy_config_aneg
,
358 .startup
= &vitesse_startup
,
359 .shutdown
= &genphy_shutdown
,
362 static struct phy_driver VSC8662_driver
= {
363 .name
= "Vitesse VSC8662",
366 .features
= PHY_GBIT_FEATURES
,
367 .config
= &genphy_config_aneg
,
368 .startup
= &vitesse_startup
,
369 .shutdown
= &genphy_shutdown
,
372 static struct phy_driver VSC8664_driver
= {
373 .name
= "Vitesse VSC8664",
376 .features
= PHY_GBIT_FEATURES
,
377 .config
= &vsc8664_config
,
378 .startup
= &vitesse_startup
,
379 .shutdown
= &genphy_shutdown
,
382 /* Vitesse bought Cicada, so we'll put these here */
383 static struct phy_driver cis8201_driver
= {
387 .features
= PHY_GBIT_FEATURES
,
388 .config
= &vitesse_config
,
389 .startup
= &vitesse_startup
,
390 .shutdown
= &genphy_shutdown
,
393 static struct phy_driver cis8204_driver
= {
394 .name
= "Cicada Cis8204",
397 .features
= PHY_GBIT_FEATURES
,
398 .config
= &cis8204_config
,
399 .startup
= &vitesse_startup
,
400 .shutdown
= &genphy_shutdown
,
403 int phy_vitesse_init(void)
405 phy_register(&VSC8641_driver
);
406 phy_register(&VSC8601_driver
);
407 phy_register(&VSC8234_driver
);
408 phy_register(&VSC8244_driver
);
409 phy_register(&VSC8211_driver
);
410 phy_register(&VSC8221_driver
);
411 phy_register(&VSC8574_driver
);
412 phy_register(&VSC8514_driver
);
413 phy_register(&VSC8662_driver
);
414 phy_register(&VSC8664_driver
);
415 phy_register(&cis8201_driver
);
416 phy_register(&cis8204_driver
);