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dm: net: Convert rtl8169 to use DM PCI API
[people/ms/u-boot.git] / drivers / net / rtl8169.c
1 /*
2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from r8169.c of etherboot
7 *
8 */
9
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
13 *
14 * SPDX-License-Identifier: GPL-2.0+
15 *
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
19 *
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
22 *
23 * Linux Driver Version 1.27a, 10.02.2002
24 *
25 * Thanks to:
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
29 * is appreciated.
30 *
31 * REVISION HISTORY:
32 * ================
33 *
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
36 *
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
39 /*
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
42 */
43 #include <common.h>
44 #include <dm.h>
45 #include <errno.h>
46 #include <malloc.h>
47 #include <memalign.h>
48 #include <net.h>
49 #ifndef CONFIG_DM_ETH
50 #include <netdev.h>
51 #endif
52 #include <asm/io.h>
53 #include <pci.h>
54
55 #undef DEBUG_RTL8169
56 #undef DEBUG_RTL8169_TX
57 #undef DEBUG_RTL8169_RX
58
59 #define drv_version "v1.5"
60 #define drv_date "01-17-2004"
61
62 static unsigned long ioaddr;
63
64 /* Condensed operations for readability. */
65 #define currticks() get_timer(0)
66
67 /* media options */
68 #define MAX_UNITS 8
69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
70
71 /* MAC address length*/
72 #define MAC_ADDR_LEN 6
73
74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
75 #define MAX_ETH_FRAME_SIZE 1536
76
77 #define TX_FIFO_THRESH 256 /* In bytes */
78
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85
86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
87 #ifdef CONFIG_SYS_RX_ETH_BUFFER
88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
89 #else
90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
91 #endif
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define RX_BUF_LEN 8192
94
95 #define RTL_MIN_IO_SIZE 0x80
96 #define TX_TIMEOUT (6*HZ)
97
98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
99 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb(ioaddr + (reg))
103 #define RTL_R16(reg) readw(ioaddr + (reg))
104 #define RTL_R32(reg) readl(ioaddr + (reg))
105
106 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
107 #define ETH_ALEN MAC_ADDR_LEN
108 #define ETH_ZLEN 60
109
110 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
111 (pci_addr_t)(unsigned long)a)
112 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
113 (phys_addr_t)a)
114
115 enum RTL8169_registers {
116 MAC0 = 0, /* Ethernet hardware address. */
117 MAR0 = 8, /* Multicast filter. */
118 TxDescStartAddrLow = 0x20,
119 TxDescStartAddrHigh = 0x24,
120 TxHDescStartAddrLow = 0x28,
121 TxHDescStartAddrHigh = 0x2c,
122 FLASH = 0x30,
123 ERSR = 0x36,
124 ChipCmd = 0x37,
125 TxPoll = 0x38,
126 IntrMask = 0x3C,
127 IntrStatus = 0x3E,
128 TxConfig = 0x40,
129 RxConfig = 0x44,
130 RxMissed = 0x4C,
131 Cfg9346 = 0x50,
132 Config0 = 0x51,
133 Config1 = 0x52,
134 Config2 = 0x53,
135 Config3 = 0x54,
136 Config4 = 0x55,
137 Config5 = 0x56,
138 MultiIntr = 0x5C,
139 PHYAR = 0x60,
140 TBICSR = 0x64,
141 TBI_ANAR = 0x68,
142 TBI_LPAR = 0x6A,
143 PHYstatus = 0x6C,
144 RxMaxSize = 0xDA,
145 CPlusCmd = 0xE0,
146 RxDescStartAddrLow = 0xE4,
147 RxDescStartAddrHigh = 0xE8,
148 EarlyTxThres = 0xEC,
149 FuncEvent = 0xF0,
150 FuncEventMask = 0xF4,
151 FuncPresetState = 0xF8,
152 FuncForceEvent = 0xFC,
153 };
154
155 enum RTL8169_register_content {
156 /*InterruptStatusBits */
157 SYSErr = 0x8000,
158 PCSTimeout = 0x4000,
159 SWInt = 0x0100,
160 TxDescUnavail = 0x80,
161 RxFIFOOver = 0x40,
162 RxUnderrun = 0x20,
163 RxOverflow = 0x10,
164 TxErr = 0x08,
165 TxOK = 0x04,
166 RxErr = 0x02,
167 RxOK = 0x01,
168
169 /*RxStatusDesc */
170 RxRES = 0x00200000,
171 RxCRC = 0x00080000,
172 RxRUNT = 0x00100000,
173 RxRWT = 0x00400000,
174
175 /*ChipCmdBits */
176 CmdReset = 0x10,
177 CmdRxEnb = 0x08,
178 CmdTxEnb = 0x04,
179 RxBufEmpty = 0x01,
180
181 /*Cfg9346Bits */
182 Cfg9346_Lock = 0x00,
183 Cfg9346_Unlock = 0xC0,
184
185 /*rx_mode_bits */
186 AcceptErr = 0x20,
187 AcceptRunt = 0x10,
188 AcceptBroadcast = 0x08,
189 AcceptMulticast = 0x04,
190 AcceptMyPhys = 0x02,
191 AcceptAllPhys = 0x01,
192
193 /*RxConfigBits */
194 RxCfgFIFOShift = 13,
195 RxCfgDMAShift = 8,
196
197 /*TxConfigBits */
198 TxInterFrameGapShift = 24,
199 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
200
201 /*rtl8169_PHYstatus */
202 TBI_Enable = 0x80,
203 TxFlowCtrl = 0x40,
204 RxFlowCtrl = 0x20,
205 _1000bpsF = 0x10,
206 _100bps = 0x08,
207 _10bps = 0x04,
208 LinkStatus = 0x02,
209 FullDup = 0x01,
210
211 /*GIGABIT_PHY_registers */
212 PHY_CTRL_REG = 0,
213 PHY_STAT_REG = 1,
214 PHY_AUTO_NEGO_REG = 4,
215 PHY_1000_CTRL_REG = 9,
216
217 /*GIGABIT_PHY_REG_BIT */
218 PHY_Restart_Auto_Nego = 0x0200,
219 PHY_Enable_Auto_Nego = 0x1000,
220
221 /* PHY_STAT_REG = 1; */
222 PHY_Auto_Nego_Comp = 0x0020,
223
224 /* PHY_AUTO_NEGO_REG = 4; */
225 PHY_Cap_10_Half = 0x0020,
226 PHY_Cap_10_Full = 0x0040,
227 PHY_Cap_100_Half = 0x0080,
228 PHY_Cap_100_Full = 0x0100,
229
230 /* PHY_1000_CTRL_REG = 9; */
231 PHY_Cap_1000_Full = 0x0200,
232
233 PHY_Cap_Null = 0x0,
234
235 /*_MediaType*/
236 _10_Half = 0x01,
237 _10_Full = 0x02,
238 _100_Half = 0x04,
239 _100_Full = 0x08,
240 _1000_Full = 0x10,
241
242 /*_TBICSRBit*/
243 TBILinkOK = 0x02000000,
244 };
245
246 static struct {
247 const char *name;
248 u8 version; /* depend on RTL8169 docs */
249 u32 RxConfigMask; /* should clear the bits supported by this chip */
250 } rtl_chip_info[] = {
251 {"RTL-8169", 0x00, 0xff7e1880,},
252 {"RTL-8169", 0x04, 0xff7e1880,},
253 {"RTL-8169", 0x00, 0xff7e1880,},
254 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
255 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
256 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
257 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
258 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
259 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
260 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
261 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
262 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
263 {"RTL-8101e", 0x34, 0xff7e1880,},
264 {"RTL-8100e", 0x32, 0xff7e1880,},
265 };
266
267 enum _DescStatusBit {
268 OWNbit = 0x80000000,
269 EORbit = 0x40000000,
270 FSbit = 0x20000000,
271 LSbit = 0x10000000,
272 };
273
274 struct TxDesc {
275 u32 status;
276 u32 vlan_tag;
277 u32 buf_addr;
278 u32 buf_Haddr;
279 };
280
281 struct RxDesc {
282 u32 status;
283 u32 vlan_tag;
284 u32 buf_addr;
285 u32 buf_Haddr;
286 };
287
288 static unsigned char rxdata[RX_BUF_LEN];
289
290 #define RTL8169_DESC_SIZE 16
291
292 #if ARCH_DMA_MINALIGN > 256
293 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
294 #else
295 # define RTL8169_ALIGN 256
296 #endif
297
298 /*
299 * Warn if the cache-line size is larger than the descriptor size. In such
300 * cases the driver will likely fail because the CPU needs to flush the cache
301 * when requeuing RX buffers, therefore descriptors written by the hardware
302 * may be discarded.
303 *
304 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
305 * the driver to allocate descriptors from a pool of non-cached memory.
306 */
307 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
308 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
309 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
310 #warning cache-line size is larger than descriptor size
311 #endif
312 #endif
313
314 /*
315 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
316 * descriptors point to a part of this buffer.
317 */
318 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
319
320 /*
321 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
322 * descriptors point to a part of this buffer.
323 */
324 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
325
326 struct rtl8169_private {
327 ulong iobase;
328 void *mmio_addr; /* memory map physical address */
329 int chipset;
330 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
331 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
332 unsigned long dirty_tx;
333 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
334 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
335 unsigned char *RxBufferRings; /* Index of Rx Buffer */
336 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
337 unsigned char *Tx_skbuff[NUM_TX_DESC];
338 } tpx;
339
340 static struct rtl8169_private *tpc;
341
342 static const u16 rtl8169_intr_mask =
343 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
344 TxOK | RxErr | RxOK;
345 static const unsigned int rtl8169_rx_config =
346 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
347
348 static struct pci_device_id supported[] = {
349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
351 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
352 {}
353 };
354
355 void mdio_write(int RegAddr, int value)
356 {
357 int i;
358
359 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
360 udelay(1000);
361
362 for (i = 2000; i > 0; i--) {
363 /* Check if the RTL8169 has completed writing to the specified MII register */
364 if (!(RTL_R32(PHYAR) & 0x80000000)) {
365 break;
366 } else {
367 udelay(100);
368 }
369 }
370 }
371
372 int mdio_read(int RegAddr)
373 {
374 int i, value = -1;
375
376 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
377 udelay(1000);
378
379 for (i = 2000; i > 0; i--) {
380 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
381 if (RTL_R32(PHYAR) & 0x80000000) {
382 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
383 break;
384 } else {
385 udelay(100);
386 }
387 }
388 return value;
389 }
390
391 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
392 {
393 int i;
394 u32 tmp;
395
396 #ifdef DEBUG_RTL8169
397 printf ("%s\n", __FUNCTION__);
398 #endif
399 ioaddr = dev_iobase;
400
401 /* Soft reset the chip. */
402 RTL_W8(ChipCmd, CmdReset);
403
404 /* Check that the chip has finished the reset. */
405 for (i = 1000; i > 0; i--)
406 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
407 break;
408 else
409 udelay(10);
410
411 /* identify chip attached to board */
412 tmp = RTL_R32(TxConfig);
413 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
414
415 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
416 if (tmp == rtl_chip_info[i].version) {
417 tpc->chipset = i;
418 goto match;
419 }
420 }
421
422 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
423 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
424 name);
425 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
426 tpc->chipset = 0;
427
428 match:
429 return 0;
430 }
431
432 /*
433 * TX and RX descriptors are 16 bytes. This causes problems with the cache
434 * maintenance on CPUs where the cache-line size exceeds the size of these
435 * descriptors. What will happen is that when the driver receives a packet
436 * it will be immediately requeued for the hardware to reuse. The CPU will
437 * therefore need to flush the cache-line containing the descriptor, which
438 * will cause all other descriptors in the same cache-line to be flushed
439 * along with it. If one of those descriptors had been written to by the
440 * device those changes (and the associated packet) will be lost.
441 *
442 * To work around this, we make use of non-cached memory if available. If
443 * descriptors are mapped uncached there's no need to manually flush them
444 * or invalidate them.
445 *
446 * Note that this only applies to descriptors. The packet data buffers do
447 * not have the same constraints since they are 1536 bytes large, so they
448 * are unlikely to share cache-lines.
449 */
450 static void *rtl_alloc_descs(unsigned int num)
451 {
452 size_t size = num * RTL8169_DESC_SIZE;
453
454 #ifdef CONFIG_SYS_NONCACHED_MEMORY
455 return (void *)noncached_alloc(size, RTL8169_ALIGN);
456 #else
457 return memalign(RTL8169_ALIGN, size);
458 #endif
459 }
460
461 /*
462 * Cache maintenance functions. These are simple wrappers around the more
463 * general purpose flush_cache() and invalidate_dcache_range() functions.
464 */
465
466 static void rtl_inval_rx_desc(struct RxDesc *desc)
467 {
468 #ifndef CONFIG_SYS_NONCACHED_MEMORY
469 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
470 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
471
472 invalidate_dcache_range(start, end);
473 #endif
474 }
475
476 static void rtl_flush_rx_desc(struct RxDesc *desc)
477 {
478 #ifndef CONFIG_SYS_NONCACHED_MEMORY
479 flush_cache((unsigned long)desc, sizeof(*desc));
480 #endif
481 }
482
483 static void rtl_inval_tx_desc(struct TxDesc *desc)
484 {
485 #ifndef CONFIG_SYS_NONCACHED_MEMORY
486 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
487 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
488
489 invalidate_dcache_range(start, end);
490 #endif
491 }
492
493 static void rtl_flush_tx_desc(struct TxDesc *desc)
494 {
495 #ifndef CONFIG_SYS_NONCACHED_MEMORY
496 flush_cache((unsigned long)desc, sizeof(*desc));
497 #endif
498 }
499
500 static void rtl_inval_buffer(void *buf, size_t size)
501 {
502 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
503 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
504
505 invalidate_dcache_range(start, end);
506 }
507
508 static void rtl_flush_buffer(void *buf, size_t size)
509 {
510 flush_cache((unsigned long)buf, size);
511 }
512
513 /**************************************************************************
514 RECV - Receive a frame
515 ***************************************************************************/
516 #ifdef CONFIG_DM_ETH
517 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
518 uchar **packetp)
519 #else
520 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
521 uchar **packetp)
522 #endif
523 {
524 /* return true if there's an ethernet packet ready to read */
525 /* nic->packet should contain data on return */
526 /* nic->packetlen should contain length of data */
527 int cur_rx;
528 int length = 0;
529
530 #ifdef DEBUG_RTL8169_RX
531 printf ("%s\n", __FUNCTION__);
532 #endif
533 ioaddr = dev_iobase;
534
535 cur_rx = tpc->cur_rx;
536
537 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
538
539 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
540 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
541 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
542 status) & 0x00001FFF) - 4;
543
544 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
545 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
546
547 if (cur_rx == NUM_RX_DESC - 1)
548 tpc->RxDescArray[cur_rx].status =
549 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
550 else
551 tpc->RxDescArray[cur_rx].status =
552 cpu_to_le32(OWNbit + RX_BUF_SIZE);
553 #ifdef CONFIG_DM_ETH
554 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
555 dm_pci_mem_to_phys(dev,
556 (pci_addr_t)(unsigned long)
557 tpc->RxBufferRing[cur_rx]));
558 #else
559 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
560 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
561 tpc->RxBufferRing[cur_rx]));
562 #endif
563 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
564 #ifdef CONFIG_DM_ETH
565 *packetp = rxdata;
566 #else
567 net_process_received_packet(rxdata, length);
568 #endif
569 } else {
570 puts("Error Rx");
571 length = -EIO;
572 }
573 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
574 tpc->cur_rx = cur_rx;
575 return length;
576
577 } else {
578 ushort sts = RTL_R8(IntrStatus);
579 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
580 udelay(100); /* wait */
581 }
582 tpc->cur_rx = cur_rx;
583 return (0); /* initially as this is called to flush the input */
584 }
585
586 #ifdef CONFIG_DM_ETH
587 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
588 {
589 struct rtl8169_private *priv = dev_get_priv(dev);
590
591 return rtl_recv_common(dev, priv->iobase, packetp);
592 }
593 #else
594 static int rtl_recv(struct eth_device *dev)
595 {
596 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
597 dev->iobase, NULL);
598 }
599 #endif /* nCONFIG_DM_ETH */
600
601 #define HZ 1000
602 /**************************************************************************
603 SEND - Transmit a frame
604 ***************************************************************************/
605 #ifdef CONFIG_DM_ETH
606 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
607 void *packet, int length)
608 #else
609 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
610 void *packet, int length)
611 #endif
612 {
613 /* send the packet to destination */
614
615 u32 to;
616 u8 *ptxb;
617 int entry = tpc->cur_tx % NUM_TX_DESC;
618 u32 len = length;
619 int ret;
620
621 #ifdef DEBUG_RTL8169_TX
622 int stime = currticks();
623 printf ("%s\n", __FUNCTION__);
624 printf("sending %d bytes\n", len);
625 #endif
626
627 ioaddr = dev_iobase;
628
629 /* point to the current txb incase multiple tx_rings are used */
630 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
631 memcpy(ptxb, (char *)packet, (int)length);
632 rtl_flush_buffer(ptxb, length);
633
634 while (len < ETH_ZLEN)
635 ptxb[len++] = '\0';
636
637 tpc->TxDescArray[entry].buf_Haddr = 0;
638 #ifdef CONFIG_DM_ETH
639 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
640 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
641 #else
642 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
643 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
644 #endif
645 if (entry != (NUM_TX_DESC - 1)) {
646 tpc->TxDescArray[entry].status =
647 cpu_to_le32((OWNbit | FSbit | LSbit) |
648 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
649 } else {
650 tpc->TxDescArray[entry].status =
651 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
652 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
653 }
654 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
655 RTL_W8(TxPoll, 0x40); /* set polling bit */
656
657 tpc->cur_tx++;
658 to = currticks() + TX_TIMEOUT;
659 do {
660 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
661 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
662 && (currticks() < to)); /* wait */
663
664 if (currticks() >= to) {
665 #ifdef DEBUG_RTL8169_TX
666 puts("tx timeout/error\n");
667 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
668 #endif
669 ret = 0;
670 } else {
671 #ifdef DEBUG_RTL8169_TX
672 puts("tx done\n");
673 #endif
674 ret = length;
675 }
676 /* Delay to make net console (nc) work properly */
677 udelay(20);
678 return ret;
679 }
680
681 #ifdef CONFIG_DM_ETH
682 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
683 {
684 struct rtl8169_private *priv = dev_get_priv(dev);
685
686 return rtl_send_common(dev, priv->iobase, packet, length);
687 }
688
689 #else
690 static int rtl_send(struct eth_device *dev, void *packet, int length)
691 {
692 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
693 dev->iobase, packet, length);
694 }
695 #endif
696
697 static void rtl8169_set_rx_mode(void)
698 {
699 u32 mc_filter[2]; /* Multicast hash filter */
700 int rx_mode;
701 u32 tmp = 0;
702
703 #ifdef DEBUG_RTL8169
704 printf ("%s\n", __FUNCTION__);
705 #endif
706
707 /* IFF_ALLMULTI */
708 /* Too many to filter perfectly -- accept all multicasts. */
709 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
710 mc_filter[1] = mc_filter[0] = 0xffffffff;
711
712 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
713 rtl_chip_info[tpc->chipset].RxConfigMask);
714
715 RTL_W32(RxConfig, tmp);
716 RTL_W32(MAR0 + 0, mc_filter[0]);
717 RTL_W32(MAR0 + 4, mc_filter[1]);
718 }
719
720 #ifdef CONFIG_DM_ETH
721 static void rtl8169_hw_start(struct udevice *dev)
722 #else
723 static void rtl8169_hw_start(pci_dev_t dev)
724 #endif
725 {
726 u32 i;
727
728 #ifdef DEBUG_RTL8169
729 int stime = currticks();
730 printf ("%s\n", __FUNCTION__);
731 #endif
732
733 #if 0
734 /* Soft reset the chip. */
735 RTL_W8(ChipCmd, CmdReset);
736
737 /* Check that the chip has finished the reset. */
738 for (i = 1000; i > 0; i--) {
739 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
740 break;
741 else
742 udelay(10);
743 }
744 #endif
745
746 RTL_W8(Cfg9346, Cfg9346_Unlock);
747
748 /* RTL-8169sb/8110sb or previous version */
749 if (tpc->chipset <= 5)
750 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
751
752 RTL_W8(EarlyTxThres, EarlyTxThld);
753
754 /* For gigabit rtl8169 */
755 RTL_W16(RxMaxSize, RxPacketMaxSize);
756
757 /* Set Rx Config register */
758 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
759 rtl_chip_info[tpc->chipset].RxConfigMask);
760 RTL_W32(RxConfig, i);
761
762 /* Set DMA burst size and Interframe Gap Time */
763 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
764 (InterFrameGap << TxInterFrameGapShift));
765
766
767 tpc->cur_rx = 0;
768
769 #ifdef CONFIG_DM_ETH
770 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
771 (pci_addr_t)(unsigned long)tpc->TxDescArray));
772 #else
773 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
774 (pci_addr_t)(unsigned long)tpc->TxDescArray));
775 #endif
776 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
777 #ifdef CONFIG_DM_ETH
778 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
779 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
780 #else
781 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
782 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
783 #endif
784 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
785
786 /* RTL-8169sc/8110sc or later version */
787 if (tpc->chipset > 5)
788 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
789
790 RTL_W8(Cfg9346, Cfg9346_Lock);
791 udelay(10);
792
793 RTL_W32(RxMissed, 0);
794
795 rtl8169_set_rx_mode();
796
797 /* no early-rx interrupts */
798 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
799
800 #ifdef DEBUG_RTL8169
801 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
802 #endif
803 }
804
805 #ifdef CONFIG_DM_ETH
806 static void rtl8169_init_ring(struct udevice *dev)
807 #else
808 static void rtl8169_init_ring(pci_dev_t dev)
809 #endif
810 {
811 int i;
812
813 #ifdef DEBUG_RTL8169
814 int stime = currticks();
815 printf ("%s\n", __FUNCTION__);
816 #endif
817
818 tpc->cur_rx = 0;
819 tpc->cur_tx = 0;
820 tpc->dirty_tx = 0;
821 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
822 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
823
824 for (i = 0; i < NUM_TX_DESC; i++) {
825 tpc->Tx_skbuff[i] = &txb[i];
826 }
827
828 for (i = 0; i < NUM_RX_DESC; i++) {
829 if (i == (NUM_RX_DESC - 1))
830 tpc->RxDescArray[i].status =
831 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
832 else
833 tpc->RxDescArray[i].status =
834 cpu_to_le32(OWNbit + RX_BUF_SIZE);
835
836 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
837 #ifdef CONFIG_DM_ETH
838 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
839 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
840 #else
841 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
842 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
843 #endif
844 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
845 }
846
847 #ifdef DEBUG_RTL8169
848 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
849 #endif
850 }
851
852 #ifdef CONFIG_DM_ETH
853 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr)
854 #else
855 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
856 #endif
857 {
858 int i;
859
860 #ifdef DEBUG_RTL8169
861 int stime = currticks();
862 printf ("%s\n", __FUNCTION__);
863 #endif
864
865 rtl8169_init_ring(dev);
866 rtl8169_hw_start(dev);
867 /* Construct a perfect filter frame with the mac address as first match
868 * and broadcast for all others */
869 for (i = 0; i < 192; i++)
870 txb[i] = 0xFF;
871
872 txb[0] = enetaddr[0];
873 txb[1] = enetaddr[1];
874 txb[2] = enetaddr[2];
875 txb[3] = enetaddr[3];
876 txb[4] = enetaddr[4];
877 txb[5] = enetaddr[5];
878
879 #ifdef DEBUG_RTL8169
880 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
881 #endif
882 }
883
884 #ifdef CONFIG_DM_ETH
885 static int rtl8169_eth_start(struct udevice *dev)
886 {
887 struct eth_pdata *plat = dev_get_platdata(dev);
888
889 rtl8169_common_start(dev, plat->enetaddr);
890
891 return 0;
892 }
893 #else
894 /**************************************************************************
895 RESET - Finish setting up the ethernet interface
896 ***************************************************************************/
897 static int rtl_reset(struct eth_device *dev, bd_t *bis)
898 {
899 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
900 dev->enetaddr);
901
902 return 0;
903 }
904 #endif /* nCONFIG_DM_ETH */
905
906 static void rtl_halt_common(unsigned long dev_iobase)
907 {
908 int i;
909
910 #ifdef DEBUG_RTL8169
911 printf ("%s\n", __FUNCTION__);
912 #endif
913
914 ioaddr = dev_iobase;
915
916 /* Stop the chip's Tx and Rx DMA processes. */
917 RTL_W8(ChipCmd, 0x00);
918
919 /* Disable interrupts by clearing the interrupt mask. */
920 RTL_W16(IntrMask, 0x0000);
921
922 RTL_W32(RxMissed, 0);
923
924 for (i = 0; i < NUM_RX_DESC; i++) {
925 tpc->RxBufferRing[i] = NULL;
926 }
927 }
928
929 #ifdef CONFIG_DM_ETH
930 void rtl8169_eth_stop(struct udevice *dev)
931 {
932 struct rtl8169_private *priv = dev_get_priv(dev);
933
934 rtl_halt_common(priv->iobase);
935 }
936 #else
937 /**************************************************************************
938 HALT - Turn off ethernet interface
939 ***************************************************************************/
940 static void rtl_halt(struct eth_device *dev)
941 {
942 rtl_halt_common(dev->iobase);
943 }
944 #endif
945
946 /**************************************************************************
947 INIT - Look for an adapter, this routine's visible to the outside
948 ***************************************************************************/
949
950 #define board_found 1
951 #define valid_link 0
952 static int rtl_init(unsigned long dev_ioaddr, const char *name,
953 unsigned char *enetaddr)
954 {
955 static int board_idx = -1;
956 int i, rc;
957 int option = -1, Cap10_100 = 0, Cap1000 = 0;
958
959 #ifdef DEBUG_RTL8169
960 printf ("%s\n", __FUNCTION__);
961 #endif
962 ioaddr = dev_ioaddr;
963
964 board_idx++;
965
966 /* point to private storage */
967 tpc = &tpx;
968
969 rc = rtl8169_init_board(ioaddr, name);
970 if (rc)
971 return rc;
972
973 /* Get MAC address. FIXME: read EEPROM */
974 for (i = 0; i < MAC_ADDR_LEN; i++)
975 enetaddr[i] = RTL_R8(MAC0 + i);
976
977 #ifdef DEBUG_RTL8169
978 printf("chipset = %d\n", tpc->chipset);
979 printf("MAC Address");
980 for (i = 0; i < MAC_ADDR_LEN; i++)
981 printf(":%02x", enetaddr[i]);
982 putc('\n');
983 #endif
984
985 #ifdef DEBUG_RTL8169
986 /* Print out some hardware info */
987 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
988 #endif
989
990 /* if TBI is not endbled */
991 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
992 int val = mdio_read(PHY_AUTO_NEGO_REG);
993
994 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
995 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
996 if (option > 0) {
997 #ifdef DEBUG_RTL8169
998 printf("%s: Force-mode Enabled.\n", dev->name);
999 #endif
1000 Cap10_100 = 0, Cap1000 = 0;
1001 switch (option) {
1002 case _10_Half:
1003 Cap10_100 = PHY_Cap_10_Half;
1004 Cap1000 = PHY_Cap_Null;
1005 break;
1006 case _10_Full:
1007 Cap10_100 = PHY_Cap_10_Full;
1008 Cap1000 = PHY_Cap_Null;
1009 break;
1010 case _100_Half:
1011 Cap10_100 = PHY_Cap_100_Half;
1012 Cap1000 = PHY_Cap_Null;
1013 break;
1014 case _100_Full:
1015 Cap10_100 = PHY_Cap_100_Full;
1016 Cap1000 = PHY_Cap_Null;
1017 break;
1018 case _1000_Full:
1019 Cap10_100 = PHY_Cap_Null;
1020 Cap1000 = PHY_Cap_1000_Full;
1021 break;
1022 default:
1023 break;
1024 }
1025 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1026 mdio_write(PHY_1000_CTRL_REG, Cap1000);
1027 } else {
1028 #ifdef DEBUG_RTL8169
1029 printf("%s: Auto-negotiation Enabled.\n",
1030 dev->name);
1031 #endif
1032 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1033 mdio_write(PHY_AUTO_NEGO_REG,
1034 PHY_Cap_10_Half | PHY_Cap_10_Full |
1035 PHY_Cap_100_Half | PHY_Cap_100_Full |
1036 (val & 0x1F));
1037
1038 /* enable 1000 Full Mode */
1039 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1040
1041 }
1042
1043 /* Enable auto-negotiation and restart auto-nigotiation */
1044 mdio_write(PHY_CTRL_REG,
1045 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1046 udelay(100);
1047
1048 /* wait for auto-negotiation process */
1049 for (i = 10000; i > 0; i--) {
1050 /* check if auto-negotiation complete */
1051 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1052 udelay(100);
1053 option = RTL_R8(PHYstatus);
1054 if (option & _1000bpsF) {
1055 #ifdef DEBUG_RTL8169
1056 printf("%s: 1000Mbps Full-duplex operation.\n",
1057 dev->name);
1058 #endif
1059 } else {
1060 #ifdef DEBUG_RTL8169
1061 printf("%s: %sMbps %s-duplex operation.\n",
1062 dev->name,
1063 (option & _100bps) ? "100" :
1064 "10",
1065 (option & FullDup) ? "Full" :
1066 "Half");
1067 #endif
1068 }
1069 break;
1070 } else {
1071 udelay(100);
1072 }
1073 } /* end for-loop to wait for auto-negotiation process */
1074
1075 } else {
1076 udelay(100);
1077 #ifdef DEBUG_RTL8169
1078 printf
1079 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1080 dev->name,
1081 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1082 #endif
1083 }
1084
1085
1086 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1087 if (!tpc->RxDescArray)
1088 return -ENOMEM;
1089
1090 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1091 if (!tpc->TxDescArray)
1092 return -ENOMEM;
1093
1094 return 0;
1095 }
1096
1097 #ifndef CONFIG_DM_ETH
1098 int rtl8169_initialize(bd_t *bis)
1099 {
1100 pci_dev_t devno;
1101 int card_number = 0;
1102 struct eth_device *dev;
1103 u32 iobase;
1104 int idx=0;
1105
1106 while(1){
1107 unsigned int region;
1108 u16 device;
1109 int err;
1110
1111 /* Find RTL8169 */
1112 if ((devno = pci_find_devices(supported, idx++)) < 0)
1113 break;
1114
1115 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1116 switch (device) {
1117 case 0x8168:
1118 region = 2;
1119 break;
1120
1121 default:
1122 region = 1;
1123 break;
1124 }
1125
1126 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1127 iobase &= ~0xf;
1128
1129 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1130
1131 dev = (struct eth_device *)malloc(sizeof *dev);
1132 if (!dev) {
1133 printf("Can not allocate memory of rtl8169\n");
1134 break;
1135 }
1136
1137 memset(dev, 0, sizeof(*dev));
1138 sprintf (dev->name, "RTL8169#%d", card_number);
1139
1140 dev->priv = (void *)(unsigned long)devno;
1141 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1142
1143 dev->init = rtl_reset;
1144 dev->halt = rtl_halt;
1145 dev->send = rtl_send;
1146 dev->recv = rtl_recv;
1147
1148 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1149 if (err < 0) {
1150 printf(pr_fmt("failed to initialize card: %d\n"), err);
1151 free(dev);
1152 continue;
1153 }
1154
1155 eth_register (dev);
1156
1157 card_number++;
1158 }
1159 return card_number;
1160 }
1161 #endif
1162
1163 #ifdef CONFIG_DM_ETH
1164 static int rtl8169_eth_probe(struct udevice *dev)
1165 {
1166 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1167 struct rtl8169_private *priv = dev_get_priv(dev);
1168 struct eth_pdata *plat = dev_get_platdata(dev);
1169 u32 iobase;
1170 int region;
1171 int ret;
1172
1173 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1174 switch (pplat->device) {
1175 case 0x8168:
1176 region = 2;
1177 break;
1178 default:
1179 region = 1;
1180 break;
1181 }
1182 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1183 iobase &= ~0xf;
1184 priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1185
1186 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1187 if (ret < 0) {
1188 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1189 return ret;
1190 }
1191
1192 return 0;
1193 }
1194
1195 static const struct eth_ops rtl8169_eth_ops = {
1196 .start = rtl8169_eth_start,
1197 .send = rtl8169_eth_send,
1198 .recv = rtl8169_eth_recv,
1199 .stop = rtl8169_eth_stop,
1200 };
1201
1202 static const struct udevice_id rtl8169_eth_ids[] = {
1203 { .compatible = "realtek,rtl8169" },
1204 { }
1205 };
1206
1207 U_BOOT_DRIVER(eth_rtl8169) = {
1208 .name = "eth_rtl8169",
1209 .id = UCLASS_ETH,
1210 .of_match = rtl8169_eth_ids,
1211 .probe = rtl8169_eth_probe,
1212 .ops = &rtl8169_eth_ops,
1213 .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1214 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1215 };
1216
1217 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1218 #endif
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