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[people/ms/u-boot.git] / drivers / net / sh_eth.c
1 /*
2 * sh_eth.c - Driver for Renesas ethernet controller.
3 *
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <malloc.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <miiphy.h>
18 #include <linux/errno.h>
19 #include <asm/io.h>
20
21 #ifdef CONFIG_DM_ETH
22 #include <clk.h>
23 #include <dm.h>
24 #include <linux/mii.h>
25 #include <asm/gpio.h>
26 #endif
27
28 #include "sh_eth.h"
29
30 #ifndef CONFIG_SH_ETHER_USE_PORT
31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
32 #endif
33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
35 #endif
36
37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
38 #define flush_cache_wback(addr, len) \
39 flush_dcache_range((u32)addr, \
40 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
41 #else
42 #define flush_cache_wback(...)
43 #endif
44
45 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
46 #define invalidate_cache(addr, len) \
47 { \
48 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
49 u32 start, end; \
50 \
51 start = (u32)addr; \
52 end = start + len; \
53 start &= ~(line_size - 1); \
54 end = ((end + line_size - 1) & ~(line_size - 1)); \
55 \
56 invalidate_dcache_range(start, end); \
57 }
58 #else
59 #define invalidate_cache(...)
60 #endif
61
62 #define TIMEOUT_CNT 1000
63
64 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
65 {
66 int ret = 0, timeout;
67 struct sh_eth_info *port_info = &eth->port_info[eth->port];
68
69 if (!packet || len > 0xffff) {
70 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
71 ret = -EINVAL;
72 goto err;
73 }
74
75 /* packet must be a 4 byte boundary */
76 if ((int)packet & 3) {
77 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
78 , __func__);
79 ret = -EFAULT;
80 goto err;
81 }
82
83 /* Update tx descriptor */
84 flush_cache_wback(packet, len);
85 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
86 port_info->tx_desc_cur->td1 = len << 16;
87 /* Must preserve the end of descriptor list indication */
88 if (port_info->tx_desc_cur->td0 & TD_TDLE)
89 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
90 else
91 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
92
93 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
94
95 /* Restart the transmitter if disabled */
96 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
97 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
98
99 /* Wait until packet is transmitted */
100 timeout = TIMEOUT_CNT;
101 do {
102 invalidate_cache(port_info->tx_desc_cur,
103 sizeof(struct tx_desc_s));
104 udelay(100);
105 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
106
107 if (timeout < 0) {
108 printf(SHETHER_NAME ": transmit timeout\n");
109 ret = -ETIMEDOUT;
110 goto err;
111 }
112
113 port_info->tx_desc_cur++;
114 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
115 port_info->tx_desc_cur = port_info->tx_desc_base;
116
117 err:
118 return ret;
119 }
120
121 static int sh_eth_recv_start(struct sh_eth_dev *eth)
122 {
123 int len = 0;
124 struct sh_eth_info *port_info = &eth->port_info[eth->port];
125
126 /* Check if the rx descriptor is ready */
127 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
128 if (port_info->rx_desc_cur->rd0 & RD_RACT)
129 return -EINVAL;
130
131 /* Check for errors */
132 if (port_info->rx_desc_cur->rd0 & RD_RFE)
133 return -EINVAL;
134
135 len = port_info->rx_desc_cur->rd1 & 0xffff;
136
137 return len;
138 }
139
140 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
141 {
142 struct sh_eth_info *port_info = &eth->port_info[eth->port];
143
144 /* Make current descriptor available again */
145 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
146 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
147 else
148 port_info->rx_desc_cur->rd0 = RD_RACT;
149
150 flush_cache_wback(port_info->rx_desc_cur,
151 sizeof(struct rx_desc_s));
152
153 /* Point to the next descriptor */
154 port_info->rx_desc_cur++;
155 if (port_info->rx_desc_cur >=
156 port_info->rx_desc_base + NUM_RX_DESC)
157 port_info->rx_desc_cur = port_info->rx_desc_base;
158 }
159
160 static int sh_eth_reset(struct sh_eth_dev *eth)
161 {
162 struct sh_eth_info *port_info = &eth->port_info[eth->port];
163 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
164 int ret = 0, i;
165
166 /* Start e-dmac transmitter and receiver */
167 sh_eth_write(port_info, EDSR_ENALL, EDSR);
168
169 /* Perform a software reset and wait for it to complete */
170 sh_eth_write(port_info, EDMR_SRST, EDMR);
171 for (i = 0; i < TIMEOUT_CNT; i++) {
172 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
173 break;
174 udelay(1000);
175 }
176
177 if (i == TIMEOUT_CNT) {
178 printf(SHETHER_NAME ": Software reset timeout\n");
179 ret = -EIO;
180 }
181
182 return ret;
183 #else
184 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
185 udelay(3000);
186 sh_eth_write(port_info,
187 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
188
189 return 0;
190 #endif
191 }
192
193 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
194 {
195 int i, ret = 0;
196 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
197 struct sh_eth_info *port_info = &eth->port_info[eth->port];
198 struct tx_desc_s *cur_tx_desc;
199
200 /*
201 * Allocate rx descriptors. They must be aligned to size of struct
202 * tx_desc_s.
203 */
204 port_info->tx_desc_alloc =
205 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
206 if (!port_info->tx_desc_alloc) {
207 printf(SHETHER_NAME ": memalign failed\n");
208 ret = -ENOMEM;
209 goto err;
210 }
211
212 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
213
214 /* Make sure we use a P2 address (non-cacheable) */
215 port_info->tx_desc_base =
216 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
217 port_info->tx_desc_cur = port_info->tx_desc_base;
218
219 /* Initialize all descriptors */
220 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
221 cur_tx_desc++, i++) {
222 cur_tx_desc->td0 = 0x00;
223 cur_tx_desc->td1 = 0x00;
224 cur_tx_desc->td2 = 0x00;
225 }
226
227 /* Mark the end of the descriptors */
228 cur_tx_desc--;
229 cur_tx_desc->td0 |= TD_TDLE;
230
231 /*
232 * Point the controller to the tx descriptor list. Must use physical
233 * addresses
234 */
235 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
236 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
237 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
238 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
239 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
240 #endif
241
242 err:
243 return ret;
244 }
245
246 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
247 {
248 int i, ret = 0;
249 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
250 struct sh_eth_info *port_info = &eth->port_info[eth->port];
251 struct rx_desc_s *cur_rx_desc;
252 u8 *rx_buf;
253
254 /*
255 * Allocate rx descriptors. They must be aligned to size of struct
256 * rx_desc_s.
257 */
258 port_info->rx_desc_alloc =
259 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
260 if (!port_info->rx_desc_alloc) {
261 printf(SHETHER_NAME ": memalign failed\n");
262 ret = -ENOMEM;
263 goto err;
264 }
265
266 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
267
268 /* Make sure we use a P2 address (non-cacheable) */
269 port_info->rx_desc_base =
270 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
271
272 port_info->rx_desc_cur = port_info->rx_desc_base;
273
274 /*
275 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
276 * aligned and in P2 area.
277 */
278 port_info->rx_buf_alloc =
279 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
280 if (!port_info->rx_buf_alloc) {
281 printf(SHETHER_NAME ": alloc failed\n");
282 ret = -ENOMEM;
283 goto err_buf_alloc;
284 }
285
286 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
287
288 /* Initialize all descriptors */
289 for (cur_rx_desc = port_info->rx_desc_base,
290 rx_buf = port_info->rx_buf_base, i = 0;
291 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
292 cur_rx_desc->rd0 = RD_RACT;
293 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
294 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
295 }
296
297 /* Mark the end of the descriptors */
298 cur_rx_desc--;
299 cur_rx_desc->rd0 |= RD_RDLE;
300
301 /* Point the controller to the rx descriptor list */
302 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
303 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
304 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
305 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
306 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
307 #endif
308
309 return ret;
310
311 err_buf_alloc:
312 free(port_info->rx_desc_alloc);
313 port_info->rx_desc_alloc = NULL;
314
315 err:
316 return ret;
317 }
318
319 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
320 {
321 struct sh_eth_info *port_info = &eth->port_info[eth->port];
322
323 if (port_info->tx_desc_alloc) {
324 free(port_info->tx_desc_alloc);
325 port_info->tx_desc_alloc = NULL;
326 }
327 }
328
329 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
330 {
331 struct sh_eth_info *port_info = &eth->port_info[eth->port];
332
333 if (port_info->rx_desc_alloc) {
334 free(port_info->rx_desc_alloc);
335 port_info->rx_desc_alloc = NULL;
336 }
337
338 if (port_info->rx_buf_alloc) {
339 free(port_info->rx_buf_alloc);
340 port_info->rx_buf_alloc = NULL;
341 }
342 }
343
344 static int sh_eth_desc_init(struct sh_eth_dev *eth)
345 {
346 int ret = 0;
347
348 ret = sh_eth_tx_desc_init(eth);
349 if (ret)
350 goto err_tx_init;
351
352 ret = sh_eth_rx_desc_init(eth);
353 if (ret)
354 goto err_rx_init;
355
356 return ret;
357 err_rx_init:
358 sh_eth_tx_desc_free(eth);
359
360 err_tx_init:
361 return ret;
362 }
363
364 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
365 unsigned char *mac)
366 {
367 u32 val;
368
369 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
370 sh_eth_write(port_info, val, MAHR);
371
372 val = (mac[4] << 8) | mac[5];
373 sh_eth_write(port_info, val, MALR);
374 }
375
376 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
377 {
378 struct sh_eth_info *port_info = &eth->port_info[eth->port];
379
380 /* Configure e-dmac registers */
381 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
382 (EMDR_DESC | EDMR_EL), EDMR);
383
384 sh_eth_write(port_info, 0, EESIPR);
385 sh_eth_write(port_info, 0, TRSCER);
386 sh_eth_write(port_info, 0, TFTR);
387 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
388 sh_eth_write(port_info, RMCR_RST, RMCR);
389 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
390 sh_eth_write(port_info, 0, RPADIR);
391 #endif
392 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
393
394 /* Configure e-mac registers */
395 sh_eth_write(port_info, 0, ECSIPR);
396
397 /* Set Mac address */
398 sh_eth_write_hwaddr(port_info, mac);
399
400 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
401 #if defined(SH_ETH_TYPE_GETHER)
402 sh_eth_write(port_info, 0, PIPR);
403 #endif
404 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
405 sh_eth_write(port_info, APR_AP, APR);
406 sh_eth_write(port_info, MPR_MP, MPR);
407 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
408 #endif
409
410 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
411 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
412 #elif defined(CONFIG_RCAR_GEN2)
413 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
414 #endif
415 }
416
417 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
418 {
419 struct sh_eth_info *port_info = &eth->port_info[eth->port];
420 struct phy_device *phy = port_info->phydev;
421 int ret = 0;
422 u32 val = 0;
423
424 /* Set the transfer speed */
425 if (phy->speed == 100) {
426 printf(SHETHER_NAME ": 100Base/");
427 #if defined(SH_ETH_TYPE_GETHER)
428 sh_eth_write(port_info, GECMR_100B, GECMR);
429 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
430 sh_eth_write(port_info, 1, RTRATE);
431 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
432 val = ECMR_RTM;
433 #endif
434 } else if (phy->speed == 10) {
435 printf(SHETHER_NAME ": 10Base/");
436 #if defined(SH_ETH_TYPE_GETHER)
437 sh_eth_write(port_info, GECMR_10B, GECMR);
438 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
439 sh_eth_write(port_info, 0, RTRATE);
440 #endif
441 }
442 #if defined(SH_ETH_TYPE_GETHER)
443 else if (phy->speed == 1000) {
444 printf(SHETHER_NAME ": 1000Base/");
445 sh_eth_write(port_info, GECMR_1000B, GECMR);
446 }
447 #endif
448
449 /* Check if full duplex mode is supported by the phy */
450 if (phy->duplex) {
451 printf("Full\n");
452 sh_eth_write(port_info,
453 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
454 ECMR);
455 } else {
456 printf("Half\n");
457 sh_eth_write(port_info,
458 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
459 ECMR);
460 }
461
462 return ret;
463 }
464
465 static void sh_eth_start(struct sh_eth_dev *eth)
466 {
467 struct sh_eth_info *port_info = &eth->port_info[eth->port];
468
469 /*
470 * Enable the e-dmac receiver only. The transmitter will be enabled when
471 * we have something to transmit
472 */
473 sh_eth_write(port_info, EDRRR_R, EDRRR);
474 }
475
476 static void sh_eth_stop(struct sh_eth_dev *eth)
477 {
478 struct sh_eth_info *port_info = &eth->port_info[eth->port];
479
480 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
481 }
482
483 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
484 {
485 int ret = 0;
486
487 ret = sh_eth_reset(eth);
488 if (ret)
489 return ret;
490
491 ret = sh_eth_desc_init(eth);
492 if (ret)
493 return ret;
494
495 sh_eth_mac_regs_config(eth, mac);
496
497 return 0;
498 }
499
500 static int sh_eth_start_common(struct sh_eth_dev *eth)
501 {
502 struct sh_eth_info *port_info = &eth->port_info[eth->port];
503 int ret;
504
505 ret = phy_startup(port_info->phydev);
506 if (ret) {
507 printf(SHETHER_NAME ": phy startup failure\n");
508 return ret;
509 }
510
511 ret = sh_eth_phy_regs_config(eth);
512 if (ret)
513 return ret;
514
515 sh_eth_start(eth);
516
517 return 0;
518 }
519
520 #ifndef CONFIG_DM_ETH
521 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
522 {
523 int ret = 0;
524 struct sh_eth_info *port_info = &eth->port_info[eth->port];
525 struct eth_device *dev = port_info->dev;
526 struct phy_device *phydev;
527
528 phydev = phy_connect(
529 miiphy_get_dev_by_name(dev->name),
530 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
531 port_info->phydev = phydev;
532 phy_config(phydev);
533
534 return ret;
535 }
536
537 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
538 {
539 struct sh_eth_dev *eth = dev->priv;
540
541 return sh_eth_send_common(eth, packet, len);
542 }
543
544 static int sh_eth_recv_common(struct sh_eth_dev *eth)
545 {
546 int len = 0;
547 struct sh_eth_info *port_info = &eth->port_info[eth->port];
548 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
549
550 len = sh_eth_recv_start(eth);
551 if (len > 0) {
552 invalidate_cache(packet, len);
553 net_process_received_packet(packet, len);
554 sh_eth_recv_finish(eth);
555 } else
556 len = 0;
557
558 /* Restart the receiver if disabled */
559 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
560 sh_eth_write(port_info, EDRRR_R, EDRRR);
561
562 return len;
563 }
564
565 static int sh_eth_recv_legacy(struct eth_device *dev)
566 {
567 struct sh_eth_dev *eth = dev->priv;
568
569 return sh_eth_recv_common(eth);
570 }
571
572 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
573 {
574 struct sh_eth_dev *eth = dev->priv;
575 int ret;
576
577 ret = sh_eth_init_common(eth, dev->enetaddr);
578 if (ret)
579 return ret;
580
581 ret = sh_eth_phy_config_legacy(eth);
582 if (ret) {
583 printf(SHETHER_NAME ": phy config timeout\n");
584 goto err_start;
585 }
586
587 ret = sh_eth_start_common(eth);
588 if (ret)
589 goto err_start;
590
591 return 0;
592
593 err_start:
594 sh_eth_tx_desc_free(eth);
595 sh_eth_rx_desc_free(eth);
596 return ret;
597 }
598
599 void sh_eth_halt_legacy(struct eth_device *dev)
600 {
601 struct sh_eth_dev *eth = dev->priv;
602
603 sh_eth_stop(eth);
604 }
605
606 int sh_eth_initialize(bd_t *bd)
607 {
608 int ret = 0;
609 struct sh_eth_dev *eth = NULL;
610 struct eth_device *dev = NULL;
611 struct mii_dev *mdiodev;
612
613 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
614 if (!eth) {
615 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
616 ret = -ENOMEM;
617 goto err;
618 }
619
620 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
621 if (!dev) {
622 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
623 ret = -ENOMEM;
624 goto err;
625 }
626 memset(dev, 0, sizeof(struct eth_device));
627 memset(eth, 0, sizeof(struct sh_eth_dev));
628
629 eth->port = CONFIG_SH_ETHER_USE_PORT;
630 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
631 eth->port_info[eth->port].iobase =
632 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
633
634 dev->priv = (void *)eth;
635 dev->iobase = 0;
636 dev->init = sh_eth_init_legacy;
637 dev->halt = sh_eth_halt_legacy;
638 dev->send = sh_eth_send_legacy;
639 dev->recv = sh_eth_recv_legacy;
640 eth->port_info[eth->port].dev = dev;
641
642 strcpy(dev->name, SHETHER_NAME);
643
644 /* Register Device to EtherNet subsystem */
645 eth_register(dev);
646
647 bb_miiphy_buses[0].priv = eth;
648 mdiodev = mdio_alloc();
649 if (!mdiodev)
650 return -ENOMEM;
651 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
652 mdiodev->read = bb_miiphy_read;
653 mdiodev->write = bb_miiphy_write;
654
655 ret = mdio_register(mdiodev);
656 if (ret < 0)
657 return ret;
658
659 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
660 puts("Please set MAC address\n");
661
662 return ret;
663
664 err:
665 if (dev)
666 free(dev);
667
668 if (eth)
669 free(eth);
670
671 printf(SHETHER_NAME ": Failed\n");
672 return ret;
673 }
674
675 #else /* CONFIG_DM_ETH */
676
677 struct sh_ether_priv {
678 struct sh_eth_dev shdev;
679
680 struct mii_dev *bus;
681 void __iomem *iobase;
682 struct clk clk;
683 struct gpio_desc reset_gpio;
684 };
685
686 static int sh_ether_send(struct udevice *dev, void *packet, int len)
687 {
688 struct sh_ether_priv *priv = dev_get_priv(dev);
689 struct sh_eth_dev *eth = &priv->shdev;
690
691 return sh_eth_send_common(eth, packet, len);
692 }
693
694 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
695 {
696 struct sh_ether_priv *priv = dev_get_priv(dev);
697 struct sh_eth_dev *eth = &priv->shdev;
698 struct sh_eth_info *port_info = &eth->port_info[eth->port];
699 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
700 int len;
701
702 len = sh_eth_recv_start(eth);
703 if (len > 0) {
704 invalidate_cache(packet, len);
705 *packetp = packet;
706
707 return len;
708 } else {
709 len = 0;
710
711 /* Restart the receiver if disabled */
712 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
713 sh_eth_write(port_info, EDRRR_R, EDRRR);
714
715 return -EAGAIN;
716 }
717 }
718
719 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
720 {
721 struct sh_ether_priv *priv = dev_get_priv(dev);
722 struct sh_eth_dev *eth = &priv->shdev;
723 struct sh_eth_info *port_info = &eth->port_info[eth->port];
724
725 sh_eth_recv_finish(eth);
726
727 /* Restart the receiver if disabled */
728 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
729 sh_eth_write(port_info, EDRRR_R, EDRRR);
730
731 return 0;
732 }
733
734 static int sh_ether_write_hwaddr(struct udevice *dev)
735 {
736 struct sh_ether_priv *priv = dev_get_priv(dev);
737 struct sh_eth_dev *eth = &priv->shdev;
738 struct sh_eth_info *port_info = &eth->port_info[eth->port];
739 struct eth_pdata *pdata = dev_get_platdata(dev);
740
741 sh_eth_write_hwaddr(port_info, pdata->enetaddr);
742
743 return 0;
744 }
745
746 static int sh_eth_phy_config(struct udevice *dev)
747 {
748 struct sh_ether_priv *priv = dev_get_priv(dev);
749 struct eth_pdata *pdata = dev_get_platdata(dev);
750 struct sh_eth_dev *eth = &priv->shdev;
751 int ret = 0;
752 struct sh_eth_info *port_info = &eth->port_info[eth->port];
753 struct phy_device *phydev;
754 int mask = 0xffffffff;
755
756 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
757 if (!phydev)
758 return -ENODEV;
759
760 phy_connect_dev(phydev, dev);
761
762 port_info->phydev = phydev;
763 phy_config(phydev);
764
765 return ret;
766 }
767
768 static int sh_ether_start(struct udevice *dev)
769 {
770 struct sh_ether_priv *priv = dev_get_priv(dev);
771 struct eth_pdata *pdata = dev_get_platdata(dev);
772 struct sh_eth_dev *eth = &priv->shdev;
773 int ret;
774
775 ret = clk_enable(&priv->clk);
776 if (ret)
777 return ret;
778
779 ret = sh_eth_init_common(eth, pdata->enetaddr);
780 if (ret)
781 goto err_clk;
782
783 ret = sh_eth_phy_config(dev);
784 if (ret) {
785 printf(SHETHER_NAME ": phy config timeout\n");
786 goto err_start;
787 }
788
789 ret = sh_eth_start_common(eth);
790 if (ret)
791 goto err_start;
792
793 return 0;
794
795 err_start:
796 sh_eth_tx_desc_free(eth);
797 sh_eth_rx_desc_free(eth);
798 err_clk:
799 clk_disable(&priv->clk);
800 return ret;
801 }
802
803 static void sh_ether_stop(struct udevice *dev)
804 {
805 struct sh_ether_priv *priv = dev_get_priv(dev);
806
807 sh_eth_stop(&priv->shdev);
808 clk_disable(&priv->clk);
809 }
810
811 static int sh_ether_probe(struct udevice *udev)
812 {
813 struct eth_pdata *pdata = dev_get_platdata(udev);
814 struct sh_ether_priv *priv = dev_get_priv(udev);
815 struct sh_eth_dev *eth = &priv->shdev;
816 struct mii_dev *mdiodev;
817 void __iomem *iobase;
818 int ret;
819
820 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
821 priv->iobase = iobase;
822
823 ret = clk_get_by_index(udev, 0, &priv->clk);
824 if (ret < 0)
825 goto err_mdio_alloc;
826
827 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
828 GPIOD_IS_OUT);
829
830 mdiodev = mdio_alloc();
831 if (!mdiodev) {
832 ret = -ENOMEM;
833 goto err_mdio_alloc;
834 }
835
836 mdiodev->read = bb_miiphy_read;
837 mdiodev->write = bb_miiphy_write;
838 bb_miiphy_buses[0].priv = eth;
839 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
840
841 ret = mdio_register(mdiodev);
842 if (ret < 0)
843 goto err_mdio_register;
844
845 priv->bus = miiphy_get_dev_by_name(udev->name);
846
847 eth->port = CONFIG_SH_ETHER_USE_PORT;
848 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
849 eth->port_info[eth->port].iobase =
850 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
851
852 return 0;
853
854 err_mdio_register:
855 mdio_free(mdiodev);
856 err_mdio_alloc:
857 unmap_physmem(priv->iobase, MAP_NOCACHE);
858 return ret;
859 }
860
861 static int sh_ether_remove(struct udevice *udev)
862 {
863 struct sh_ether_priv *priv = dev_get_priv(udev);
864 struct sh_eth_dev *eth = &priv->shdev;
865 struct sh_eth_info *port_info = &eth->port_info[eth->port];
866
867 free(port_info->phydev);
868 mdio_unregister(priv->bus);
869 mdio_free(priv->bus);
870
871 if (dm_gpio_is_valid(&priv->reset_gpio))
872 dm_gpio_free(udev, &priv->reset_gpio);
873
874 unmap_physmem(priv->iobase, MAP_NOCACHE);
875
876 return 0;
877 }
878
879 static const struct eth_ops sh_ether_ops = {
880 .start = sh_ether_start,
881 .send = sh_ether_send,
882 .recv = sh_ether_recv,
883 .free_pkt = sh_ether_free_pkt,
884 .stop = sh_ether_stop,
885 .write_hwaddr = sh_ether_write_hwaddr,
886 };
887
888 int sh_ether_ofdata_to_platdata(struct udevice *dev)
889 {
890 struct eth_pdata *pdata = dev_get_platdata(dev);
891 const char *phy_mode;
892 const fdt32_t *cell;
893 int ret = 0;
894
895 pdata->iobase = devfdt_get_addr(dev);
896 pdata->phy_interface = -1;
897 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
898 NULL);
899 if (phy_mode)
900 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
901 if (pdata->phy_interface == -1) {
902 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
903 return -EINVAL;
904 }
905
906 pdata->max_speed = 1000;
907 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
908 if (cell)
909 pdata->max_speed = fdt32_to_cpu(*cell);
910
911 sprintf(bb_miiphy_buses[0].name, dev->name);
912
913 return ret;
914 }
915
916 static const struct udevice_id sh_ether_ids[] = {
917 { .compatible = "renesas,ether-r8a7791" },
918 { }
919 };
920
921 U_BOOT_DRIVER(eth_sh_ether) = {
922 .name = "sh_ether",
923 .id = UCLASS_ETH,
924 .of_match = sh_ether_ids,
925 .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
926 .probe = sh_ether_probe,
927 .remove = sh_ether_remove,
928 .ops = &sh_ether_ops,
929 .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
930 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
931 .flags = DM_FLAG_ALLOC_PRIV_DMA,
932 };
933 #endif
934
935 /******* for bb_miiphy *******/
936 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
937 {
938 return 0;
939 }
940
941 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
942 {
943 struct sh_eth_dev *eth = bus->priv;
944 struct sh_eth_info *port_info = &eth->port_info[eth->port];
945
946 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
947
948 return 0;
949 }
950
951 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
952 {
953 struct sh_eth_dev *eth = bus->priv;
954 struct sh_eth_info *port_info = &eth->port_info[eth->port];
955
956 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
957
958 return 0;
959 }
960
961 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
962 {
963 struct sh_eth_dev *eth = bus->priv;
964 struct sh_eth_info *port_info = &eth->port_info[eth->port];
965
966 if (v)
967 sh_eth_write(port_info,
968 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
969 else
970 sh_eth_write(port_info,
971 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
972
973 return 0;
974 }
975
976 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
977 {
978 struct sh_eth_dev *eth = bus->priv;
979 struct sh_eth_info *port_info = &eth->port_info[eth->port];
980
981 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
982
983 return 0;
984 }
985
986 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
987 {
988 struct sh_eth_dev *eth = bus->priv;
989 struct sh_eth_info *port_info = &eth->port_info[eth->port];
990
991 if (v)
992 sh_eth_write(port_info,
993 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
994 else
995 sh_eth_write(port_info,
996 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
997
998 return 0;
999 }
1000
1001 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1002 {
1003 udelay(10);
1004
1005 return 0;
1006 }
1007
1008 struct bb_miiphy_bus bb_miiphy_buses[] = {
1009 {
1010 .name = "sh_eth",
1011 .init = sh_eth_bb_init,
1012 .mdio_active = sh_eth_bb_mdio_active,
1013 .mdio_tristate = sh_eth_bb_mdio_tristate,
1014 .set_mdio = sh_eth_bb_set_mdio,
1015 .get_mdio = sh_eth_bb_get_mdio,
1016 .set_mdc = sh_eth_bb_set_mdc,
1017 .delay = sh_eth_bb_delay,
1018 }
1019 };
1020
1021 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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