2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
24 #include <linux/mii.h>
30 #ifndef CONFIG_SH_ETHER_USE_PORT
31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
38 #define flush_cache_wback(addr, len) \
39 flush_dcache_range((u32)addr, \
40 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
42 #define flush_cache_wback(...)
45 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
46 #define invalidate_cache(addr, len) \
48 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
53 start &= ~(line_size - 1); \
54 end = ((end + line_size - 1) & ~(line_size - 1)); \
56 invalidate_dcache_range(start, end); \
59 #define invalidate_cache(...)
62 #define TIMEOUT_CNT 1000
64 static int sh_eth_send_common(struct sh_eth_dev
*eth
, void *packet
, int len
)
67 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
69 if (!packet
|| len
> 0xffff) {
70 printf(SHETHER_NAME
": %s: Invalid argument\n", __func__
);
75 /* packet must be a 4 byte boundary */
76 if ((int)packet
& 3) {
77 printf(SHETHER_NAME
": %s: packet not 4 byte aligned\n"
83 /* Update tx descriptor */
84 flush_cache_wback(packet
, len
);
85 port_info
->tx_desc_cur
->td2
= ADDR_TO_PHY(packet
);
86 port_info
->tx_desc_cur
->td1
= len
<< 16;
87 /* Must preserve the end of descriptor list indication */
88 if (port_info
->tx_desc_cur
->td0
& TD_TDLE
)
89 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
| TD_TDLE
;
91 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
;
93 flush_cache_wback(port_info
->tx_desc_cur
, sizeof(struct tx_desc_s
));
95 /* Restart the transmitter if disabled */
96 if (!(sh_eth_read(port_info
, EDTRR
) & EDTRR_TRNS
))
97 sh_eth_write(port_info
, EDTRR_TRNS
, EDTRR
);
99 /* Wait until packet is transmitted */
100 timeout
= TIMEOUT_CNT
;
102 invalidate_cache(port_info
->tx_desc_cur
,
103 sizeof(struct tx_desc_s
));
105 } while (port_info
->tx_desc_cur
->td0
& TD_TACT
&& timeout
--);
108 printf(SHETHER_NAME
": transmit timeout\n");
113 port_info
->tx_desc_cur
++;
114 if (port_info
->tx_desc_cur
>= port_info
->tx_desc_base
+ NUM_TX_DESC
)
115 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
121 static int sh_eth_recv_start(struct sh_eth_dev
*eth
)
123 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
125 /* Check if the rx descriptor is ready */
126 invalidate_cache(port_info
->rx_desc_cur
, sizeof(struct rx_desc_s
));
127 if (port_info
->rx_desc_cur
->rd0
& RD_RACT
)
130 /* Check for errors */
131 if (port_info
->rx_desc_cur
->rd0
& RD_RFE
)
134 return port_info
->rx_desc_cur
->rd1
& 0xffff;
137 static void sh_eth_recv_finish(struct sh_eth_dev
*eth
)
139 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
141 /* Make current descriptor available again */
142 if (port_info
->rx_desc_cur
->rd0
& RD_RDLE
)
143 port_info
->rx_desc_cur
->rd0
= RD_RACT
| RD_RDLE
;
145 port_info
->rx_desc_cur
->rd0
= RD_RACT
;
147 flush_cache_wback(port_info
->rx_desc_cur
,
148 sizeof(struct rx_desc_s
));
150 /* Point to the next descriptor */
151 port_info
->rx_desc_cur
++;
152 if (port_info
->rx_desc_cur
>=
153 port_info
->rx_desc_base
+ NUM_RX_DESC
)
154 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
157 static int sh_eth_reset(struct sh_eth_dev
*eth
)
159 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
160 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
163 /* Start e-dmac transmitter and receiver */
164 sh_eth_write(port_info
, EDSR_ENALL
, EDSR
);
166 /* Perform a software reset and wait for it to complete */
167 sh_eth_write(port_info
, EDMR_SRST
, EDMR
);
168 for (i
= 0; i
< TIMEOUT_CNT
; i
++) {
169 if (!(sh_eth_read(port_info
, EDMR
) & EDMR_SRST
))
174 if (i
== TIMEOUT_CNT
) {
175 printf(SHETHER_NAME
": Software reset timeout\n");
181 sh_eth_write(port_info
, sh_eth_read(port_info
, EDMR
) | EDMR_SRST
, EDMR
);
183 sh_eth_write(port_info
,
184 sh_eth_read(port_info
, EDMR
) & ~EDMR_SRST
, EDMR
);
190 static int sh_eth_tx_desc_init(struct sh_eth_dev
*eth
)
193 u32 alloc_desc_size
= NUM_TX_DESC
* sizeof(struct tx_desc_s
);
194 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
195 struct tx_desc_s
*cur_tx_desc
;
198 * Allocate rx descriptors. They must be aligned to size of struct
201 port_info
->tx_desc_alloc
=
202 memalign(sizeof(struct tx_desc_s
), alloc_desc_size
);
203 if (!port_info
->tx_desc_alloc
) {
204 printf(SHETHER_NAME
": memalign failed\n");
209 flush_cache_wback(port_info
->tx_desc_alloc
, alloc_desc_size
);
211 /* Make sure we use a P2 address (non-cacheable) */
212 port_info
->tx_desc_base
=
213 (struct tx_desc_s
*)ADDR_TO_P2((u32
)port_info
->tx_desc_alloc
);
214 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
216 /* Initialize all descriptors */
217 for (cur_tx_desc
= port_info
->tx_desc_base
, i
= 0; i
< NUM_TX_DESC
;
218 cur_tx_desc
++, i
++) {
219 cur_tx_desc
->td0
= 0x00;
220 cur_tx_desc
->td1
= 0x00;
221 cur_tx_desc
->td2
= 0x00;
224 /* Mark the end of the descriptors */
226 cur_tx_desc
->td0
|= TD_TDLE
;
229 * Point the controller to the tx descriptor list. Must use physical
232 sh_eth_write(port_info
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDLAR
);
233 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
234 sh_eth_write(port_info
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDFAR
);
235 sh_eth_write(port_info
, ADDR_TO_PHY(cur_tx_desc
), TDFXR
);
236 sh_eth_write(port_info
, 0x01, TDFFR
);/* Last discriptor bit */
243 static int sh_eth_rx_desc_init(struct sh_eth_dev
*eth
)
246 u32 alloc_desc_size
= NUM_RX_DESC
* sizeof(struct rx_desc_s
);
247 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
248 struct rx_desc_s
*cur_rx_desc
;
252 * Allocate rx descriptors. They must be aligned to size of struct
255 port_info
->rx_desc_alloc
=
256 memalign(sizeof(struct rx_desc_s
), alloc_desc_size
);
257 if (!port_info
->rx_desc_alloc
) {
258 printf(SHETHER_NAME
": memalign failed\n");
263 flush_cache_wback(port_info
->rx_desc_alloc
, alloc_desc_size
);
265 /* Make sure we use a P2 address (non-cacheable) */
266 port_info
->rx_desc_base
=
267 (struct rx_desc_s
*)ADDR_TO_P2((u32
)port_info
->rx_desc_alloc
);
269 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
272 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
273 * aligned and in P2 area.
275 port_info
->rx_buf_alloc
=
276 memalign(RX_BUF_ALIGNE_SIZE
, NUM_RX_DESC
* MAX_BUF_SIZE
);
277 if (!port_info
->rx_buf_alloc
) {
278 printf(SHETHER_NAME
": alloc failed\n");
283 port_info
->rx_buf_base
= (u8
*)ADDR_TO_P2((u32
)port_info
->rx_buf_alloc
);
285 /* Initialize all descriptors */
286 for (cur_rx_desc
= port_info
->rx_desc_base
,
287 rx_buf
= port_info
->rx_buf_base
, i
= 0;
288 i
< NUM_RX_DESC
; cur_rx_desc
++, rx_buf
+= MAX_BUF_SIZE
, i
++) {
289 cur_rx_desc
->rd0
= RD_RACT
;
290 cur_rx_desc
->rd1
= MAX_BUF_SIZE
<< 16;
291 cur_rx_desc
->rd2
= (u32
)ADDR_TO_PHY(rx_buf
);
294 /* Mark the end of the descriptors */
296 cur_rx_desc
->rd0
|= RD_RDLE
;
298 /* Point the controller to the rx descriptor list */
299 sh_eth_write(port_info
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDLAR
);
300 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
301 sh_eth_write(port_info
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDFAR
);
302 sh_eth_write(port_info
, ADDR_TO_PHY(cur_rx_desc
), RDFXR
);
303 sh_eth_write(port_info
, RDFFR_RDLF
, RDFFR
);
309 free(port_info
->rx_desc_alloc
);
310 port_info
->rx_desc_alloc
= NULL
;
316 static void sh_eth_tx_desc_free(struct sh_eth_dev
*eth
)
318 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
320 if (port_info
->tx_desc_alloc
) {
321 free(port_info
->tx_desc_alloc
);
322 port_info
->tx_desc_alloc
= NULL
;
326 static void sh_eth_rx_desc_free(struct sh_eth_dev
*eth
)
328 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
330 if (port_info
->rx_desc_alloc
) {
331 free(port_info
->rx_desc_alloc
);
332 port_info
->rx_desc_alloc
= NULL
;
335 if (port_info
->rx_buf_alloc
) {
336 free(port_info
->rx_buf_alloc
);
337 port_info
->rx_buf_alloc
= NULL
;
341 static int sh_eth_desc_init(struct sh_eth_dev
*eth
)
345 ret
= sh_eth_tx_desc_init(eth
);
349 ret
= sh_eth_rx_desc_init(eth
);
355 sh_eth_tx_desc_free(eth
);
361 static void sh_eth_write_hwaddr(struct sh_eth_info
*port_info
,
366 val
= (mac
[0] << 24) | (mac
[1] << 16) | (mac
[2] << 8) | mac
[3];
367 sh_eth_write(port_info
, val
, MAHR
);
369 val
= (mac
[4] << 8) | mac
[5];
370 sh_eth_write(port_info
, val
, MALR
);
373 static void sh_eth_mac_regs_config(struct sh_eth_dev
*eth
, unsigned char *mac
)
375 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
377 /* Configure e-dmac registers */
378 sh_eth_write(port_info
, (sh_eth_read(port_info
, EDMR
) & ~EMDR_DESC_R
) |
379 (EMDR_DESC
| EDMR_EL
), EDMR
);
381 sh_eth_write(port_info
, 0, EESIPR
);
382 sh_eth_write(port_info
, 0, TRSCER
);
383 sh_eth_write(port_info
, 0, TFTR
);
384 sh_eth_write(port_info
, (FIFO_SIZE_T
| FIFO_SIZE_R
), FDR
);
385 sh_eth_write(port_info
, RMCR_RST
, RMCR
);
386 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
387 sh_eth_write(port_info
, 0, RPADIR
);
389 sh_eth_write(port_info
, (FIFO_F_D_RFF
| FIFO_F_D_RFD
), FCFTR
);
391 /* Configure e-mac registers */
392 sh_eth_write(port_info
, 0, ECSIPR
);
394 /* Set Mac address */
395 sh_eth_write_hwaddr(port_info
, mac
);
397 sh_eth_write(port_info
, RFLR_RFL_MIN
, RFLR
);
398 #if defined(SH_ETH_TYPE_GETHER)
399 sh_eth_write(port_info
, 0, PIPR
);
401 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
402 sh_eth_write(port_info
, APR_AP
, APR
);
403 sh_eth_write(port_info
, MPR_MP
, MPR
);
404 sh_eth_write(port_info
, TPAUSER_TPAUSE
, TPAUSER
);
407 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
408 sh_eth_write(port_info
, CONFIG_SH_ETHER_SH7734_MII
, RMII_MII
);
409 #elif defined(CONFIG_RCAR_GEN2)
410 sh_eth_write(port_info
, sh_eth_read(port_info
, RMIIMR
) | 0x1, RMIIMR
);
414 static int sh_eth_phy_regs_config(struct sh_eth_dev
*eth
)
416 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
417 struct phy_device
*phy
= port_info
->phydev
;
421 /* Set the transfer speed */
422 if (phy
->speed
== 100) {
423 printf(SHETHER_NAME
": 100Base/");
424 #if defined(SH_ETH_TYPE_GETHER)
425 sh_eth_write(port_info
, GECMR_100B
, GECMR
);
426 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
427 sh_eth_write(port_info
, 1, RTRATE
);
428 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
431 } else if (phy
->speed
== 10) {
432 printf(SHETHER_NAME
": 10Base/");
433 #if defined(SH_ETH_TYPE_GETHER)
434 sh_eth_write(port_info
, GECMR_10B
, GECMR
);
435 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
436 sh_eth_write(port_info
, 0, RTRATE
);
439 #if defined(SH_ETH_TYPE_GETHER)
440 else if (phy
->speed
== 1000) {
441 printf(SHETHER_NAME
": 1000Base/");
442 sh_eth_write(port_info
, GECMR_1000B
, GECMR
);
446 /* Check if full duplex mode is supported by the phy */
449 sh_eth_write(port_info
,
450 val
| (ECMR_CHG_DM
| ECMR_RE
| ECMR_TE
| ECMR_DM
),
454 sh_eth_write(port_info
,
455 val
| (ECMR_CHG_DM
| ECMR_RE
| ECMR_TE
),
462 static void sh_eth_start(struct sh_eth_dev
*eth
)
464 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
467 * Enable the e-dmac receiver only. The transmitter will be enabled when
468 * we have something to transmit
470 sh_eth_write(port_info
, EDRRR_R
, EDRRR
);
473 static void sh_eth_stop(struct sh_eth_dev
*eth
)
475 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
477 sh_eth_write(port_info
, ~EDRRR_R
, EDRRR
);
480 static int sh_eth_init_common(struct sh_eth_dev
*eth
, unsigned char *mac
)
484 ret
= sh_eth_reset(eth
);
488 ret
= sh_eth_desc_init(eth
);
492 sh_eth_mac_regs_config(eth
, mac
);
497 static int sh_eth_start_common(struct sh_eth_dev
*eth
)
499 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
502 ret
= phy_startup(port_info
->phydev
);
504 printf(SHETHER_NAME
": phy startup failure\n");
508 ret
= sh_eth_phy_regs_config(eth
);
517 #ifndef CONFIG_DM_ETH
518 static int sh_eth_phy_config_legacy(struct sh_eth_dev
*eth
)
521 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
522 struct eth_device
*dev
= port_info
->dev
;
523 struct phy_device
*phydev
;
525 phydev
= phy_connect(
526 miiphy_get_dev_by_name(dev
->name
),
527 port_info
->phy_addr
, dev
, CONFIG_SH_ETHER_PHY_MODE
);
528 port_info
->phydev
= phydev
;
534 static int sh_eth_send_legacy(struct eth_device
*dev
, void *packet
, int len
)
536 struct sh_eth_dev
*eth
= dev
->priv
;
538 return sh_eth_send_common(eth
, packet
, len
);
541 static int sh_eth_recv_common(struct sh_eth_dev
*eth
)
544 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
545 uchar
*packet
= (uchar
*)ADDR_TO_P2(port_info
->rx_desc_cur
->rd2
);
547 len
= sh_eth_recv_start(eth
);
549 invalidate_cache(packet
, len
);
550 net_process_received_packet(packet
, len
);
551 sh_eth_recv_finish(eth
);
555 /* Restart the receiver if disabled */
556 if (!(sh_eth_read(port_info
, EDRRR
) & EDRRR_R
))
557 sh_eth_write(port_info
, EDRRR_R
, EDRRR
);
562 static int sh_eth_recv_legacy(struct eth_device
*dev
)
564 struct sh_eth_dev
*eth
= dev
->priv
;
566 return sh_eth_recv_common(eth
);
569 static int sh_eth_init_legacy(struct eth_device
*dev
, bd_t
*bd
)
571 struct sh_eth_dev
*eth
= dev
->priv
;
574 ret
= sh_eth_init_common(eth
, dev
->enetaddr
);
578 ret
= sh_eth_phy_config_legacy(eth
);
580 printf(SHETHER_NAME
": phy config timeout\n");
584 ret
= sh_eth_start_common(eth
);
591 sh_eth_tx_desc_free(eth
);
592 sh_eth_rx_desc_free(eth
);
596 void sh_eth_halt_legacy(struct eth_device
*dev
)
598 struct sh_eth_dev
*eth
= dev
->priv
;
603 int sh_eth_initialize(bd_t
*bd
)
606 struct sh_eth_dev
*eth
= NULL
;
607 struct eth_device
*dev
= NULL
;
608 struct mii_dev
*mdiodev
;
610 eth
= (struct sh_eth_dev
*)malloc(sizeof(struct sh_eth_dev
));
612 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
617 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
619 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
623 memset(dev
, 0, sizeof(struct eth_device
));
624 memset(eth
, 0, sizeof(struct sh_eth_dev
));
626 eth
->port
= CONFIG_SH_ETHER_USE_PORT
;
627 eth
->port_info
[eth
->port
].phy_addr
= CONFIG_SH_ETHER_PHY_ADDR
;
628 eth
->port_info
[eth
->port
].iobase
=
629 (void __iomem
*)(BASE_IO_ADDR
+ 0x800 * eth
->port
);
631 dev
->priv
= (void *)eth
;
633 dev
->init
= sh_eth_init_legacy
;
634 dev
->halt
= sh_eth_halt_legacy
;
635 dev
->send
= sh_eth_send_legacy
;
636 dev
->recv
= sh_eth_recv_legacy
;
637 eth
->port_info
[eth
->port
].dev
= dev
;
639 strcpy(dev
->name
, SHETHER_NAME
);
641 /* Register Device to EtherNet subsystem */
644 bb_miiphy_buses
[0].priv
= eth
;
645 mdiodev
= mdio_alloc();
648 strncpy(mdiodev
->name
, dev
->name
, MDIO_NAME_LEN
);
649 mdiodev
->read
= bb_miiphy_read
;
650 mdiodev
->write
= bb_miiphy_write
;
652 ret
= mdio_register(mdiodev
);
656 if (!eth_env_get_enetaddr("ethaddr", dev
->enetaddr
))
657 puts("Please set MAC address\n");
668 printf(SHETHER_NAME
": Failed\n");
672 #else /* CONFIG_DM_ETH */
674 struct sh_ether_priv
{
675 struct sh_eth_dev shdev
;
680 struct gpio_desc reset_gpio
;
683 static int sh_ether_send(struct udevice
*dev
, void *packet
, int len
)
685 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
686 struct sh_eth_dev
*eth
= &priv
->shdev
;
688 return sh_eth_send_common(eth
, packet
, len
);
691 static int sh_ether_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
693 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
694 struct sh_eth_dev
*eth
= &priv
->shdev
;
695 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
696 uchar
*packet
= (uchar
*)ADDR_TO_P2(port_info
->rx_desc_cur
->rd2
);
699 len
= sh_eth_recv_start(eth
);
701 invalidate_cache(packet
, len
);
708 /* Restart the receiver if disabled */
709 if (!(sh_eth_read(port_info
, EDRRR
) & EDRRR_R
))
710 sh_eth_write(port_info
, EDRRR_R
, EDRRR
);
716 static int sh_ether_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
718 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
719 struct sh_eth_dev
*eth
= &priv
->shdev
;
720 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
722 sh_eth_recv_finish(eth
);
724 /* Restart the receiver if disabled */
725 if (!(sh_eth_read(port_info
, EDRRR
) & EDRRR_R
))
726 sh_eth_write(port_info
, EDRRR_R
, EDRRR
);
731 static int sh_ether_write_hwaddr(struct udevice
*dev
)
733 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
734 struct sh_eth_dev
*eth
= &priv
->shdev
;
735 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
736 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
738 sh_eth_write_hwaddr(port_info
, pdata
->enetaddr
);
743 static int sh_eth_phy_config(struct udevice
*dev
)
745 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
746 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
747 struct sh_eth_dev
*eth
= &priv
->shdev
;
749 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
750 struct phy_device
*phydev
;
751 int mask
= 0xffffffff;
753 phydev
= phy_find_by_mask(priv
->bus
, mask
, pdata
->phy_interface
);
757 phy_connect_dev(phydev
, dev
);
759 port_info
->phydev
= phydev
;
765 static int sh_ether_start(struct udevice
*dev
)
767 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
768 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
769 struct sh_eth_dev
*eth
= &priv
->shdev
;
772 ret
= clk_enable(&priv
->clk
);
776 ret
= sh_eth_init_common(eth
, pdata
->enetaddr
);
780 ret
= sh_eth_phy_config(dev
);
782 printf(SHETHER_NAME
": phy config timeout\n");
786 ret
= sh_eth_start_common(eth
);
793 sh_eth_tx_desc_free(eth
);
794 sh_eth_rx_desc_free(eth
);
796 clk_disable(&priv
->clk
);
800 static void sh_ether_stop(struct udevice
*dev
)
802 struct sh_ether_priv
*priv
= dev_get_priv(dev
);
804 sh_eth_stop(&priv
->shdev
);
805 clk_disable(&priv
->clk
);
808 static int sh_ether_probe(struct udevice
*udev
)
810 struct eth_pdata
*pdata
= dev_get_platdata(udev
);
811 struct sh_ether_priv
*priv
= dev_get_priv(udev
);
812 struct sh_eth_dev
*eth
= &priv
->shdev
;
813 struct mii_dev
*mdiodev
;
816 priv
->iobase
= pdata
->iobase
;
818 ret
= clk_get_by_index(udev
, 0, &priv
->clk
);
822 gpio_request_by_name(udev
, "reset-gpios", 0, &priv
->reset_gpio
,
825 mdiodev
= mdio_alloc();
831 mdiodev
->read
= bb_miiphy_read
;
832 mdiodev
->write
= bb_miiphy_write
;
833 bb_miiphy_buses
[0].priv
= eth
;
834 snprintf(mdiodev
->name
, sizeof(mdiodev
->name
), udev
->name
);
836 ret
= mdio_register(mdiodev
);
838 goto err_mdio_register
;
840 priv
->bus
= miiphy_get_dev_by_name(udev
->name
);
842 eth
->port
= CONFIG_SH_ETHER_USE_PORT
;
843 eth
->port_info
[eth
->port
].phy_addr
= CONFIG_SH_ETHER_PHY_ADDR
;
844 eth
->port_info
[eth
->port
].iobase
=
845 (void __iomem
*)(BASE_IO_ADDR
+ 0x800 * eth
->port
);
854 static int sh_ether_remove(struct udevice
*udev
)
856 struct sh_ether_priv
*priv
= dev_get_priv(udev
);
857 struct sh_eth_dev
*eth
= &priv
->shdev
;
858 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
860 free(port_info
->phydev
);
861 mdio_unregister(priv
->bus
);
862 mdio_free(priv
->bus
);
864 if (dm_gpio_is_valid(&priv
->reset_gpio
))
865 dm_gpio_free(udev
, &priv
->reset_gpio
);
870 static const struct eth_ops sh_ether_ops
= {
871 .start
= sh_ether_start
,
872 .send
= sh_ether_send
,
873 .recv
= sh_ether_recv
,
874 .free_pkt
= sh_ether_free_pkt
,
875 .stop
= sh_ether_stop
,
876 .write_hwaddr
= sh_ether_write_hwaddr
,
879 int sh_ether_ofdata_to_platdata(struct udevice
*dev
)
881 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
882 const char *phy_mode
;
886 pdata
->iobase
= devfdt_get_addr(dev
);
887 pdata
->phy_interface
= -1;
888 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
891 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
892 if (pdata
->phy_interface
== -1) {
893 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
897 pdata
->max_speed
= 1000;
898 cell
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "max-speed", NULL
);
900 pdata
->max_speed
= fdt32_to_cpu(*cell
);
902 sprintf(bb_miiphy_buses
[0].name
, dev
->name
);
907 static const struct udevice_id sh_ether_ids
[] = {
908 { .compatible
= "renesas,ether-r8a7791" },
912 U_BOOT_DRIVER(eth_sh_ether
) = {
915 .of_match
= sh_ether_ids
,
916 .ofdata_to_platdata
= sh_ether_ofdata_to_platdata
,
917 .probe
= sh_ether_probe
,
918 .remove
= sh_ether_remove
,
919 .ops
= &sh_ether_ops
,
920 .priv_auto_alloc_size
= sizeof(struct sh_ether_priv
),
921 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
922 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,
926 /******* for bb_miiphy *******/
927 static int sh_eth_bb_init(struct bb_miiphy_bus
*bus
)
932 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus
*bus
)
934 struct sh_eth_dev
*eth
= bus
->priv
;
935 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
937 sh_eth_write(port_info
, sh_eth_read(port_info
, PIR
) | PIR_MMD
, PIR
);
942 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus
)
944 struct sh_eth_dev
*eth
= bus
->priv
;
945 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
947 sh_eth_write(port_info
, sh_eth_read(port_info
, PIR
) & ~PIR_MMD
, PIR
);
952 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
954 struct sh_eth_dev
*eth
= bus
->priv
;
955 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
958 sh_eth_write(port_info
,
959 sh_eth_read(port_info
, PIR
) | PIR_MDO
, PIR
);
961 sh_eth_write(port_info
,
962 sh_eth_read(port_info
, PIR
) & ~PIR_MDO
, PIR
);
967 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
969 struct sh_eth_dev
*eth
= bus
->priv
;
970 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
972 *v
= (sh_eth_read(port_info
, PIR
) & PIR_MDI
) >> 3;
977 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
979 struct sh_eth_dev
*eth
= bus
->priv
;
980 struct sh_eth_info
*port_info
= ð
->port_info
[eth
->port
];
983 sh_eth_write(port_info
,
984 sh_eth_read(port_info
, PIR
) | PIR_MDC
, PIR
);
986 sh_eth_write(port_info
,
987 sh_eth_read(port_info
, PIR
) & ~PIR_MDC
, PIR
);
992 static int sh_eth_bb_delay(struct bb_miiphy_bus
*bus
)
999 struct bb_miiphy_bus bb_miiphy_buses
[] = {
1002 .init
= sh_eth_bb_init
,
1003 .mdio_active
= sh_eth_bb_mdio_active
,
1004 .mdio_tristate
= sh_eth_bb_mdio_tristate
,
1005 .set_mdio
= sh_eth_bb_set_mdio
,
1006 .get_mdio
= sh_eth_bb_get_mdio
,
1007 .set_mdc
= sh_eth_bb_set_mdc
,
1008 .delay
= sh_eth_bb_delay
,
1012 int bb_miiphy_buses_num
= ARRAY_SIZE(bb_miiphy_buses
);