drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controler.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  * Copyright (C) 2013  Renesas Electronics Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <asm/errno.h>
  19 #include <asm/io.h>
  20
  21 #include "sh_eth.h"
  22
  23 #ifndef CONFIG_SH_ETHER_USE_PORT
  24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  25 #endif
  26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  28 #endif
  29
  30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  31 #define flush_cache_wback(addr, len)    \
  32                 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
  33 #else
  34 #define flush_cache_wback(...)
  35 #endif
  36
  37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  38 #define invalidate_cache(addr, len)             \
  39         {       \
  40                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  41                 u32 start, end; \
  42                 \
  43                 start = (u32)addr;      \
  44                 end = start + len;      \
  45                 start &= ~(line_size - 1);      \
  46                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  47                 \
  48                 invalidate_dcache_range(start, end);    \
  49         }
  50 #else
  51 #define invalidate_cache(...)
  52 #endif
  53
  54 #define TIMEOUT_CNT 1000
  55
  56 int sh_eth_send(struct eth_device *dev, void *packet, int len)
  57 {
  58         struct sh_eth_dev *eth = dev->priv;
  59         int port = eth->port, ret = 0, timeout;
  60         struct sh_eth_info *port_info = &eth->port_info[port];
  61
  62         if (!packet || len > 0xffff) {
  63                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  64                 ret = -EINVAL;
  65                 goto err;
  66         }
  67
  68         /* packet must be a 4 byte boundary */
  69         if ((int)packet & 3) {
  70                 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
  71                                 , __func__);
  72                 ret = -EFAULT;
  73                 goto err;
  74         }
  75
  76         /* Update tx descriptor */
  77         flush_cache_wback(packet, len);
  78         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  79         port_info->tx_desc_cur->td1 = len << 16;
  80         /* Must preserve the end of descriptor list indication */
  81         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  82                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  83         else
  84                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  85
  86         /* Restart the transmitter if disabled */
  87         if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
  88                 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
  89
  90         /* Wait until packet is transmitted */
  91         timeout = TIMEOUT_CNT;
  92         do {
  93                 invalidate_cache(port_info->tx_desc_cur,
  94                                  sizeof(struct tx_desc_s));
  95                 udelay(100);
  96         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  97
  98         if (timeout < 0) {
  99                 printf(SHETHER_NAME ": transmit timeout\n");
 100                 ret = -ETIMEDOUT;
 101                 goto err;
 102         }
 103
 104         port_info->tx_desc_cur++;
 105         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 106                 port_info->tx_desc_cur = port_info->tx_desc_base;
 107
 108 err:
 109         return ret;
 110 }
 111
 112 int sh_eth_recv(struct eth_device *dev)
 113 {
 114         struct sh_eth_dev *eth = dev->priv;
 115         int port = eth->port, len = 0;
 116         struct sh_eth_info *port_info = &eth->port_info[port];
 117         uchar *packet;
 118
 119         /* Check if the rx descriptor is ready */
 120         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 121         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 122                 /* Check for errors */
 123                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 124                         len = port_info->rx_desc_cur->rd1 & 0xffff;
 125                         packet = (uchar *)
 126                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 127                         invalidate_cache(packet, len);
 128                         NetReceive(packet, len);
 129                 }
 130
 131                 /* Make current descriptor available again */
 132                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 133                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 134                 else
 135                         port_info->rx_desc_cur->rd0 = RD_RACT;
 136                 /* Point to the next descriptor */
 137                 port_info->rx_desc_cur++;
 138                 if (port_info->rx_desc_cur >=
 139                     port_info->rx_desc_base + NUM_RX_DESC)
 140                         port_info->rx_desc_cur = port_info->rx_desc_base;
 141         }
 142
 143         /* Restart the receiver if disabled */
 144         if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
 145                 sh_eth_write(eth, EDRRR_R, EDRRR);
 146
 147         return len;
 148 }
 149
 150 static int sh_eth_reset(struct sh_eth_dev *eth)
 151 {
 152 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 153         int ret = 0, i;
 154
 155         /* Start e-dmac transmitter and receiver */
 156         sh_eth_write(eth, EDSR_ENALL, EDSR);
 157
 158         /* Perform a software reset and wait for it to complete */
 159         sh_eth_write(eth, EDMR_SRST, EDMR);
 160         for (i = 0; i < TIMEOUT_CNT; i++) {
 161                 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
 162                         break;
 163                 udelay(1000);
 164         }
 165
 166         if (i == TIMEOUT_CNT) {
 167                 printf(SHETHER_NAME  ": Software reset timeout\n");
 168                 ret = -EIO;
 169         }
 170
 171         return ret;
 172 #else
 173         sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
 174         udelay(3000);
 175         sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
 176
 177         return 0;
 178 #endif
 179 }
 180
 181 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 182 {
 183         int port = eth->port, i, ret = 0;
 184         u32 tmp_addr;
 185         struct sh_eth_info *port_info = &eth->port_info[port];
 186         struct tx_desc_s *cur_tx_desc;
 187
 188         /*
 189          * Allocate rx descriptors. They must be aligned to size of struct
 190          * tx_desc_s.
 191          */
 192         port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
 193                                                  sizeof(struct tx_desc_s) +
 194                                                  sizeof(struct tx_desc_s) - 1);
 195         if (!port_info->tx_desc_malloc) {
 196                 printf(SHETHER_NAME ": malloc failed\n");
 197                 ret = -ENOMEM;
 198                 goto err;
 199         }
 200
 201         tmp_addr = (u32) (((int)port_info->tx_desc_malloc +
 202                           sizeof(struct tx_desc_s) - 1) &
 203                           ~(sizeof(struct tx_desc_s) - 1));
 204         flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
 205         /* Make sure we use a P2 address (non-cacheable) */
 206         port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
 207         port_info->tx_desc_cur = port_info->tx_desc_base;
 208
 209         /* Initialize all descriptors */
 210         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 211              cur_tx_desc++, i++) {
 212                 cur_tx_desc->td0 = 0x00;
 213                 cur_tx_desc->td1 = 0x00;
 214                 cur_tx_desc->td2 = 0x00;
 215         }
 216
 217         /* Mark the end of the descriptors */
 218         cur_tx_desc--;
 219         cur_tx_desc->td0 |= TD_TDLE;
 220
 221         /* Point the controller to the tx descriptor list. Must use physical
 222            addresses */
 223         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 224 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 225         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 226         sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 227         sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
 228 #endif
 229
 230 err:
 231         return ret;
 232 }
 233
 234 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 235 {
 236         int port = eth->port, i , ret = 0;
 237         struct sh_eth_info *port_info = &eth->port_info[port];
 238         struct rx_desc_s *cur_rx_desc;
 239         u32 tmp_addr;
 240         u8 *rx_buf;
 241
 242         /*
 243          * Allocate rx descriptors. They must be aligned to size of struct
 244          * rx_desc_s.
 245          */
 246         port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
 247                                                  sizeof(struct rx_desc_s) +
 248                                                  sizeof(struct rx_desc_s) - 1);
 249         if (!port_info->rx_desc_malloc) {
 250                 printf(SHETHER_NAME ": malloc failed\n");
 251                 ret = -ENOMEM;
 252                 goto err;
 253         }
 254
 255         tmp_addr = (u32) (((int)port_info->rx_desc_malloc +
 256                           sizeof(struct rx_desc_s) - 1) &
 257                           ~(sizeof(struct rx_desc_s) - 1));
 258         flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
 259         /* Make sure we use a P2 address (non-cacheable) */
 260         port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
 261
 262         port_info->rx_desc_cur = port_info->rx_desc_base;
 263
 264         /*
 265          * Allocate rx data buffers. They must be 32 bytes aligned  and in
 266          * P2 area
 267          */
 268         port_info->rx_buf_malloc = malloc(
 269                 NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
 270         if (!port_info->rx_buf_malloc) {
 271                 printf(SHETHER_NAME ": malloc failed\n");
 272                 ret = -ENOMEM;
 273                 goto err_buf_malloc;
 274         }
 275
 276         tmp_addr = (u32)(((int)port_info->rx_buf_malloc
 277                           + (RX_BUF_ALIGNE_SIZE - 1)) &
 278                           ~(RX_BUF_ALIGNE_SIZE - 1));
 279         port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
 280
 281         /* Initialize all descriptors */
 282         for (cur_rx_desc = port_info->rx_desc_base,
 283              rx_buf = port_info->rx_buf_base, i = 0;
 284              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 285                 cur_rx_desc->rd0 = RD_RACT;
 286                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 287                 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
 288         }
 289
 290         /* Mark the end of the descriptors */
 291         cur_rx_desc--;
 292         cur_rx_desc->rd0 |= RD_RDLE;
 293
 294         /* Point the controller to the rx descriptor list */
 295         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 296 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 297         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 298         sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 299         sh_eth_write(eth, RDFFR_RDLF, RDFFR);
 300 #endif
 301
 302         return ret;
 303
 304 err_buf_malloc:
 305         free(port_info->rx_desc_malloc);
 306         port_info->rx_desc_malloc = NULL;
 307
 308 err:
 309         return ret;
 310 }
 311
 312 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 313 {
 314         int port = eth->port;
 315         struct sh_eth_info *port_info = &eth->port_info[port];
 316
 317         if (port_info->tx_desc_malloc) {
 318                 free(port_info->tx_desc_malloc);
 319                 port_info->tx_desc_malloc = NULL;
 320         }
 321 }
 322
 323 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 324 {
 325         int port = eth->port;
 326         struct sh_eth_info *port_info = &eth->port_info[port];
 327
 328         if (port_info->rx_desc_malloc) {
 329                 free(port_info->rx_desc_malloc);
 330                 port_info->rx_desc_malloc = NULL;
 331         }
 332
 333         if (port_info->rx_buf_malloc) {
 334                 free(port_info->rx_buf_malloc);
 335                 port_info->rx_buf_malloc = NULL;
 336         }
 337 }
 338
 339 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 340 {
 341         int ret = 0;
 342
 343         ret = sh_eth_tx_desc_init(eth);
 344         if (ret)
 345                 goto err_tx_init;
 346
 347         ret = sh_eth_rx_desc_init(eth);
 348         if (ret)
 349                 goto err_rx_init;
 350
 351         return ret;
 352 err_rx_init:
 353         sh_eth_tx_desc_free(eth);
 354
 355 err_tx_init:
 356         return ret;
 357 }
 358
 359 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 360 {
 361         int port = eth->port, ret = 0;
 362         struct sh_eth_info *port_info = &eth->port_info[port];
 363         struct eth_device *dev = port_info->dev;
 364         struct phy_device *phydev;
 365
 366         phydev = phy_connect(
 367                         miiphy_get_dev_by_name(dev->name),
 368                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 369         port_info->phydev = phydev;
 370         phy_config(phydev);
 371
 372         return ret;
 373 }
 374
 375 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 376 {
 377         int port = eth->port, ret = 0;
 378         u32 val;
 379         struct sh_eth_info *port_info = &eth->port_info[port];
 380         struct eth_device *dev = port_info->dev;
 381         struct phy_device *phy;
 382
 383         /* Configure e-dmac registers */
 384         sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
 385                         (EMDR_DESC | EDMR_EL), EDMR);
 386
 387         sh_eth_write(eth, 0, EESIPR);
 388         sh_eth_write(eth, 0, TRSCER);
 389         sh_eth_write(eth, 0, TFTR);
 390         sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 391         sh_eth_write(eth, RMCR_RST, RMCR);
 392 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 393         sh_eth_write(eth, 0, RPADIR);
 394 #endif
 395         sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 396
 397         /* Configure e-mac registers */
 398         sh_eth_write(eth, 0, ECSIPR);
 399
 400         /* Set Mac address */
 401         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 402             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 403         sh_eth_write(eth, val, MAHR);
 404
 405         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 406         sh_eth_write(eth, val, MALR);
 407
 408         sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
 409 #if defined(SH_ETH_TYPE_GETHER)
 410         sh_eth_write(eth, 0, PIPR);
 411 #endif
 412 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 413         sh_eth_write(eth, APR_AP, APR);
 414         sh_eth_write(eth, MPR_MP, MPR);
 415         sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
 416 #endif
 417
 418 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 419         sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 420 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 421         defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 422         sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 423 #endif
 424         /* Configure phy */
 425         ret = sh_eth_phy_config(eth);
 426         if (ret) {
 427                 printf(SHETHER_NAME ": phy config timeout\n");
 428                 goto err_phy_cfg;
 429         }
 430         phy = port_info->phydev;
 431         ret = phy_startup(phy);
 432         if (ret) {
 433                 printf(SHETHER_NAME ": phy startup failure\n");
 434                 return ret;
 435         }
 436
 437         val = 0;
 438
 439         /* Set the transfer speed */
 440         if (phy->speed == 100) {
 441                 printf(SHETHER_NAME ": 100Base/");
 442 #if defined(SH_ETH_TYPE_GETHER)
 443                 sh_eth_write(eth, GECMR_100B, GECMR);
 444 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 445                 sh_eth_write(eth, 1, RTRATE);
 446 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
 447                 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
 448                 defined(CONFIG_R8A7794)
 449                 val = ECMR_RTM;
 450 #endif
 451         } else if (phy->speed == 10) {
 452                 printf(SHETHER_NAME ": 10Base/");
 453 #if defined(SH_ETH_TYPE_GETHER)
 454                 sh_eth_write(eth, GECMR_10B, GECMR);
 455 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 456                 sh_eth_write(eth, 0, RTRATE);
 457 #endif
 458         }
 459 #if defined(SH_ETH_TYPE_GETHER)
 460         else if (phy->speed == 1000) {
 461                 printf(SHETHER_NAME ": 1000Base/");
 462                 sh_eth_write(eth, GECMR_1000B, GECMR);
 463         }
 464 #endif
 465
 466         /* Check if full duplex mode is supported by the phy */
 467         if (phy->duplex) {
 468                 printf("Full\n");
 469                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
 470                              ECMR);
 471         } else {
 472                 printf("Half\n");
 473                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
 474         }
 475
 476         return ret;
 477
 478 err_phy_cfg:
 479         return ret;
 480 }
 481
 482 static void sh_eth_start(struct sh_eth_dev *eth)
 483 {
 484         /*
 485          * Enable the e-dmac receiver only. The transmitter will be enabled when
 486          * we have something to transmit
 487          */
 488         sh_eth_write(eth, EDRRR_R, EDRRR);
 489 }
 490
 491 static void sh_eth_stop(struct sh_eth_dev *eth)
 492 {
 493         sh_eth_write(eth, ~EDRRR_R, EDRRR);
 494 }
 495
 496 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 497 {
 498         int ret = 0;
 499         struct sh_eth_dev *eth = dev->priv;
 500
 501         ret = sh_eth_reset(eth);
 502         if (ret)
 503                 goto err;
 504
 505         ret = sh_eth_desc_init(eth);
 506         if (ret)
 507                 goto err;
 508
 509         ret = sh_eth_config(eth, bd);
 510         if (ret)
 511                 goto err_config;
 512
 513         sh_eth_start(eth);
 514
 515         return ret;
 516
 517 err_config:
 518         sh_eth_tx_desc_free(eth);
 519         sh_eth_rx_desc_free(eth);
 520
 521 err:
 522         return ret;
 523 }
 524
 525 void sh_eth_halt(struct eth_device *dev)
 526 {
 527         struct sh_eth_dev *eth = dev->priv;
 528         sh_eth_stop(eth);
 529 }
 530
 531 int sh_eth_initialize(bd_t *bd)
 532 {
 533         int ret = 0;
 534         struct sh_eth_dev *eth = NULL;
 535         struct eth_device *dev = NULL;
 536
 537         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 538         if (!eth) {
 539                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 540                 ret = -ENOMEM;
 541                 goto err;
 542         }
 543
 544         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 545         if (!dev) {
 546                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 547                 ret = -ENOMEM;
 548                 goto err;
 549         }
 550         memset(dev, 0, sizeof(struct eth_device));
 551         memset(eth, 0, sizeof(struct sh_eth_dev));
 552
 553         eth->port = CONFIG_SH_ETHER_USE_PORT;
 554         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 555
 556         dev->priv = (void *)eth;
 557         dev->iobase = 0;
 558         dev->init = sh_eth_init;
 559         dev->halt = sh_eth_halt;
 560         dev->send = sh_eth_send;
 561         dev->recv = sh_eth_recv;
 562         eth->port_info[eth->port].dev = dev;
 563
 564         sprintf(dev->name, SHETHER_NAME);
 565
 566         /* Register Device to EtherNet subsystem  */
 567         eth_register(dev);
 568
 569         bb_miiphy_buses[0].priv = eth;
 570         miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
 571
 572         if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
 573                 puts("Please set MAC address\n");
 574
 575         return ret;
 576
 577 err:
 578         if (dev)
 579                 free(dev);
 580
 581         if (eth)
 582                 free(eth);
 583
 584         printf(SHETHER_NAME ": Failed\n");
 585         return ret;
 586 }
 587
 588 /******* for bb_miiphy *******/
 589 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 590 {
 591         return 0;
 592 }
 593
 594 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 595 {
 596         struct sh_eth_dev *eth = bus->priv;
 597
 598         sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
 599
 600         return 0;
 601 }
 602
 603 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 604 {
 605         struct sh_eth_dev *eth = bus->priv;
 606
 607         sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
 608
 609         return 0;
 610 }
 611
 612 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 613 {
 614         struct sh_eth_dev *eth = bus->priv;
 615
 616         if (v)
 617                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
 618         else
 619                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
 620
 621         return 0;
 622 }
 623
 624 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 625 {
 626         struct sh_eth_dev *eth = bus->priv;
 627
 628         *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
 629
 630         return 0;
 631 }
 632
 633 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 634 {
 635         struct sh_eth_dev *eth = bus->priv;
 636
 637         if (v)
 638                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
 639         else
 640                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
 641
 642         return 0;
 643 }
 644
 645 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 646 {
 647         udelay(10);
 648
 649         return 0;
 650 }
 651
 652 struct bb_miiphy_bus bb_miiphy_buses[] = {
 653         {
 654                 .name           = "sh_eth",
 655                 .init           = sh_eth_bb_init,
 656                 .mdio_active    = sh_eth_bb_mdio_active,
 657                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 658                 .set_mdio       = sh_eth_bb_set_mdio,
 659                 .get_mdio       = sh_eth_bb_get_mdio,
 660                 .set_mdc        = sh_eth_bb_set_mdc,
 661                 .delay          = sh_eth_bb_delay,
 662         }
 663 };
 664 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);