2 * sh_eth.c - Driver for Renesas ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
22 #ifndef CONFIG_SH_ETHER_USE_PORT
23 # error "Please define CONFIG_SH_ETHER_USE_PORT"
25 #ifndef CONFIG_SH_ETHER_PHY_ADDR
26 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
29 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
30 #define flush_cache_wback(addr, len) \
31 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
33 #define flush_cache_wback(...)
36 #define TIMEOUT_CNT 1000
38 int sh_eth_send(struct eth_device
*dev
, void *packet
, int len
)
40 struct sh_eth_dev
*eth
= dev
->priv
;
41 int port
= eth
->port
, ret
= 0, timeout
;
42 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
44 if (!packet
|| len
> 0xffff) {
45 printf(SHETHER_NAME
": %s: Invalid argument\n", __func__
);
50 /* packet must be a 4 byte boundary */
51 if ((int)packet
& 3) {
52 printf(SHETHER_NAME
": %s: packet not 4 byte alligned\n", __func__
);
57 /* Update tx descriptor */
58 flush_cache_wback(packet
, len
);
59 port_info
->tx_desc_cur
->td2
= ADDR_TO_PHY(packet
);
60 port_info
->tx_desc_cur
->td1
= len
<< 16;
61 /* Must preserve the end of descriptor list indication */
62 if (port_info
->tx_desc_cur
->td0
& TD_TDLE
)
63 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
| TD_TDLE
;
65 port_info
->tx_desc_cur
->td0
= TD_TACT
| TD_TFP
;
67 /* Restart the transmitter if disabled */
68 if (!(sh_eth_read(eth
, EDTRR
) & EDTRR_TRNS
))
69 sh_eth_write(eth
, EDTRR_TRNS
, EDTRR
);
71 /* Wait until packet is transmitted */
72 timeout
= TIMEOUT_CNT
;
73 while (port_info
->tx_desc_cur
->td0
& TD_TACT
&& timeout
--)
77 printf(SHETHER_NAME
": transmit timeout\n");
82 port_info
->tx_desc_cur
++;
83 if (port_info
->tx_desc_cur
>= port_info
->tx_desc_base
+ NUM_TX_DESC
)
84 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
90 int sh_eth_recv(struct eth_device
*dev
)
92 struct sh_eth_dev
*eth
= dev
->priv
;
93 int port
= eth
->port
, len
= 0;
94 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
97 /* Check if the rx descriptor is ready */
98 if (!(port_info
->rx_desc_cur
->rd0
& RD_RACT
)) {
99 /* Check for errors */
100 if (!(port_info
->rx_desc_cur
->rd0
& RD_RFE
)) {
101 len
= port_info
->rx_desc_cur
->rd1
& 0xffff;
103 ADDR_TO_P2(port_info
->rx_desc_cur
->rd2
);
104 NetReceive(packet
, len
);
107 /* Make current descriptor available again */
108 if (port_info
->rx_desc_cur
->rd0
& RD_RDLE
)
109 port_info
->rx_desc_cur
->rd0
= RD_RACT
| RD_RDLE
;
111 port_info
->rx_desc_cur
->rd0
= RD_RACT
;
113 /* Point to the next descriptor */
114 port_info
->rx_desc_cur
++;
115 if (port_info
->rx_desc_cur
>=
116 port_info
->rx_desc_base
+ NUM_RX_DESC
)
117 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
120 /* Restart the receiver if disabled */
121 if (!(sh_eth_read(eth
, EDRRR
) & EDRRR_R
))
122 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
127 static int sh_eth_reset(struct sh_eth_dev
*eth
)
129 #if defined(SH_ETH_TYPE_GETHER)
132 /* Start e-dmac transmitter and receiver */
133 sh_eth_write(eth
, EDSR_ENALL
, EDSR
);
135 /* Perform a software reset and wait for it to complete */
136 sh_eth_write(eth
, EDMR_SRST
, EDMR
);
137 for (i
= 0; i
< TIMEOUT_CNT
; i
++) {
138 if (!(sh_eth_read(eth
, EDMR
) & EDMR_SRST
))
143 if (i
== TIMEOUT_CNT
) {
144 printf(SHETHER_NAME
": Software reset timeout\n");
150 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) | EDMR_SRST
, EDMR
);
152 sh_eth_write(eth
, sh_eth_read(eth
, EDMR
) & ~EDMR_SRST
, EDMR
);
158 static int sh_eth_tx_desc_init(struct sh_eth_dev
*eth
)
160 int port
= eth
->port
, i
, ret
= 0;
162 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
163 struct tx_desc_s
*cur_tx_desc
;
166 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
168 port_info
->tx_desc_malloc
= malloc(NUM_TX_DESC
*
169 sizeof(struct tx_desc_s
) +
171 if (!port_info
->tx_desc_malloc
) {
172 printf(SHETHER_NAME
": malloc failed\n");
177 tmp_addr
= (u32
) (((int)port_info
->tx_desc_malloc
+ TX_DESC_SIZE
- 1) &
178 ~(TX_DESC_SIZE
- 1));
179 flush_cache_wback(tmp_addr
, NUM_TX_DESC
* sizeof(struct tx_desc_s
));
180 /* Make sure we use a P2 address (non-cacheable) */
181 port_info
->tx_desc_base
= (struct tx_desc_s
*)ADDR_TO_P2(tmp_addr
);
182 port_info
->tx_desc_cur
= port_info
->tx_desc_base
;
184 /* Initialize all descriptors */
185 for (cur_tx_desc
= port_info
->tx_desc_base
, i
= 0; i
< NUM_TX_DESC
;
186 cur_tx_desc
++, i
++) {
187 cur_tx_desc
->td0
= 0x00;
188 cur_tx_desc
->td1
= 0x00;
189 cur_tx_desc
->td2
= 0x00;
192 /* Mark the end of the descriptors */
194 cur_tx_desc
->td0
|= TD_TDLE
;
196 /* Point the controller to the tx descriptor list. Must use physical
198 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDLAR
);
199 #if defined(SH_ETH_TYPE_GETHER)
200 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->tx_desc_base
), TDFAR
);
201 sh_eth_write(eth
, ADDR_TO_PHY(cur_tx_desc
), TDFXR
);
202 sh_eth_write(eth
, 0x01, TDFFR
);/* Last discriptor bit */
209 static int sh_eth_rx_desc_init(struct sh_eth_dev
*eth
)
211 int port
= eth
->port
, i
, ret
= 0;
212 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
213 struct rx_desc_s
*cur_rx_desc
;
218 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
220 port_info
->rx_desc_malloc
= malloc(NUM_RX_DESC
*
221 sizeof(struct rx_desc_s
) +
223 if (!port_info
->rx_desc_malloc
) {
224 printf(SHETHER_NAME
": malloc failed\n");
229 tmp_addr
= (u32
) (((int)port_info
->rx_desc_malloc
+ RX_DESC_SIZE
- 1) &
230 ~(RX_DESC_SIZE
- 1));
231 flush_cache_wback(tmp_addr
, NUM_RX_DESC
* sizeof(struct rx_desc_s
));
232 /* Make sure we use a P2 address (non-cacheable) */
233 port_info
->rx_desc_base
= (struct rx_desc_s
*)ADDR_TO_P2(tmp_addr
);
235 port_info
->rx_desc_cur
= port_info
->rx_desc_base
;
238 * Allocate rx data buffers. They must be 32 bytes aligned and in
241 port_info
->rx_buf_malloc
= malloc(NUM_RX_DESC
* MAX_BUF_SIZE
+ 31);
242 if (!port_info
->rx_buf_malloc
) {
243 printf(SHETHER_NAME
": malloc failed\n");
248 tmp_addr
= (u32
)(((int)port_info
->rx_buf_malloc
+ (32 - 1)) &
250 port_info
->rx_buf_base
= (u8
*)ADDR_TO_P2(tmp_addr
);
252 /* Initialize all descriptors */
253 for (cur_rx_desc
= port_info
->rx_desc_base
,
254 rx_buf
= port_info
->rx_buf_base
, i
= 0;
255 i
< NUM_RX_DESC
; cur_rx_desc
++, rx_buf
+= MAX_BUF_SIZE
, i
++) {
256 cur_rx_desc
->rd0
= RD_RACT
;
257 cur_rx_desc
->rd1
= MAX_BUF_SIZE
<< 16;
258 cur_rx_desc
->rd2
= (u32
) ADDR_TO_PHY(rx_buf
);
261 /* Mark the end of the descriptors */
263 cur_rx_desc
->rd0
|= RD_RDLE
;
265 /* Point the controller to the rx descriptor list */
266 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDLAR
);
267 #if defined(SH_ETH_TYPE_GETHER)
268 sh_eth_write(eth
, ADDR_TO_PHY(port_info
->rx_desc_base
), RDFAR
);
269 sh_eth_write(eth
, ADDR_TO_PHY(cur_rx_desc
), RDFXR
);
270 sh_eth_write(eth
, RDFFR_RDLF
, RDFFR
);
276 free(port_info
->rx_desc_malloc
);
277 port_info
->rx_desc_malloc
= NULL
;
283 static void sh_eth_tx_desc_free(struct sh_eth_dev
*eth
)
285 int port
= eth
->port
;
286 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
288 if (port_info
->tx_desc_malloc
) {
289 free(port_info
->tx_desc_malloc
);
290 port_info
->tx_desc_malloc
= NULL
;
294 static void sh_eth_rx_desc_free(struct sh_eth_dev
*eth
)
296 int port
= eth
->port
;
297 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
299 if (port_info
->rx_desc_malloc
) {
300 free(port_info
->rx_desc_malloc
);
301 port_info
->rx_desc_malloc
= NULL
;
304 if (port_info
->rx_buf_malloc
) {
305 free(port_info
->rx_buf_malloc
);
306 port_info
->rx_buf_malloc
= NULL
;
310 static int sh_eth_desc_init(struct sh_eth_dev
*eth
)
314 ret
= sh_eth_tx_desc_init(eth
);
318 ret
= sh_eth_rx_desc_init(eth
);
324 sh_eth_tx_desc_free(eth
);
330 static int sh_eth_phy_config(struct sh_eth_dev
*eth
)
332 int port
= eth
->port
, ret
= 0;
333 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
334 struct eth_device
*dev
= port_info
->dev
;
335 struct phy_device
*phydev
;
337 phydev
= phy_connect(
338 miiphy_get_dev_by_name(dev
->name
),
339 port_info
->phy_addr
, dev
, CONFIG_SH_ETHER_PHY_MODE
);
340 port_info
->phydev
= phydev
;
346 static int sh_eth_config(struct sh_eth_dev
*eth
, bd_t
*bd
)
348 int port
= eth
->port
, ret
= 0;
350 struct sh_eth_info
*port_info
= ð
->port_info
[port
];
351 struct eth_device
*dev
= port_info
->dev
;
352 struct phy_device
*phy
;
354 /* Configure e-dmac registers */
355 sh_eth_write(eth
, (sh_eth_read(eth
, EDMR
) & ~EMDR_DESC_R
) | EDMR_EL
,
357 sh_eth_write(eth
, 0, EESIPR
);
358 sh_eth_write(eth
, 0, TRSCER
);
359 sh_eth_write(eth
, 0, TFTR
);
360 sh_eth_write(eth
, (FIFO_SIZE_T
| FIFO_SIZE_R
), FDR
);
361 sh_eth_write(eth
, RMCR_RST
, RMCR
);
362 #if defined(SH_ETH_TYPE_GETHER)
363 sh_eth_write(eth
, 0, RPADIR
);
365 sh_eth_write(eth
, (FIFO_F_D_RFF
| FIFO_F_D_RFD
), FCFTR
);
367 /* Configure e-mac registers */
368 sh_eth_write(eth
, 0, ECSIPR
);
370 /* Set Mac address */
371 val
= dev
->enetaddr
[0] << 24 | dev
->enetaddr
[1] << 16 |
372 dev
->enetaddr
[2] << 8 | dev
->enetaddr
[3];
373 sh_eth_write(eth
, val
, MAHR
);
375 val
= dev
->enetaddr
[4] << 8 | dev
->enetaddr
[5];
376 sh_eth_write(eth
, val
, MALR
);
378 sh_eth_write(eth
, RFLR_RFL_MIN
, RFLR
);
379 #if defined(SH_ETH_TYPE_GETHER)
380 sh_eth_write(eth
, 0, PIPR
);
381 sh_eth_write(eth
, APR_AP
, APR
);
382 sh_eth_write(eth
, MPR_MP
, MPR
);
383 sh_eth_write(eth
, TPAUSER_TPAUSE
, TPAUSER
);
386 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
387 sh_eth_write(eth
, CONFIG_SH_ETHER_SH7734_MII
, RMII_MII
);
390 ret
= sh_eth_phy_config(eth
);
392 printf(SHETHER_NAME
": phy config timeout\n");
395 phy
= port_info
->phydev
;
396 ret
= phy_startup(phy
);
398 printf(SHETHER_NAME
": phy startup failure\n");
404 /* Set the transfer speed */
405 if (phy
->speed
== 100) {
406 printf(SHETHER_NAME
": 100Base/");
407 #if defined(SH_ETH_TYPE_GETHER)
408 sh_eth_write(eth
, GECMR_100B
, GECMR
);
409 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
410 sh_eth_write(eth
, 1, RTRATE
);
411 #elif defined(CONFIG_CPU_SH7724)
414 } else if (phy
->speed
== 10) {
415 printf(SHETHER_NAME
": 10Base/");
416 #if defined(SH_ETH_TYPE_GETHER)
417 sh_eth_write(eth
, GECMR_10B
, GECMR
);
418 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
419 sh_eth_write(eth
, 0, RTRATE
);
422 #if defined(SH_ETH_TYPE_GETHER)
423 else if (phy
->speed
== 1000) {
424 printf(SHETHER_NAME
": 1000Base/");
425 sh_eth_write(eth
, GECMR_1000B
, GECMR
);
429 /* Check if full duplex mode is supported by the phy */
432 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
|ECMR_DM
),
436 sh_eth_write(eth
, val
| (ECMR_CHG_DM
|ECMR_RE
|ECMR_TE
), ECMR
);
445 static void sh_eth_start(struct sh_eth_dev
*eth
)
448 * Enable the e-dmac receiver only. The transmitter will be enabled when
449 * we have something to transmit
451 sh_eth_write(eth
, EDRRR_R
, EDRRR
);
454 static void sh_eth_stop(struct sh_eth_dev
*eth
)
456 sh_eth_write(eth
, ~EDRRR_R
, EDRRR
);
459 int sh_eth_init(struct eth_device
*dev
, bd_t
*bd
)
462 struct sh_eth_dev
*eth
= dev
->priv
;
464 ret
= sh_eth_reset(eth
);
468 ret
= sh_eth_desc_init(eth
);
472 ret
= sh_eth_config(eth
, bd
);
481 sh_eth_tx_desc_free(eth
);
482 sh_eth_rx_desc_free(eth
);
488 void sh_eth_halt(struct eth_device
*dev
)
490 struct sh_eth_dev
*eth
= dev
->priv
;
494 int sh_eth_initialize(bd_t
*bd
)
497 struct sh_eth_dev
*eth
= NULL
;
498 struct eth_device
*dev
= NULL
;
500 eth
= (struct sh_eth_dev
*)malloc(sizeof(struct sh_eth_dev
));
502 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
507 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
509 printf(SHETHER_NAME
": %s: malloc failed\n", __func__
);
513 memset(dev
, 0, sizeof(struct eth_device
));
514 memset(eth
, 0, sizeof(struct sh_eth_dev
));
516 eth
->port
= CONFIG_SH_ETHER_USE_PORT
;
517 eth
->port_info
[eth
->port
].phy_addr
= CONFIG_SH_ETHER_PHY_ADDR
;
519 dev
->priv
= (void *)eth
;
521 dev
->init
= sh_eth_init
;
522 dev
->halt
= sh_eth_halt
;
523 dev
->send
= sh_eth_send
;
524 dev
->recv
= sh_eth_recv
;
525 eth
->port_info
[eth
->port
].dev
= dev
;
527 sprintf(dev
->name
, SHETHER_NAME
);
529 /* Register Device to EtherNet subsystem */
532 bb_miiphy_buses
[0].priv
= eth
;
533 miiphy_register(dev
->name
, bb_miiphy_read
, bb_miiphy_write
);
535 if (!eth_getenv_enetaddr("ethaddr", dev
->enetaddr
))
536 puts("Please set MAC address\n");
547 printf(SHETHER_NAME
": Failed\n");
551 /******* for bb_miiphy *******/
552 static int sh_eth_bb_init(struct bb_miiphy_bus
*bus
)
557 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus
*bus
)
559 struct sh_eth_dev
*eth
= bus
->priv
;
561 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MMD
, PIR
);
566 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus
)
568 struct sh_eth_dev
*eth
= bus
->priv
;
570 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MMD
, PIR
);
575 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
577 struct sh_eth_dev
*eth
= bus
->priv
;
580 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDO
, PIR
);
582 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDO
, PIR
);
587 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
589 struct sh_eth_dev
*eth
= bus
->priv
;
591 *v
= (sh_eth_read(eth
, PIR
) & PIR_MDI
) >> 3;
596 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
598 struct sh_eth_dev
*eth
= bus
->priv
;
601 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) | PIR_MDC
, PIR
);
603 sh_eth_write(eth
, sh_eth_read(eth
, PIR
) & ~PIR_MDC
, PIR
);
608 static int sh_eth_bb_delay(struct bb_miiphy_bus
*bus
)
615 struct bb_miiphy_bus bb_miiphy_buses
[] = {
618 .init
= sh_eth_bb_init
,
619 .mdio_active
= sh_eth_bb_mdio_active
,
620 .mdio_tristate
= sh_eth_bb_mdio_tristate
,
621 .set_mdio
= sh_eth_bb_set_mdio
,
622 .get_mdio
= sh_eth_bb_get_mdio
,
623 .set_mdc
= sh_eth_bb_set_mdc
,
624 .delay
= sh_eth_bb_delay
,
627 int bb_miiphy_buses_num
= ARRAY_SIZE(bb_miiphy_buses
);