drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controller.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20
  21 #include "sh_eth.h"
  22
  23 #ifndef CONFIG_SH_ETHER_USE_PORT
  24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  25 #endif
  26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  28 #endif
  29
  30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  31 #define flush_cache_wback(addr, len)    \
  32                 flush_dcache_range((u32)addr, \
  33                 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  34 #else
  35 #define flush_cache_wback(...)
  36 #endif
  37
  38 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  39 #define invalidate_cache(addr, len)             \
  40         {       \
  41                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  42                 u32 start, end; \
  43                 \
  44                 start = (u32)addr;      \
  45                 end = start + len;      \
  46                 start &= ~(line_size - 1);      \
  47                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  48                 \
  49                 invalidate_dcache_range(start, end);    \
  50         }
  51 #else
  52 #define invalidate_cache(...)
  53 #endif
  54
  55 #define TIMEOUT_CNT 1000
  56
  57 int sh_eth_send(struct eth_device *dev, void *packet, int len)
  58 {
  59         struct sh_eth_dev *eth = dev->priv;
  60         int port = eth->port, ret = 0, timeout;
  61         struct sh_eth_info *port_info = &eth->port_info[port];
  62
  63         if (!packet || len > 0xffff) {
  64                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  65                 ret = -EINVAL;
  66                 goto err;
  67         }
  68
  69         /* packet must be a 4 byte boundary */
  70         if ((int)packet & 3) {
  71                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  72                                 , __func__);
  73                 ret = -EFAULT;
  74                 goto err;
  75         }
  76
  77         /* Update tx descriptor */
  78         flush_cache_wback(packet, len);
  79         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  80         port_info->tx_desc_cur->td1 = len << 16;
  81         /* Must preserve the end of descriptor list indication */
  82         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  83                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  84         else
  85                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  86
  87         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  88
  89         /* Restart the transmitter if disabled */
  90         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  91                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  92
  93         /* Wait until packet is transmitted */
  94         timeout = TIMEOUT_CNT;
  95         do {
  96                 invalidate_cache(port_info->tx_desc_cur,
  97                                  sizeof(struct tx_desc_s));
  98                 udelay(100);
  99         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 100
 101         if (timeout < 0) {
 102                 printf(SHETHER_NAME ": transmit timeout\n");
 103                 ret = -ETIMEDOUT;
 104                 goto err;
 105         }
 106
 107         port_info->tx_desc_cur++;
 108         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 109                 port_info->tx_desc_cur = port_info->tx_desc_base;
 110
 111 err:
 112         return ret;
 113 }
 114
 115 int sh_eth_recv(struct eth_device *dev)
 116 {
 117         struct sh_eth_dev *eth = dev->priv;
 118         int port = eth->port, len = 0;
 119         struct sh_eth_info *port_info = &eth->port_info[port];
 120         uchar *packet;
 121
 122         /* Check if the rx descriptor is ready */
 123         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 124         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 125                 /* Check for errors */
 126                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 127                         len = port_info->rx_desc_cur->rd1 & 0xffff;
 128                         packet = (uchar *)
 129                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 130                         invalidate_cache(packet, len);
 131                         net_process_received_packet(packet, len);
 132                 }
 133
 134                 /* Make current descriptor available again */
 135                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 136                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 137                 else
 138                         port_info->rx_desc_cur->rd0 = RD_RACT;
 139
 140                 flush_cache_wback(port_info->rx_desc_cur,
 141                                   sizeof(struct rx_desc_s));
 142
 143                 /* Point to the next descriptor */
 144                 port_info->rx_desc_cur++;
 145                 if (port_info->rx_desc_cur >=
 146                     port_info->rx_desc_base + NUM_RX_DESC)
 147                         port_info->rx_desc_cur = port_info->rx_desc_base;
 148         }
 149
 150         /* Restart the receiver if disabled */
 151         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 152                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 153
 154         return len;
 155 }
 156
 157 static int sh_eth_reset(struct sh_eth_dev *eth)
 158 {
 159         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 160 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 161         int ret = 0, i;
 162
 163         /* Start e-dmac transmitter and receiver */
 164         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 165
 166         /* Perform a software reset and wait for it to complete */
 167         sh_eth_write(port_info, EDMR_SRST, EDMR);
 168         for (i = 0; i < TIMEOUT_CNT; i++) {
 169                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 170                         break;
 171                 udelay(1000);
 172         }
 173
 174         if (i == TIMEOUT_CNT) {
 175                 printf(SHETHER_NAME  ": Software reset timeout\n");
 176                 ret = -EIO;
 177         }
 178
 179         return ret;
 180 #else
 181         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 182         udelay(3000);
 183         sh_eth_write(port_info,
 184                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 185
 186         return 0;
 187 #endif
 188 }
 189
 190 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 191 {
 192         int port = eth->port, i, ret = 0;
 193         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 194         struct sh_eth_info *port_info = &eth->port_info[port];
 195         struct tx_desc_s *cur_tx_desc;
 196
 197         /*
 198          * Allocate rx descriptors. They must be aligned to size of struct
 199          * tx_desc_s.
 200          */
 201         port_info->tx_desc_alloc =
 202                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 203         if (!port_info->tx_desc_alloc) {
 204                 printf(SHETHER_NAME ": memalign failed\n");
 205                 ret = -ENOMEM;
 206                 goto err;
 207         }
 208
 209         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 210
 211         /* Make sure we use a P2 address (non-cacheable) */
 212         port_info->tx_desc_base =
 213                 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
 214         port_info->tx_desc_cur = port_info->tx_desc_base;
 215
 216         /* Initialize all descriptors */
 217         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 218              cur_tx_desc++, i++) {
 219                 cur_tx_desc->td0 = 0x00;
 220                 cur_tx_desc->td1 = 0x00;
 221                 cur_tx_desc->td2 = 0x00;
 222         }
 223
 224         /* Mark the end of the descriptors */
 225         cur_tx_desc--;
 226         cur_tx_desc->td0 |= TD_TDLE;
 227
 228         /*
 229          * Point the controller to the tx descriptor list. Must use physical
 230          * addresses
 231          */
 232         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 233 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 234         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 235         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 236         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 237 #endif
 238
 239 err:
 240         return ret;
 241 }
 242
 243 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 244 {
 245         int port = eth->port, i, ret = 0;
 246         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 247         struct sh_eth_info *port_info = &eth->port_info[port];
 248         struct rx_desc_s *cur_rx_desc;
 249         u8 *rx_buf;
 250
 251         /*
 252          * Allocate rx descriptors. They must be aligned to size of struct
 253          * rx_desc_s.
 254          */
 255         port_info->rx_desc_alloc =
 256                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 257         if (!port_info->rx_desc_alloc) {
 258                 printf(SHETHER_NAME ": memalign failed\n");
 259                 ret = -ENOMEM;
 260                 goto err;
 261         }
 262
 263         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 264
 265         /* Make sure we use a P2 address (non-cacheable) */
 266         port_info->rx_desc_base =
 267                 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 268
 269         port_info->rx_desc_cur = port_info->rx_desc_base;
 270
 271         /*
 272          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 273          * aligned and in P2 area.
 274          */
 275         port_info->rx_buf_alloc =
 276                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 277         if (!port_info->rx_buf_alloc) {
 278                 printf(SHETHER_NAME ": alloc failed\n");
 279                 ret = -ENOMEM;
 280                 goto err_buf_alloc;
 281         }
 282
 283         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 284
 285         /* Initialize all descriptors */
 286         for (cur_rx_desc = port_info->rx_desc_base,
 287              rx_buf = port_info->rx_buf_base, i = 0;
 288              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 289                 cur_rx_desc->rd0 = RD_RACT;
 290                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 291                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 292         }
 293
 294         /* Mark the end of the descriptors */
 295         cur_rx_desc--;
 296         cur_rx_desc->rd0 |= RD_RDLE;
 297
 298         /* Point the controller to the rx descriptor list */
 299         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 300 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 301         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 302         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 303         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 304 #endif
 305
 306         return ret;
 307
 308 err_buf_alloc:
 309         free(port_info->rx_desc_alloc);
 310         port_info->rx_desc_alloc = NULL;
 311
 312 err:
 313         return ret;
 314 }
 315
 316 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 317 {
 318         int port = eth->port;
 319         struct sh_eth_info *port_info = &eth->port_info[port];
 320
 321         if (port_info->tx_desc_alloc) {
 322                 free(port_info->tx_desc_alloc);
 323                 port_info->tx_desc_alloc = NULL;
 324         }
 325 }
 326
 327 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 328 {
 329         int port = eth->port;
 330         struct sh_eth_info *port_info = &eth->port_info[port];
 331
 332         if (port_info->rx_desc_alloc) {
 333                 free(port_info->rx_desc_alloc);
 334                 port_info->rx_desc_alloc = NULL;
 335         }
 336
 337         if (port_info->rx_buf_alloc) {
 338                 free(port_info->rx_buf_alloc);
 339                 port_info->rx_buf_alloc = NULL;
 340         }
 341 }
 342
 343 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 344 {
 345         int ret = 0;
 346
 347         ret = sh_eth_tx_desc_init(eth);
 348         if (ret)
 349                 goto err_tx_init;
 350
 351         ret = sh_eth_rx_desc_init(eth);
 352         if (ret)
 353                 goto err_rx_init;
 354
 355         return ret;
 356 err_rx_init:
 357         sh_eth_tx_desc_free(eth);
 358
 359 err_tx_init:
 360         return ret;
 361 }
 362
 363 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 364 {
 365         int port = eth->port, ret = 0;
 366         struct sh_eth_info *port_info = &eth->port_info[port];
 367         struct eth_device *dev = port_info->dev;
 368         struct phy_device *phydev;
 369
 370         phydev = phy_connect(
 371                         miiphy_get_dev_by_name(dev->name),
 372                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 373         port_info->phydev = phydev;
 374         phy_config(phydev);
 375
 376         return ret;
 377 }
 378
 379 static int sh_eth_config(struct sh_eth_dev *eth)
 380 {
 381         int port = eth->port, ret = 0;
 382         u32 val;
 383         struct sh_eth_info *port_info = &eth->port_info[port];
 384         struct eth_device *dev = port_info->dev;
 385         struct phy_device *phy;
 386
 387         /* Configure e-dmac registers */
 388         sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
 389                         (EMDR_DESC | EDMR_EL), EDMR);
 390
 391         sh_eth_write(port_info, 0, EESIPR);
 392         sh_eth_write(port_info, 0, TRSCER);
 393         sh_eth_write(port_info, 0, TFTR);
 394         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 395         sh_eth_write(port_info, RMCR_RST, RMCR);
 396 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 397         sh_eth_write(port_info, 0, RPADIR);
 398 #endif
 399         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 400
 401         /* Configure e-mac registers */
 402         sh_eth_write(port_info, 0, ECSIPR);
 403
 404         /* Set Mac address */
 405         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 406             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 407         sh_eth_write(port_info, val, MAHR);
 408
 409         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 410         sh_eth_write(port_info, val, MALR);
 411
 412         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 413 #if defined(SH_ETH_TYPE_GETHER)
 414         sh_eth_write(port_info, 0, PIPR);
 415 #endif
 416 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 417         sh_eth_write(port_info, APR_AP, APR);
 418         sh_eth_write(port_info, MPR_MP, MPR);
 419         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 420 #endif
 421
 422 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 423         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 424 #elif defined(CONFIG_RCAR_GEN2)
 425         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 426 #endif
 427         /* Configure phy */
 428         ret = sh_eth_phy_config(eth);
 429         if (ret) {
 430                 printf(SHETHER_NAME ": phy config timeout\n");
 431                 goto err_phy_cfg;
 432         }
 433         phy = port_info->phydev;
 434         ret = phy_startup(phy);
 435         if (ret) {
 436                 printf(SHETHER_NAME ": phy startup failure\n");
 437                 return ret;
 438         }
 439
 440         val = 0;
 441
 442         /* Set the transfer speed */
 443         if (phy->speed == 100) {
 444                 printf(SHETHER_NAME ": 100Base/");
 445 #if defined(SH_ETH_TYPE_GETHER)
 446                 sh_eth_write(port_info, GECMR_100B, GECMR);
 447 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 448                 sh_eth_write(port_info, 1, RTRATE);
 449 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
 450                 val = ECMR_RTM;
 451 #endif
 452         } else if (phy->speed == 10) {
 453                 printf(SHETHER_NAME ": 10Base/");
 454 #if defined(SH_ETH_TYPE_GETHER)
 455                 sh_eth_write(port_info, GECMR_10B, GECMR);
 456 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 457                 sh_eth_write(port_info, 0, RTRATE);
 458 #endif
 459         }
 460 #if defined(SH_ETH_TYPE_GETHER)
 461         else if (phy->speed == 1000) {
 462                 printf(SHETHER_NAME ": 1000Base/");
 463                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 464         }
 465 #endif
 466
 467         /* Check if full duplex mode is supported by the phy */
 468         if (phy->duplex) {
 469                 printf("Full\n");
 470                 sh_eth_write(port_info,
 471                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 472                              ECMR);
 473         } else {
 474                 printf("Half\n");
 475                 sh_eth_write(port_info,
 476                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 477                              ECMR);
 478         }
 479
 480         return ret;
 481
 482 err_phy_cfg:
 483         return ret;
 484 }
 485
 486 static void sh_eth_start(struct sh_eth_dev *eth)
 487 {
 488         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 489
 490         /*
 491          * Enable the e-dmac receiver only. The transmitter will be enabled when
 492          * we have something to transmit
 493          */
 494         sh_eth_write(port_info, EDRRR_R, EDRRR);
 495 }
 496
 497 static void sh_eth_stop(struct sh_eth_dev *eth)
 498 {
 499         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 500
 501         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 502 }
 503
 504 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 505 {
 506         int ret = 0;
 507         struct sh_eth_dev *eth = dev->priv;
 508
 509         ret = sh_eth_reset(eth);
 510         if (ret)
 511                 goto err;
 512
 513         ret = sh_eth_desc_init(eth);
 514         if (ret)
 515                 goto err;
 516
 517         ret = sh_eth_config(eth);
 518         if (ret)
 519                 goto err_config;
 520
 521         sh_eth_start(eth);
 522
 523         return ret;
 524
 525 err_config:
 526         sh_eth_tx_desc_free(eth);
 527         sh_eth_rx_desc_free(eth);
 528
 529 err:
 530         return ret;
 531 }
 532
 533 void sh_eth_halt(struct eth_device *dev)
 534 {
 535         struct sh_eth_dev *eth = dev->priv;
 536
 537         sh_eth_stop(eth);
 538 }
 539
 540 int sh_eth_initialize(bd_t *bd)
 541 {
 542         int ret = 0;
 543         struct sh_eth_dev *eth = NULL;
 544         struct eth_device *dev = NULL;
 545         struct mii_dev *mdiodev;
 546
 547         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 548         if (!eth) {
 549                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 550                 ret = -ENOMEM;
 551                 goto err;
 552         }
 553
 554         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 555         if (!dev) {
 556                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 557                 ret = -ENOMEM;
 558                 goto err;
 559         }
 560         memset(dev, 0, sizeof(struct eth_device));
 561         memset(eth, 0, sizeof(struct sh_eth_dev));
 562
 563         eth->port = CONFIG_SH_ETHER_USE_PORT;
 564         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 565         eth->port_info[eth->port].iobase =
 566                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 567
 568         dev->priv = (void *)eth;
 569         dev->iobase = 0;
 570         dev->init = sh_eth_init;
 571         dev->halt = sh_eth_halt;
 572         dev->send = sh_eth_send;
 573         dev->recv = sh_eth_recv;
 574         eth->port_info[eth->port].dev = dev;
 575
 576         strcpy(dev->name, SHETHER_NAME);
 577
 578         /* Register Device to EtherNet subsystem  */
 579         eth_register(dev);
 580
 581         bb_miiphy_buses[0].priv = eth;
 582         mdiodev = mdio_alloc();
 583         if (!mdiodev)
 584                 return -ENOMEM;
 585         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 586         mdiodev->read = bb_miiphy_read;
 587         mdiodev->write = bb_miiphy_write;
 588
 589         ret = mdio_register(mdiodev);
 590         if (ret < 0)
 591                 return ret;
 592
 593         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 594                 puts("Please set MAC address\n");
 595
 596         return ret;
 597
 598 err:
 599         if (dev)
 600                 free(dev);
 601
 602         if (eth)
 603                 free(eth);
 604
 605         printf(SHETHER_NAME ": Failed\n");
 606         return ret;
 607 }
 608
 609 /******* for bb_miiphy *******/
 610 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 611 {
 612         return 0;
 613 }
 614
 615 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 616 {
 617         struct sh_eth_dev *eth = bus->priv;
 618         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 619
 620         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 621
 622         return 0;
 623 }
 624
 625 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 626 {
 627         struct sh_eth_dev *eth = bus->priv;
 628         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 629
 630         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 631
 632         return 0;
 633 }
 634
 635 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 636 {
 637         struct sh_eth_dev *eth = bus->priv;
 638         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 639
 640         if (v)
 641                 sh_eth_write(port_info,
 642                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 643         else
 644                 sh_eth_write(port_info,
 645                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 646
 647         return 0;
 648 }
 649
 650 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 651 {
 652         struct sh_eth_dev *eth = bus->priv;
 653         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 654
 655         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 656
 657         return 0;
 658 }
 659
 660 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 661 {
 662         struct sh_eth_dev *eth = bus->priv;
 663         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 664
 665         if (v)
 666                 sh_eth_write(port_info,
 667                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
 668         else
 669                 sh_eth_write(port_info,
 670                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
 671
 672         return 0;
 673 }
 674
 675 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 676 {
 677         udelay(10);
 678
 679         return 0;
 680 }
 681
 682 struct bb_miiphy_bus bb_miiphy_buses[] = {
 683         {
 684                 .name           = "sh_eth",
 685                 .init           = sh_eth_bb_init,
 686                 .mdio_active    = sh_eth_bb_mdio_active,
 687                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 688                 .set_mdio       = sh_eth_bb_set_mdio,
 689                 .get_mdio       = sh_eth_bb_get_mdio,
 690                 .set_mdc        = sh_eth_bb_set_mdc,
 691                 .delay          = sh_eth_bb_delay,
 692         }
 693 };
 694
 695 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);