drivers/net/sh_eth.h

   1 /*
   2  * sh_eth.h - Driver for Renesas SuperH ethernet controller.
   3  *
   4  * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
   5  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <netdev.h>
  12 #include <asm/types.h>
  13
  14 #define SHETHER_NAME "sh_eth"
  15
  16 #if defined(CONFIG_SH)
  17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
  18    use area P2 (non-cacheable) */
  19 #define ADDR_TO_P2(addr)        ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  20
  21 /* The ethernet controller needs to use physical addresses */
  22 #if defined(CONFIG_SH_32BIT)
  23 #define ADDR_TO_PHY(addr)       ((((int)(addr) & ~0xe0000000) | 0x40000000))
  24 #else
  25 #define ADDR_TO_PHY(addr)       ((int)(addr) & ~0xe0000000)
  26 #endif
  27 #elif defined(CONFIG_ARM)
  28 #ifndef inl
  29 #define inl     readl
  30 #define outl    writel
  31 #endif
  32 #define ADDR_TO_PHY(addr)       ((int)(addr))
  33 #define ADDR_TO_P2(addr)        (addr)
  34 #endif /* defined(CONFIG_SH) */
  35
  36 /* base padding size is 16 */
  37 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
  38 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
  39 #endif
  40
  41 /* Number of supported ports */
  42 #define MAX_PORT_NUM    2
  43
  44 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  45    buffers must be a multiple of 32 bytes */
  46 #define MAX_BUF_SIZE    (48 * 32)
  47
  48 /* The number of tx descriptors must be large enough to point to 5 or more
  49    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  50    We use one descriptor per frame */
  51 #define NUM_TX_DESC             8
  52
  53 /* The size of the tx descriptor is determined by how much padding is used.
  54    4, 20, or 52 bytes of padding can be used */
  55 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  56
  57 /* Tx descriptor. We always use 3 bytes of padding */
  58 struct tx_desc_s {
  59         volatile u32 td0;
  60         u32 td1;
  61         u32 td2;                /* Buffer start */
  62         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  63 };
  64
  65 /* There is no limitation in the number of rx descriptors */
  66 #define NUM_RX_DESC     8
  67
  68 /* The size of the rx descriptor is determined by how much padding is used.
  69    4, 20, or 52 bytes of padding can be used */
  70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  71 /* aligned cache line size */
  72 #define RX_BUF_ALIGNE_SIZE      (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
  73
  74 /* Rx descriptor. We always use 4 bytes of padding */
  75 struct rx_desc_s {
  76         volatile u32 rd0;
  77         volatile u32 rd1;
  78         u32 rd2;                /* Buffer start */
  79         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  80 };
  81
  82 struct sh_eth_info {
  83         struct tx_desc_s *tx_desc_alloc;
  84         struct tx_desc_s *tx_desc_base;
  85         struct tx_desc_s *tx_desc_cur;
  86         struct rx_desc_s *rx_desc_alloc;
  87         struct rx_desc_s *rx_desc_base;
  88         struct rx_desc_s *rx_desc_cur;
  89         u8 *rx_buf_alloc;
  90         u8 *rx_buf_base;
  91         u8 mac_addr[6];
  92         u8 phy_addr;
  93         struct eth_device *dev;
  94         struct phy_device *phydev;
  95         void __iomem *iobase;
  96 };
  97
  98 struct sh_eth_dev {
  99         int port;
 100         struct sh_eth_info port_info[MAX_PORT_NUM];
 101 };
 102
 103 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
 104 enum {
 105         /* E-DMAC registers */
 106         EDSR = 0,
 107         EDMR,
 108         EDTRR,
 109         EDRRR,
 110         EESR,
 111         EESIPR,
 112         TDLAR,
 113         TDFAR,
 114         TDFXR,
 115         TDFFR,
 116         RDLAR,
 117         RDFAR,
 118         RDFXR,
 119         RDFFR,
 120         TRSCER,
 121         RMFCR,
 122         TFTR,
 123         FDR,
 124         RMCR,
 125         EDOCR,
 126         TFUCR,
 127         RFOCR,
 128         FCFTR,
 129         RPADIR,
 130         TRIMD,
 131         RBWAR,
 132         TBRAR,
 133
 134         /* Ether registers */
 135         ECMR,
 136         ECSR,
 137         ECSIPR,
 138         PIR,
 139         PSR,
 140         RDMLR,
 141         PIPR,
 142         RFLR,
 143         IPGR,
 144         APR,
 145         MPR,
 146         PFTCR,
 147         PFRCR,
 148         RFCR,
 149         RFCF,
 150         TPAUSER,
 151         TPAUSECR,
 152         BCFR,
 153         BCFRR,
 154         GECMR,
 155         BCULR,
 156         MAHR,
 157         MALR,
 158         TROCR,
 159         CDCR,
 160         LCCR,
 161         CNDCR,
 162         CEFCR,
 163         FRECR,
 164         TSFRCR,
 165         TLFRCR,
 166         CERCR,
 167         CEECR,
 168         RMIIMR, /* R8A7790 */
 169         MAFCR,
 170         RTRATE,
 171         CSMR,
 172         RMII_MII,
 173
 174         /* This value must be written at last. */
 175         SH_ETH_MAX_REGISTER_OFFSET,
 176 };
 177
 178 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 179         [EDSR]  = 0x0000,
 180         [EDMR]  = 0x0400,
 181         [EDTRR] = 0x0408,
 182         [EDRRR] = 0x0410,
 183         [EESR]  = 0x0428,
 184         [EESIPR]        = 0x0430,
 185         [TDLAR] = 0x0010,
 186         [TDFAR] = 0x0014,
 187         [TDFXR] = 0x0018,
 188         [TDFFR] = 0x001c,
 189         [RDLAR] = 0x0030,
 190         [RDFAR] = 0x0034,
 191         [RDFXR] = 0x0038,
 192         [RDFFR] = 0x003c,
 193         [TRSCER]        = 0x0438,
 194         [RMFCR] = 0x0440,
 195         [TFTR]  = 0x0448,
 196         [FDR]   = 0x0450,
 197         [RMCR]  = 0x0458,
 198         [RPADIR]        = 0x0460,
 199         [FCFTR] = 0x0468,
 200         [CSMR] = 0x04E4,
 201
 202         [ECMR]  = 0x0500,
 203         [ECSR]  = 0x0510,
 204         [ECSIPR]        = 0x0518,
 205         [PIR]   = 0x0520,
 206         [PSR]   = 0x0528,
 207         [PIPR]  = 0x052c,
 208         [RFLR]  = 0x0508,
 209         [APR]   = 0x0554,
 210         [MPR]   = 0x0558,
 211         [PFTCR] = 0x055c,
 212         [PFRCR] = 0x0560,
 213         [TPAUSER]       = 0x0564,
 214         [GECMR] = 0x05b0,
 215         [BCULR] = 0x05b4,
 216         [MAHR]  = 0x05c0,
 217         [MALR]  = 0x05c8,
 218         [TROCR] = 0x0700,
 219         [CDCR]  = 0x0708,
 220         [LCCR]  = 0x0710,
 221         [CEFCR] = 0x0740,
 222         [FRECR] = 0x0748,
 223         [TSFRCR]        = 0x0750,
 224         [TLFRCR]        = 0x0758,
 225         [RFCR]  = 0x0760,
 226         [CERCR] = 0x0768,
 227         [CEECR] = 0x0770,
 228         [MAFCR] = 0x0778,
 229         [RMII_MII] =  0x0790,
 230 };
 231
 232 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 233         [ECMR]  = 0x0100,
 234         [RFLR]  = 0x0108,
 235         [ECSR]  = 0x0110,
 236         [ECSIPR]        = 0x0118,
 237         [PIR]   = 0x0120,
 238         [PSR]   = 0x0128,
 239         [RDMLR] = 0x0140,
 240         [IPGR]  = 0x0150,
 241         [APR]   = 0x0154,
 242         [MPR]   = 0x0158,
 243         [TPAUSER]       = 0x0164,
 244         [RFCF]  = 0x0160,
 245         [TPAUSECR]      = 0x0168,
 246         [BCFRR] = 0x016c,
 247         [MAHR]  = 0x01c0,
 248         [MALR]  = 0x01c8,
 249         [TROCR] = 0x01d0,
 250         [CDCR]  = 0x01d4,
 251         [LCCR]  = 0x01d8,
 252         [CNDCR] = 0x01dc,
 253         [CEFCR] = 0x01e4,
 254         [FRECR] = 0x01e8,
 255         [TSFRCR]        = 0x01ec,
 256         [TLFRCR]        = 0x01f0,
 257         [RFCR]  = 0x01f4,
 258         [MAFCR] = 0x01f8,
 259         [RTRATE]        = 0x01fc,
 260
 261         [EDMR]  = 0x0000,
 262         [EDTRR] = 0x0008,
 263         [EDRRR] = 0x0010,
 264         [TDLAR] = 0x0018,
 265         [RDLAR] = 0x0020,
 266         [EESR]  = 0x0028,
 267         [EESIPR]        = 0x0030,
 268         [TRSCER]        = 0x0038,
 269         [RMFCR] = 0x0040,
 270         [TFTR]  = 0x0048,
 271         [FDR]   = 0x0050,
 272         [RMCR]  = 0x0058,
 273         [TFUCR] = 0x0064,
 274         [RFOCR] = 0x0068,
 275         [RMIIMR] = 0x006C,
 276         [FCFTR] = 0x0070,
 277         [RPADIR]        = 0x0078,
 278         [TRIMD] = 0x007c,
 279         [RBWAR] = 0x00c8,
 280         [RDFAR] = 0x00cc,
 281         [TBRAR] = 0x00d4,
 282         [TDFAR] = 0x00d8,
 283 };
 284
 285 /* Register Address */
 286 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 287 #define SH_ETH_TYPE_GETHER
 288 #define BASE_IO_ADDR    0xfee00000
 289 #elif defined(CONFIG_CPU_SH7757) || \
 290         defined(CONFIG_CPU_SH7752) || \
 291         defined(CONFIG_CPU_SH7753)
 292 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 293 #define SH_ETH_TYPE_GETHER
 294 #define BASE_IO_ADDR    0xfee00000
 295 #else
 296 #define SH_ETH_TYPE_ETHER
 297 #define BASE_IO_ADDR    0xfef00000
 298 #endif
 299 #elif defined(CONFIG_CPU_SH7724)
 300 #define SH_ETH_TYPE_ETHER
 301 #define BASE_IO_ADDR    0xA4600000
 302 #elif defined(CONFIG_R8A7740)
 303 #define SH_ETH_TYPE_GETHER
 304 #define BASE_IO_ADDR    0xE9A00000
 305 #elif defined(CONFIG_RCAR_GEN2)
 306 #define SH_ETH_TYPE_ETHER
 307 #define BASE_IO_ADDR    0xEE700200
 308 #elif defined(CONFIG_R7S72100)
 309 #define SH_ETH_TYPE_RZ
 310 #define BASE_IO_ADDR    0xE8203000
 311 #endif
 312
 313 /*
 314  * Register's bits
 315  * Copy from Linux driver source code
 316  */
 317 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 318 /* EDSR */
 319 enum EDSR_BIT {
 320         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 321 };
 322 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 323 #endif
 324
 325 /* EDMR */
 326 enum DMAC_M_BIT {
 327         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 328 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 329         EDMR_SRST       = 0x03, /* Receive/Send reset */
 330         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 331         EDMR_EL         = 0x40, /* Litte endian */
 332 #elif defined(SH_ETH_TYPE_ETHER)
 333         EDMR_SRST       = 0x01,
 334         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 335         EDMR_EL         = 0x40, /* Litte endian */
 336 #else
 337         EDMR_SRST = 0x01,
 338 #endif
 339 };
 340
 341 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
 342 # define EMDR_DESC EDMR_DL1
 343 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
 344 # define EMDR_DESC EDMR_DL0
 345 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
 346 # define EMDR_DESC 0
 347 #endif
 348
 349 /* RFLR */
 350 #define RFLR_RFL_MIN    0x05EE  /* Recv Frame length 1518 byte */
 351
 352 /* EDTRR */
 353 enum DMAC_T_BIT {
 354 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 355         EDTRR_TRNS = 0x03,
 356 #else
 357         EDTRR_TRNS = 0x01,
 358 #endif
 359 };
 360
 361 /* GECMR */
 362 enum GECMR_BIT {
 363 #if defined(CONFIG_CPU_SH7757) || \
 364         defined(CONFIG_CPU_SH7752) || \
 365         defined(CONFIG_CPU_SH7753)
 366         GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 367 #else
 368         GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
 369 #endif
 370 };
 371
 372 /* EDRRR*/
 373 enum EDRRR_R_BIT {
 374         EDRRR_R = 0x01,
 375 };
 376
 377 /* TPAUSER */
 378 enum TPAUSER_BIT {
 379         TPAUSER_TPAUSE = 0x0000ffff,
 380         TPAUSER_UNLIMITED = 0,
 381 };
 382
 383 /* BCFR */
 384 enum BCFR_BIT {
 385         BCFR_RPAUSE = 0x0000ffff,
 386         BCFR_UNLIMITED = 0,
 387 };
 388
 389 /* PIR */
 390 enum PIR_BIT {
 391         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 392 };
 393
 394 /* PSR */
 395 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 396
 397 /* EESR */
 398 enum EESR_BIT {
 399 #if defined(SH_ETH_TYPE_ETHER)
 400         EESR_TWB  = 0x40000000,
 401 #else
 402         EESR_TWB  = 0xC0000000,
 403         EESR_TC1  = 0x20000000,
 404         EESR_TUC  = 0x10000000,
 405         EESR_ROC  = 0x80000000,
 406 #endif
 407         EESR_TABT = 0x04000000,
 408         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 409 #if defined(SH_ETH_TYPE_ETHER)
 410         EESR_ADE  = 0x00800000,
 411 #endif
 412         EESR_ECI  = 0x00400000,
 413         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 414         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 415         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 416 #if defined(SH_ETH_TYPE_ETHER)
 417         EESR_CND  = 0x00000800,
 418 #endif
 419         EESR_DLC  = 0x00000400,
 420         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 421         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 422         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 423         EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 424         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 425 };
 426
 427
 428 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 429 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 430 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 431                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 432 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 433
 434 #else
 435 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 436 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 437                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 438 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 439 #endif
 440
 441 /* EESIPR */
 442 enum DMAC_IM_BIT {
 443         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 444         DMAC_M_RABT = 0x02000000,
 445         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 446         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 447         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 448         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 449         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 450         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 451         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 452         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 453         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 454         DMAC_M_RINT1 = 0x00000001,
 455 };
 456
 457 /* Receive descriptor bit */
 458 enum RD_STS_BIT {
 459         RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
 460         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 461         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 462         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 463         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 464         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 465         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 466         RD_RFS1 = 0x00000001,
 467 };
 468 #define RDF1ST  RD_RFP1
 469 #define RDFEND  RD_RFP0
 470 #define RD_RFP  (RD_RFP1|RD_RFP0)
 471
 472 /* RDFFR*/
 473 enum RDFFR_BIT {
 474         RDFFR_RDLF = 0x01,
 475 };
 476
 477 /* FCFTR */
 478 enum FCFTR_BIT {
 479         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 480         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 481         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 482 };
 483 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 484 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 485
 486 /* Transfer descriptor bit */
 487 enum TD_STS_BIT {
 488 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
 489         defined(SH_ETH_TYPE_RZ)
 490         TD_TACT = 0x80000000,
 491 #else
 492         TD_TACT = 0x7fffffff,
 493 #endif
 494         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 495         TD_TFP0 = 0x10000000,
 496 };
 497 #define TDF1ST  TD_TFP1
 498 #define TDFEND  TD_TFP0
 499 #define TD_TFP  (TD_TFP1|TD_TFP0)
 500
 501 /* RMCR */
 502 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 503 /* ECMR */
 504 enum FELIC_MODE_BIT {
 505 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 506         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 507         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 508 #endif
 509         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 510         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 511         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 512         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 513         ECMR_PRM = 0x00000001,
 514 #ifdef CONFIG_CPU_SH7724
 515         ECMR_RTM = 0x00000010,
 516 #elif defined(CONFIG_RCAR_GEN2)
 517         ECMR_RTM = 0x00000004,
 518 #endif
 519
 520 };
 521
 522 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 523 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
 524                         ECMR_RXF | ECMR_TXF | ECMR_MCT)
 525 #elif defined(SH_ETH_TYPE_ETHER)
 526 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 527 #else
 528 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 529 #endif
 530
 531 /* ECSR */
 532 enum ECSR_STATUS_BIT {
 533 #if defined(SH_ETH_TYPE_ETHER)
 534         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 535 #endif
 536         ECSR_LCHNG = 0x04,
 537         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 538 };
 539
 540 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 541 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 542 #else
 543 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 544                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 545 #endif
 546
 547 /* ECSIPR */
 548 enum ECSIPR_STATUS_MASK_BIT {
 549 #if defined(SH_ETH_TYPE_ETHER)
 550         ECSIPR_BRCRXIP = 0x20,
 551         ECSIPR_PSRTOIP = 0x10,
 552 #elif defined(SH_ETY_TYPE_GETHER)
 553         ECSIPR_PSRTOIP = 0x10,
 554         ECSIPR_PHYIP = 0x08,
 555 #endif
 556         ECSIPR_LCHNGIP = 0x04,
 557         ECSIPR_MPDIP = 0x02,
 558         ECSIPR_ICDIP = 0x01,
 559 };
 560
 561 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 562 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 563 #else
 564 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 565                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 566 #endif
 567
 568 /* APR */
 569 enum APR_BIT {
 570         APR_AP = 0x00000004,
 571 };
 572
 573 /* MPR */
 574 enum MPR_BIT {
 575         MPR_MP = 0x00000006,
 576 };
 577
 578 /* TRSCER */
 579 enum DESC_I_BIT {
 580         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 581         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 582         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 583         DESC_I_RINT1 = 0x0001,
 584 };
 585
 586 /* RPADIR */
 587 enum RPADIR_BIT {
 588         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 589         RPADIR_PADR = 0x0003f,
 590 };
 591
 592 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 593 # define RPADIR_INIT (0x00)
 594 #else
 595 # define RPADIR_INIT (RPADIR_PADS1)
 596 #endif
 597
 598 /* FDR */
 599 enum FIFO_SIZE_BIT {
 600         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 601 };
 602
 603 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
 604                                             int enum_index)
 605 {
 606 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 607         const u16 *reg_offset = sh_eth_offset_gigabit;
 608 #elif defined(SH_ETH_TYPE_ETHER)
 609         const u16 *reg_offset = sh_eth_offset_fast_sh4;
 610 #else
 611 #error
 612 #endif
 613         return (unsigned long)port->iobase + reg_offset[enum_index];
 614 }
 615
 616 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
 617                                 int enum_index)
 618 {
 619         outl(data, sh_eth_reg_addr(port, enum_index));
 620 }
 621
 622 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
 623                                         int enum_index)
 624 {
 625         return inl(sh_eth_reg_addr(port, enum_index));
 626 }