drivers/net/sh_eth.h

   1 /*
   2  * sh_eth.h - Driver for Renesas SuperH ethernet controler.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <netdev.h>
  24 #include <asm/types.h>
  25
  26 #define SHETHER_NAME "sh_eth"
  27
  28 /* Malloc returns addresses in the P1 area (cacheable). However we need to
  29    use area P2 (non-cacheable) */
  30 #define ADDR_TO_P2(addr)        ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  31
  32 /* The ethernet controller needs to use physical addresses */
  33 #if defined(CONFIG_SH_32BIT)
  34 #define ADDR_TO_PHY(addr)       ((((int)(addr) & ~0xe0000000) | 0x40000000))
  35 #else
  36 #define ADDR_TO_PHY(addr)       ((int)(addr) & ~0xe0000000)
  37 #endif
  38
  39 /* Number of supported ports */
  40 #define MAX_PORT_NUM    2
  41
  42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  43    buffers must be a multiple of 32 bytes */
  44 #define MAX_BUF_SIZE    (48 * 32)
  45
  46 /* The number of tx descriptors must be large enough to point to 5 or more
  47    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  48    We use one descriptor per frame */
  49 #define NUM_TX_DESC             8
  50
  51 /* The size of the tx descriptor is determined by how much padding is used.
  52    4, 20, or 52 bytes of padding can be used */
  53 #define TX_DESC_PADDING         4
  54 #define TX_DESC_SIZE            (12 + TX_DESC_PADDING)
  55
  56 /* Tx descriptor. We always use 3 bytes of padding */
  57 struct tx_desc_s {
  58         volatile u32 td0;
  59         u32 td1;
  60         u32 td2;                /* Buffer start */
  61         u32 padding;
  62 };
  63
  64 /* There is no limitation in the number of rx descriptors */
  65 #define NUM_RX_DESC     8
  66
  67 /* The size of the rx descriptor is determined by how much padding is used.
  68    4, 20, or 52 bytes of padding can be used */
  69 #define RX_DESC_PADDING         4
  70 #define RX_DESC_SIZE            (12 + RX_DESC_PADDING)
  71
  72 /* Rx descriptor. We always use 4 bytes of padding */
  73 struct rx_desc_s {
  74         volatile u32 rd0;
  75         volatile u32 rd1;
  76         u32 rd2;                /* Buffer start */
  77         u32 padding;
  78 };
  79
  80 struct sh_eth_info {
  81         struct tx_desc_s *tx_desc_malloc;
  82         struct tx_desc_s *tx_desc_base;
  83         struct tx_desc_s *tx_desc_cur;
  84         struct rx_desc_s *rx_desc_malloc;
  85         struct rx_desc_s *rx_desc_base;
  86         struct rx_desc_s *rx_desc_cur;
  87         u8 *rx_buf_malloc;
  88         u8 *rx_buf_base;
  89         u8 mac_addr[6];
  90         u8 phy_addr;
  91         struct eth_device *dev;
  92         struct phy_device *phydev;
  93 };
  94
  95 struct sh_eth_dev {
  96         int port;
  97         struct sh_eth_info port_info[MAX_PORT_NUM];
  98 };
  99
 100 /* Register Address */
 101 #ifdef CONFIG_CPU_SH7763
 102 #define BASE_IO_ADDR    0xfee00000
 103
 104 #define EDSR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
 105
 106 #define TDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
 107 #define TDFAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
 108 #define TDFXR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
 109 #define TDFFR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
 110
 111 #define RDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
 112 #define RDFAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
 113 #define RDFXR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
 114 #define RDFFR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
 115
 116 #define EDMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
 117 #define EDTRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
 118 #define EDRRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
 119 #define EESR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
 120 #define EESIPR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
 121 #define TRSCER(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
 122 #define TFTR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
 123 #define FDR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
 124 #define RMCR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
 125 #define RPADIR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
 126 #define FCFTR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
 127 #define ECMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
 128 #define RFLR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
 129 #define ECSIPR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
 130 #define PIR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
 131 #define PIPR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
 132 #define APR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
 133 #define MPR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
 134 #define TPAUSER(port)   (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
 135 #define GECMR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
 136 #define MALR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
 137 #define MAHR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
 138
 139 #elif defined(CONFIG_CPU_SH7757)
 140 #define BASE_IO_ADDR    0xfef00000
 141
 142 #define TDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
 143 #define RDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
 144
 145 #define EDMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
 146 #define EDTRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
 147 #define EDRRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
 148 #define EESR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
 149 #define EESIPR(port)            (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
 150 #define TRSCER(port)            (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
 151 #define TFTR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
 152 #define FDR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
 153 #define RMCR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
 154 #define FCFTR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
 155 #define ECMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
 156 #define RFLR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
 157 #define ECSIPR(port)            (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
 158 #define PIR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
 159 #define APR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
 160 #define MPR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
 161 #define TPAUSER(port)           (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
 162 #define MAHR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
 163 #define MALR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
 164 #define RTRATE(port)            (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
 165
 166 #elif defined(CONFIG_CPU_SH7724)
 167 #define BASE_IO_ADDR    0xA4600000
 168
 169 #define TDLAR(port)             (BASE_IO_ADDR + 0x0018)
 170 #define RDLAR(port)             (BASE_IO_ADDR + 0x0020)
 171
 172 #define EDMR(port)              (BASE_IO_ADDR + 0x0000)
 173 #define EDTRR(port)             (BASE_IO_ADDR + 0x0008)
 174 #define EDRRR(port)             (BASE_IO_ADDR + 0x0010)
 175 #define EESR(port)              (BASE_IO_ADDR + 0x0028)
 176 #define EESIPR(port)    (BASE_IO_ADDR + 0x0030)
 177 #define TRSCER(port)    (BASE_IO_ADDR + 0x0038)
 178 #define TFTR(port)              (BASE_IO_ADDR + 0x0048)
 179 #define FDR(port)               (BASE_IO_ADDR + 0x0050)
 180 #define RMCR(port)              (BASE_IO_ADDR + 0x0058)
 181 #define FCFTR(port)             (BASE_IO_ADDR + 0x0070)
 182 #define ECMR(port)              (BASE_IO_ADDR + 0x0100)
 183 #define RFLR(port)              (BASE_IO_ADDR + 0x0108)
 184 #define ECSIPR(port)    (BASE_IO_ADDR + 0x0118)
 185 #define PIR(port)               (BASE_IO_ADDR + 0x0120)
 186 #define APR(port)               (BASE_IO_ADDR + 0x0154)
 187 #define MPR(port)               (BASE_IO_ADDR + 0x0158)
 188 #define TPAUSER(port)   (BASE_IO_ADDR + 0x0164)
 189 #define MAHR(port)              (BASE_IO_ADDR + 0x01c0)
 190 #define MALR(port)              (BASE_IO_ADDR + 0x01c8)
 191 #endif
 192
 193 /*
 194  * Register's bits
 195  * Copy from Linux driver source code
 196  */
 197 #ifdef CONFIG_CPU_SH7763
 198 /* EDSR */
 199 enum EDSR_BIT {
 200         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 201 };
 202 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 203 #endif
 204
 205 /* EDMR */
 206 enum DMAC_M_BIT {
 207         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 208 #ifdef CONFIG_CPU_SH7763
 209         EDMR_SRST       = 0x03,
 210         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 211         EDMR_EL         = 0x40, /* Litte endian */
 212 #elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
 213         EDMR_SRST       = 0x01,
 214         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 215         EDMR_EL         = 0x40, /* Litte endian */
 216 #else /* CONFIG_CPU_SH7763 */
 217         EDMR_SRST = 0x01,
 218 #endif
 219 };
 220
 221 /* RFLR */
 222 #define RFLR_RFL_MIN    0x05EE  /* Recv Frame length 1518 byte */
 223
 224 /* EDTRR */
 225 enum DMAC_T_BIT {
 226 #ifdef CONFIG_CPU_SH7763
 227         EDTRR_TRNS = 0x03,
 228 #else
 229         EDTRR_TRNS = 0x01,
 230 #endif
 231 };
 232
 233 /* GECMR */
 234 enum GECMR_BIT {
 235         GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
 236 };
 237
 238 /* EDRRR*/
 239 enum EDRRR_R_BIT {
 240         EDRRR_R = 0x01,
 241 };
 242
 243 /* TPAUSER */
 244 enum TPAUSER_BIT {
 245         TPAUSER_TPAUSE = 0x0000ffff,
 246         TPAUSER_UNLIMITED = 0,
 247 };
 248
 249 /* BCFR */
 250 enum BCFR_BIT {
 251         BCFR_RPAUSE = 0x0000ffff,
 252         BCFR_UNLIMITED = 0,
 253 };
 254
 255 /* PIR */
 256 enum PIR_BIT {
 257         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 258 };
 259
 260 /* PSR */
 261 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 262
 263 /* EESR */
 264 enum EESR_BIT {
 265 #ifndef CONFIG_CPU_SH7763
 266         EESR_TWB  = 0x40000000,
 267 #else
 268         EESR_TWB  = 0xC0000000,
 269         EESR_TC1  = 0x20000000,
 270         EESR_TUC  = 0x10000000,
 271         EESR_ROC  = 0x80000000,
 272 #endif
 273         EESR_TABT = 0x04000000,
 274         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 275 #ifndef CONFIG_CPU_SH7763
 276         EESR_ADE  = 0x00800000,
 277 #endif
 278         EESR_ECI  = 0x00400000,
 279         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 280         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 281         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 282 #ifndef CONFIG_CPU_SH7763
 283         EESR_CND  = 0x00000800,
 284 #endif
 285         EESR_DLC  = 0x00000400,
 286         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 287         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 288         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 289         rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 290         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 291 };
 292
 293
 294 #ifdef CONFIG_CPU_SH7763
 295 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 296 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 297                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 298 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 299
 300 #else
 301 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 302 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 303                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 304 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 305 #endif
 306
 307 /* EESIPR */
 308 enum DMAC_IM_BIT {
 309         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 310         DMAC_M_RABT = 0x02000000,
 311         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 312         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 313         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 314         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 315         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 316         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 317         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 318         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 319         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 320         DMAC_M_RINT1 = 0x00000001,
 321 };
 322
 323 /* Receive descriptor bit */
 324 enum RD_STS_BIT {
 325         RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
 326         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 327         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 328         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 329         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 330         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 331         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 332         RD_RFS1 = 0x00000001,
 333 };
 334 #define RDF1ST  RD_RFP1
 335 #define RDFEND  RD_RFP0
 336 #define RD_RFP  (RD_RFP1|RD_RFP0)
 337
 338 /* RDFFR*/
 339 enum RDFFR_BIT {
 340         RDFFR_RDLF = 0x01,
 341 };
 342
 343 /* FCFTR */
 344 enum FCFTR_BIT {
 345         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 346         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 347         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 348 };
 349 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 350 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 351
 352 /* Transfer descriptor bit */
 353 enum TD_STS_BIT {
 354 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
 355                 || defined(CONFIG_CPU_SH7724)
 356         TD_TACT = 0x80000000,
 357 #else
 358         TD_TACT = 0x7fffffff,
 359 #endif
 360         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 361         TD_TFP0 = 0x10000000,
 362 };
 363 #define TDF1ST  TD_TFP1
 364 #define TDFEND  TD_TFP0
 365 #define TD_TFP  (TD_TFP1|TD_TFP0)
 366
 367 /* RMCR */
 368 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 369 /* ECMR */
 370 enum FELIC_MODE_BIT {
 371 #ifdef CONFIG_CPU_SH7763
 372         ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 373         ECMR_RZPF = 0x00100000,
 374 #endif
 375         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 376         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 377         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 378         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 379         ECMR_PRM = 0x00000001,
 380 #ifdef CONFIG_CPU_SH7724
 381         ECMR_RTM = 0x00000010,
 382 #endif
 383
 384 };
 385
 386 #ifdef CONFIG_CPU_SH7763
 387 #define ECMR_CHG_DM     (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 388                                                 ECMR_TXF | ECMR_MCT)
 389 #elif CONFIG_CPU_SH7757
 390 #define ECMR_CHG_DM     (ECMR_ZPF)
 391 #elif CONFIG_CPU_SH7724
 392 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 393 #else
 394 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 395 #endif
 396
 397 /* ECSR */
 398 enum ECSR_STATUS_BIT {
 399 #ifndef CONFIG_CPU_SH7763
 400         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 401 #endif
 402         ECSR_LCHNG = 0x04,
 403         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 404 };
 405
 406 #ifdef CONFIG_CPU_SH7763
 407 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 408 #else
 409 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 410                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 411 #endif
 412
 413 /* ECSIPR */
 414 enum ECSIPR_STATUS_MASK_BIT {
 415 #ifndef CONFIG_CPU_SH7763
 416         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 417 #endif
 418         ECSIPR_LCHNGIP = 0x04,
 419         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 420 };
 421
 422 #ifdef CONFIG_CPU_SH7763
 423 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 424 #else
 425 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 426                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 427 #endif
 428
 429 /* APR */
 430 enum APR_BIT {
 431 #ifdef CONFIG_CPU_SH7757
 432         APR_AP = 0x00000001,
 433 #else
 434         APR_AP = 0x00000004,
 435 #endif
 436 };
 437
 438 /* MPR */
 439 enum MPR_BIT {
 440 #ifdef CONFIG_CPU_SH7757
 441         MPR_MP = 0x00000001,
 442 #else
 443         MPR_MP = 0x00000006,
 444 #endif
 445 };
 446
 447 /* TRSCER */
 448 enum DESC_I_BIT {
 449         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 450         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 451         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 452         DESC_I_RINT1 = 0x0001,
 453 };
 454
 455 /* RPADIR */
 456 enum RPADIR_BIT {
 457         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 458         RPADIR_PADR = 0x0003f,
 459 };
 460
 461 #ifdef CONFIG_CPU_SH7763
 462 # define RPADIR_INIT (0x00)
 463 #else
 464 # define RPADIR_INIT (RPADIR_PADS1)
 465 #endif
 466
 467 /* FDR */
 468 enum FIFO_SIZE_BIT {
 469         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 470 };