drivers/net/sk98lin/h/skdrv2nd.h

   1 /******************************************************************************
   2  *
   3  * Name:        skdrv2nd.h
   4  * Project:     GEnesis, PCI Gigabit Ethernet Adapter
   5  * Version:     $Revision: 1.15 $
   6  * Date:        $Date: 2003/02/25 14:16:40 $
   7  * Purpose:     Second header file for driver and all other modules
   8  *
   9  ******************************************************************************/
  10
  11 /******************************************************************************
  12  *
  13  *      (C)Copyright 1998-2003 SysKonnect GmbH.
  14  *
  15  *      This program is free software; you can redistribute it and/or modify
  16  *      it under the terms of the GNU General Public License as published by
  17  *      the Free Software Foundation; either version 2 of the License, or
  18  *      (at your option) any later version.
  19  *
  20  *      The information in this file is provided "AS IS" without warranty.
  21  *
  22  ******************************************************************************/
  23
  24 /******************************************************************************
  25  *
  26  * History:
  27  *
  28  *      $Log: skdrv2nd.h,v $
  29  *      Revision 1.15  2003/02/25 14:16:40  mlindner
  30  *      Fix: Copyright statement
  31  *
  32  *      Revision 1.14  2003/02/25 13:26:26  mlindner
  33  *      Add: Support for various vendors
  34  *
  35  *      Revision 1.13  2002/10/02 12:46:02  mlindner
  36  *      Add: Support for Yukon
  37  *
  38  *      Revision 1.12.2.2  2001/09/05 12:14:50  mlindner
  39  *      add: New hardware revision int
  40  *
  41  *      Revision 1.12.2.1  2001/03/12 16:50:59  mlindner
  42  *      chg: kernel 2.4 adaption
  43  *
  44  *      Revision 1.12  2001/03/01 12:52:15  mlindner
  45  *      Fixed ring size
  46  *
  47  *      Revision 1.11  2001/02/19 13:28:02  mlindner
  48  *      Changed PNMI parameter values
  49  *
  50  *      Revision 1.10  2001/01/22 14:16:04  mlindner
  51  *      added ProcFs functionality
  52  *      Dual Net functionality integrated
  53  *      Rlmt networks added
  54  *
  55  *      Revision 1.1  2000/10/05 19:46:50  phargrov
  56  *      Add directory src/vipk_devs_nonlbl/vipk_sk98lin/
  57  *      This is the SysKonnect SK-98xx Gigabit Ethernet driver,
  58  *      contributed by SysKonnect.
  59  *
  60  *      Revision 1.9  2000/02/21 10:39:55  cgoos
  61  *      Added flag for jumbo support usage.
  62  *
  63  *      Revision 1.8  1999/11/22 13:50:44  cgoos
  64  *      Changed license header to GPL.
  65  *      Fixed two comments.
  66  *
  67  *      Revision 1.7  1999/09/28 12:38:21  cgoos
  68  *      Added CheckQueue to SK_AC.
  69  *
  70  *      Revision 1.6  1999/07/27 08:04:05  cgoos
  71  *      Added checksumming variables to SK_AC.
  72  *
  73  *      Revision 1.5  1999/03/29 12:33:26  cgoos
  74  *      Rreversed to fine lock granularity.
  75  *
  76  *      Revision 1.4  1999/03/15 12:14:02  cgoos
  77  *      Added DriverLock to SK_AC.
  78  *      Removed other locks.
  79  *
  80  *      Revision 1.3  1999/03/01 08:52:27  cgoos
  81  *      Changed pAC->PciDev declaration.
  82  *
  83  *      Revision 1.2  1999/02/18 10:57:14  cgoos
  84  *      Removed SkDrvTimeStamp prototype.
  85  *      Fixed SkGeOsGetTime prototype.
  86  *
  87  *      Revision 1.1  1999/02/16 07:41:01  cgoos
  88  *      First version.
  89  *
  90  *
  91  *
  92  ******************************************************************************/
  93
  94 /******************************************************************************
  95  *
  96  * Description:
  97  *
  98  * This is the second include file of the driver, which includes all other
  99  * neccessary files and defines all structures and constants used by the
 100  * driver and the common modules.
 101  *
 102  * Include File Hierarchy:
 103  *
 104  *      see skge.c
 105  *
 106  ******************************************************************************/
 107
 108 #ifndef __INC_SKDRV2ND_H
 109 #define __INC_SKDRV2ND_H
 110
 111 #include "h/skqueue.h"
 112 #include "h/skgehwt.h"
 113 #include "h/sktimer.h"
 114 #include "h/ski2c.h"
 115 #include "h/skgepnmi.h"
 116 #include "h/skvpd.h"
 117 #include "h/skgehw.h"
 118 #include "h/skgeinit.h"
 119 #include "h/skaddr.h"
 120 #include "h/skgesirq.h"
 121 #include "h/skcsum.h"
 122 #include "h/skrlmt.h"
 123 #include "h/skgedrv.h"
 124
 125 #define SK_PCI_ISCOMPLIANT(result, pdev) {     \
 126     result = SK_FALSE; /* default */     \
 127     /* 3Com (0x10b7) */     \
 128     if (pdev->vendor == 0x10b7) {     \
 129         /* Gigabit Ethernet Adapter (0x1700) */     \
 130         if ((pdev->device == 0x1700)) { \
 131             result = SK_TRUE;     \
 132         }     \
 133     /* SysKonnect (0x1148) */     \
 134     } else if (pdev->vendor == 0x1148) {     \
 135         /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */     \
 136         /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */     \
 137         if ((pdev->device == 0x4300) || \
 138             (pdev->device == 0x4320)) { \
 139             result = SK_TRUE;     \
 140         }     \
 141     /* D-Link (0x1186) */     \
 142     } else if (pdev->vendor == 0x1186) {     \
 143         /* Gigabit Ethernet Adapter (0x4c00) */     \
 144         if ((pdev->device == 0x4c00)) { \
 145             result = SK_TRUE;     \
 146         }     \
 147     /* CNet (0x1371) */     \
 148     } else if (pdev->vendor == 0x1371) {     \
 149         /* GigaCard Network Adapter (0x434e) */     \
 150         if ((pdev->device == 0x434e)) { \
 151             result = SK_TRUE;     \
 152         }     \
 153     /* Linksys (0x1737) */     \
 154     } else if (pdev->vendor == 0x1737) {     \
 155         /* Gigabit Network Adapter (0x1032) */     \
 156         /* Gigabit Network Adapter (0x1064) */     \
 157         if ((pdev->device == 0x1032) || \
 158             (pdev->device == 0x1064)) { \
 159             result = SK_TRUE;     \
 160         }     \
 161     } else {     \
 162         result = SK_FALSE;     \
 163     }     \
 164 }
 165
 166
 167 extern SK_MBUF          *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
 168 extern void             SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
 169 extern SK_U64           SkOsGetTime(SK_AC*);
 170 extern int              SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
 171 extern int              SkPciReadCfgWord(SK_AC*, int, SK_U16*);
 172 extern int              SkPciReadCfgByte(SK_AC*, int, SK_U8*);
 173 extern int              SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
 174 extern int              SkPciWriteCfgWord(SK_AC*, int, SK_U16);
 175 extern int              SkPciWriteCfgByte(SK_AC*, int, SK_U8);
 176 extern int              SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
 177
 178 struct s_DrvRlmtMbuf {
 179         SK_MBUF         *pNext;         /* Pointer to next RLMT Mbuf. */
 180         SK_U8           *pData;         /* Data buffer (virtually contig.). */
 181         unsigned        Size;           /* Data buffer size. */
 182         unsigned        Length;         /* Length of packet (<= Size). */
 183         SK_U32          PortIdx;        /* Receiving/transmitting port. */
 184 #ifdef SK_RLMT_MBUF_PRIVATE
 185         SK_RLMT_MBUF    Rlmt;           /* Private part for RLMT. */
 186 #endif  /* SK_RLMT_MBUF_PRIVATE */
 187         struct sk_buff  *pOs;           /* Pointer to message block */
 188 };
 189
 190
 191 /*
 192  * ioctl definitions
 193  */
 194 #define         SK_IOCTL_BASE           (SIOCDEVPRIVATE)
 195 #define         SK_IOCTL_GETMIB         (SK_IOCTL_BASE + 0)
 196 #define         SK_IOCTL_SETMIB         (SK_IOCTL_BASE + 1)
 197 #define         SK_IOCTL_PRESETMIB      (SK_IOCTL_BASE + 2)
 198
 199 typedef struct s_IOCTL  SK_GE_IOCTL;
 200
 201 struct s_IOCTL {
 202         char*           pData;
 203         unsigned int    Len;
 204 };
 205
 206
 207 /*
 208  * define sizes of descriptor rings in bytes
 209  */
 210
 211 #if 0
 212 #define         TX_RING_SIZE    (8*1024)
 213 #define         RX_RING_SIZE    (24*1024)
 214 #else
 215 #define         TX_RING_SIZE    (10 * 40)
 216 #define         RX_RING_SIZE    (10 * 40)
 217 #endif
 218
 219 /*
 220  * Buffer size for ethernet packets
 221  */
 222 #define ETH_BUF_SIZE    1540
 223 #define ETH_MAX_MTU     1514
 224 #define ETH_MIN_MTU     60
 225 #define ETH_MULTICAST_BIT       0x01
 226 #define SK_JUMBO_MTU    9000
 227
 228 /*
 229  * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
 230  */
 231 #define TX_PRIO_LOW     0
 232 #define TX_PRIO_HIGH    1
 233
 234 /*
 235  * alignment of rx/tx descriptors
 236  */
 237 #define DESCR_ALIGN     8
 238
 239 /*
 240  * definitions for pnmi. TODO
 241  */
 242 #define SK_DRIVER_RESET(pAC, IoC)       0
 243 #define SK_DRIVER_SENDEVENT(pAC, IoC)   0
 244 #define SK_DRIVER_SELFTEST(pAC, IoC)    0
 245 /* For get mtu you must add an own function */
 246 #define SK_DRIVER_GET_MTU(pAc,IoC,i)    0
 247 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v)  0
 248 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v)       0
 249
 250
 251 /* TX and RX descriptors *****************************************************/
 252
 253 typedef struct s_RxD RXD; /* the receive descriptor */
 254
 255 struct s_RxD {
 256         volatile SK_U32 RBControl;      /* Receive Buffer Control */
 257         SK_U32          VNextRxd;       /* Next receive descriptor,low dword */
 258         SK_U32          VDataLow;       /* Receive buffer Addr, low dword */
 259         SK_U32          VDataHigh;      /* Receive buffer Addr, high dword */
 260         SK_U32          FrameStat;      /* Receive Frame Status word */
 261         SK_U32          TimeStamp;      /* Time stamp from XMAC */
 262         SK_U32          TcpSums;        /* TCP Sum 2 / TCP Sum 1 */
 263         SK_U32          TcpSumStarts;   /* TCP Sum Start 2 / TCP Sum Start 1 */
 264         RXD             *pNextRxd;      /* Pointer to next Rxd */
 265         struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer */
 266 };
 267
 268 typedef struct s_TxD TXD; /* the transmit descriptor */
 269
 270 struct s_TxD {
 271         volatile SK_U32 TBControl;      /* Transmit Buffer Control */
 272         SK_U32          VNextTxd;       /* Next transmit descriptor,low dword */
 273         SK_U32          VDataLow;       /* Transmit Buffer Addr, low dword */
 274         SK_U32          VDataHigh;      /* Transmit Buffer Addr, high dword */
 275         SK_U32          FrameStat;      /* Transmit Frame Status Word */
 276         SK_U32          TcpSumOfs;      /* Reserved / TCP Sum Offset */
 277         SK_U16          TcpSumSt;       /* TCP Sum Start */
 278         SK_U16          TcpSumWr;       /* TCP Sum Write */
 279         SK_U32          TcpReserved;    /* not used */
 280         TXD             *pNextTxd;      /* Pointer to next Txd */
 281         struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer */
 282 };
 283
 284
 285 /* definition of flags in descriptor control field */
 286 #define RX_CTRL_OWN_BMU         UINT32_C(0x80000000)
 287 #define RX_CTRL_STF             UINT32_C(0x40000000)
 288 #define RX_CTRL_EOF             UINT32_C(0x20000000)
 289 #define RX_CTRL_EOB_IRQ         UINT32_C(0x10000000)
 290 #define RX_CTRL_EOF_IRQ         UINT32_C(0x08000000)
 291 #define RX_CTRL_DEV_NULL        UINT32_C(0x04000000)
 292 #define RX_CTRL_STAT_VALID      UINT32_C(0x02000000)
 293 #define RX_CTRL_TIME_VALID      UINT32_C(0x01000000)
 294 #define RX_CTRL_CHECK_DEFAULT   UINT32_C(0x00550000)
 295 #define RX_CTRL_CHECK_CSUM      UINT32_C(0x00560000)
 296 #define RX_CTRL_LEN_MASK        UINT32_C(0x0000FFFF)
 297
 298 #define TX_CTRL_OWN_BMU         UINT32_C(0x80000000)
 299 #define TX_CTRL_STF             UINT32_C(0x40000000)
 300 #define TX_CTRL_EOF             UINT32_C(0x20000000)
 301 #define TX_CTRL_EOB_IRQ         UINT32_C(0x10000000)
 302 #define TX_CTRL_EOF_IRQ         UINT32_C(0x08000000)
 303 #define TX_CTRL_ST_FWD          UINT32_C(0x04000000)
 304 #define TX_CTRL_DISAB_CRC       UINT32_C(0x02000000)
 305 #define TX_CTRL_SOFTWARE        UINT32_C(0x01000000)
 306 #define TX_CTRL_CHECK_DEFAULT   UINT32_C(0x00550000)
 307 #define TX_CTRL_CHECK_CSUM      UINT32_C(0x00560000)
 308 #define TX_CTRL_LEN_MASK        UINT32_C(0x0000FFFF)
 309
 310
 311 /* The offsets of registers in the TX and RX queue control io area ***********/
 312
 313 #define RX_Q_BUF_CTRL_CNT       0x00
 314 #define RX_Q_NEXT_DESCR_LOW     0x04
 315 #define RX_Q_BUF_ADDR_LOW       0x08
 316 #define RX_Q_BUF_ADDR_HIGH      0x0c
 317 #define RX_Q_FRAME_STAT         0x10
 318 #define RX_Q_TIME_STAMP         0x14
 319 #define RX_Q_CSUM_1_2           0x18
 320 #define RX_Q_CSUM_START_1_2     0x1c
 321 #define RX_Q_CUR_DESCR_LOW      0x20
 322 #define RX_Q_DESCR_HIGH         0x24
 323 #define RX_Q_CUR_ADDR_LOW       0x28
 324 #define RX_Q_CUR_ADDR_HIGH      0x2c
 325 #define RX_Q_CUR_BYTE_CNT       0x30
 326 #define RX_Q_CTRL               0x34
 327 #define RX_Q_FLAG               0x38
 328 #define RX_Q_TEST1              0x3c
 329 #define RX_Q_TEST2              0x40
 330 #define RX_Q_TEST3              0x44
 331
 332 #define TX_Q_BUF_CTRL_CNT       0x00
 333 #define TX_Q_NEXT_DESCR_LOW     0x04
 334 #define TX_Q_BUF_ADDR_LOW       0x08
 335 #define TX_Q_BUF_ADDR_HIGH      0x0c
 336 #define TX_Q_FRAME_STAT         0x10
 337 #define TX_Q_CSUM_START         0x14
 338 #define TX_Q_CSUM_START_POS     0x18
 339 #define TX_Q_RESERVED           0x1c
 340 #define TX_Q_CUR_DESCR_LOW      0x20
 341 #define TX_Q_DESCR_HIGH         0x24
 342 #define TX_Q_CUR_ADDR_LOW       0x28
 343 #define TX_Q_CUR_ADDR_HIGH      0x2c
 344 #define TX_Q_CUR_BYTE_CNT       0x30
 345 #define TX_Q_CTRL               0x34
 346 #define TX_Q_FLAG               0x38
 347 #define TX_Q_TEST1              0x3c
 348 #define TX_Q_TEST2              0x40
 349 #define TX_Q_TEST3              0x44
 350
 351 /* definition of flags in the queue control field */
 352 #define RX_Q_CTRL_POLL_ON       0x00000080
 353 #define RX_Q_CTRL_POLL_OFF      0x00000040
 354 #define RX_Q_CTRL_STOP          0x00000020
 355 #define RX_Q_CTRL_START         0x00000010
 356 #define RX_Q_CTRL_CLR_I_PAR     0x00000008
 357 #define RX_Q_CTRL_CLR_I_EOB     0x00000004
 358 #define RX_Q_CTRL_CLR_I_EOF     0x00000002
 359 #define RX_Q_CTRL_CLR_I_ERR     0x00000001
 360
 361 #define TX_Q_CTRL_POLL_ON       0x00000080
 362 #define TX_Q_CTRL_POLL_OFF      0x00000040
 363 #define TX_Q_CTRL_STOP          0x00000020
 364 #define TX_Q_CTRL_START         0x00000010
 365 #define TX_Q_CTRL_CLR_I_EOB     0x00000004
 366 #define TX_Q_CTRL_CLR_I_EOF     0x00000002
 367 #define TX_Q_CTRL_CLR_I_ERR     0x00000001
 368
 369
 370 /* Interrupt bits in the interrupts source register **************************/
 371 #define IRQ_HW_ERROR            0x80000000
 372 #define IRQ_RESERVED            0x40000000
 373 #define IRQ_PKT_TOUT_RX1        0x20000000
 374 #define IRQ_PKT_TOUT_RX2        0x10000000
 375 #define IRQ_PKT_TOUT_TX1        0x08000000
 376 #define IRQ_PKT_TOUT_TX2        0x04000000
 377 #define IRQ_I2C_READY           0x02000000
 378 #define IRQ_SW                  0x01000000
 379 #define IRQ_EXTERNAL_REG        0x00800000
 380 #define IRQ_TIMER               0x00400000
 381 #define IRQ_MAC1                0x00200000
 382 #define IRQ_LINK_SYNC_C_M1      0x00100000
 383 #define IRQ_MAC2                0x00080000
 384 #define IRQ_LINK_SYNC_C_M2      0x00040000
 385 #define IRQ_EOB_RX1             0x00020000
 386 #define IRQ_EOF_RX1             0x00010000
 387 #define IRQ_CHK_RX1             0x00008000
 388 #define IRQ_EOB_RX2             0x00004000
 389 #define IRQ_EOF_RX2             0x00002000
 390 #define IRQ_CHK_RX2             0x00001000
 391 #define IRQ_EOB_SY_TX1          0x00000800
 392 #define IRQ_EOF_SY_TX1          0x00000400
 393 #define IRQ_CHK_SY_TX1          0x00000200
 394 #define IRQ_EOB_AS_TX1          0x00000100
 395 #define IRQ_EOF_AS_TX1          0x00000080
 396 #define IRQ_CHK_AS_TX1          0x00000040
 397 #define IRQ_EOB_SY_TX2          0x00000020
 398 #define IRQ_EOF_SY_TX2          0x00000010
 399 #define IRQ_CHK_SY_TX2          0x00000008
 400 #define IRQ_EOB_AS_TX2          0x00000004
 401 #define IRQ_EOF_AS_TX2          0x00000002
 402 #define IRQ_CHK_AS_TX2          0x00000001
 403
 404 #define DRIVER_IRQS     (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \
 405                         IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \
 406                         IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2)
 407
 408 #define SPECIAL_IRQS    (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
 409                         IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
 410                         IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
 411                         IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \
 412                         IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \
 413                         IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
 414                         IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
 415                         IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
 416
 417 #define IRQ_MASK        (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \
 418                         IRQ_EOB_RX2 | IRQ_EOF_RX2 | \
 419                         IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \
 420                         IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \
 421                         IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \
 422                         IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \
 423                         IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
 424                         IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
 425                         IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
 426                         IRQ_MAC1 | \
 427                         IRQ_MAC2 | \
 428                         IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
 429                         IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
 430                         IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
 431
 432 #define IRQ_HWE_MASK    0x00000FFF /* enable all HW irqs */
 433
 434 typedef struct s_DevNet DEV_NET;
 435
 436 struct s_DevNet {
 437         int             PortNr;
 438         int             NetNr;
 439         int             Mtu;
 440         int             Up;
 441         SK_AC   *pAC;
 442 };
 443
 444 typedef struct s_TxPort         TX_PORT;
 445
 446 struct s_TxPort {
 447         /* the transmit descriptor rings */
 448         caddr_t         pTxDescrRing;   /* descriptor area memory */
 449         SK_U64          VTxDescrRing;   /* descr. area bus virt. addr. */
 450         TXD             *pTxdRingHead;  /* Head of Tx rings */
 451         TXD             *pTxdRingTail;  /* Tail of Tx rings */
 452         TXD             *pTxdRingPrev;  /* descriptor sent previously */
 453         int             TxdRingFree;    /* # of free entrys */
 454 #if 0
 455         spinlock_t      TxDesRingLock;  /* serialize descriptor accesses */
 456 #endif
 457         caddr_t         HwAddr;         /* bmu registers address */
 458         int             PortIndex;      /* index number of port (0 or 1) */
 459 };
 460
 461 typedef struct s_RxPort         RX_PORT;
 462
 463 struct s_RxPort {
 464         /* the receive descriptor rings */
 465         caddr_t         pRxDescrRing;   /* descriptor area memory */
 466         SK_U64          VRxDescrRing;   /* descr. area bus virt. addr. */
 467         RXD             *pRxdRingHead;  /* Head of Rx rings */
 468         RXD             *pRxdRingTail;  /* Tail of Rx rings */
 469         RXD             *pRxdRingPrev;  /* descriptor given to BMU previously */
 470         int             RxdRingFree;    /* # of free entrys */
 471 #if 0
 472         spinlock_t      RxDesRingLock;  /* serialize descriptor accesses */
 473 #endif
 474         int             RxFillLimit;    /* limit for buffers in ring */
 475         caddr_t         HwAddr;         /* bmu registers address */
 476         int             PortIndex;      /* index number of port (0 or 1) */
 477 };
 478
 479 typedef struct s_PerStrm        PER_STRM;
 480
 481 #define SK_ALLOC_IRQ    0x00000001
 482
 483 /****************************************************************************
 484  * Per board structure / Adapter Context structure:
 485  *      Allocated within attach(9e) and freed within detach(9e).
 486  *      Contains all 'per device' necessary handles, flags, locks etc.:
 487  */
 488 struct s_AC  {
 489         SK_GEINIT       GIni;           /* GE init struct */
 490         SK_PNMI         Pnmi;           /* PNMI data struct */
 491         SK_VPD          vpd;            /* vpd data struct */
 492         SK_QUEUE        Event;          /* Event queue */
 493         SK_HWT          Hwt;            /* Hardware Timer control struct */
 494         SK_TIMCTRL      Tim;            /* Software Timer control struct */
 495         SK_I2C          I2c;            /* I2C relevant data structure */
 496         SK_ADDR         Addr;           /* for Address module */
 497         SK_CSUM         Csum;           /* for checksum module */
 498         SK_RLMT         Rlmt;           /* for rlmt module */
 499 #if 0
 500         spinlock_t      SlowPathLock;   /* Normal IRQ lock */
 501 #endif
 502         SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
 503         int                     RlmtMode;       /* link check mode to set */
 504         int                     RlmtNets;       /* Number of nets */
 505
 506         SK_IOC          IoBase;         /* register set of adapter */
 507         int             BoardLevel;     /* level of active hw init (0-2) */
 508         char            DeviceStr[80];  /* adapter string from vpd */
 509         SK_U32          AllocFlag;      /* flag allocation of resources */
 510 #if 0
 511         struct pci_dev  *PciDev;        /* for access to pci config space */
 512         SK_U32          PciDevId;       /* pci device id */
 513 #else
 514         int             PciDev;
 515 #endif
 516         struct SK_NET_DEVICE    *dev[2];        /* pointer to device struct */
 517         char            Name[30];       /* driver name */
 518         struct SK_NET_DEVICE    *Next;          /* link all devices (for clearing) */
 519         int             RxBufSize;      /* length of receive buffers */
 520 #if 0
 521         struct net_device_stats stats;  /* linux 'netstat -i' statistics */
 522 #endif
 523         int             Index;          /* internal board index number */
 524
 525         /* adapter RAM sizes for queues of active port */
 526         int             RxQueueSize;    /* memory used for receive queue */
 527         int             TxSQueueSize;   /* memory used for sync. tx queue */
 528         int             TxAQueueSize;   /* memory used for async. tx queue */
 529
 530         int             PromiscCount;   /* promiscuous mode counter  */
 531         int             AllMultiCount;  /* allmulticast mode counter */
 532         int             MulticCount;    /* number of different MC    */
 533                                         /*  addresses for this board */
 534                                         /*  (may be more than HW can)*/
 535
 536         int             HWRevision;     /* Hardware revision */
 537         int             ActivePort;     /* the active XMAC port */
 538         int             MaxPorts;               /* number of activated ports */
 539         int             TxDescrPerRing; /* # of descriptors per tx ring */
 540         int             RxDescrPerRing; /* # of descriptors per rx ring */
 541
 542         caddr_t         pDescrMem;      /* Pointer to the descriptor area */
 543         dma_addr_t      pDescrMemDMA;   /* PCI DMA address of area */
 544
 545         /* the port structures with descriptor rings */
 546         TX_PORT         TxPort[SK_MAX_MACS][2];
 547         RX_PORT         RxPort[SK_MAX_MACS];
 548
 549         unsigned int    CsOfs1;         /* for checksum calculation */
 550         unsigned int    CsOfs2;         /* for checksum calculation */
 551         SK_U32          CsOfs;          /* for checksum calculation */
 552
 553         SK_BOOL         CheckQueue;     /* check event queue soon */
 554
 555         /* Only for tests */
 556         int             PortUp;
 557         int             PortDown;
 558
 559 };
 560
 561 #endif /* __INC_SKDRV2ND_H */