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[people/ms/u-boot.git] / drivers / net / smc91111.c
1 /*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
17 .
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
22 .
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 .
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
30 .
31 .
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
37 .
38 . Arguments:
39 . io = for the base address
40 . irq = for the IRQ
41 .
42 . author:
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
45 .
46 .
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
48 .
49 . Sources:
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
53 .
54 . History:
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
61
62 #include <common.h>
63 #include <command.h>
64 #include <config.h>
65 #include "smc91111.h"
66 #include <net.h>
67
68 /* Use power-down feature of the chip */
69 #define POWER_DOWN 0
70
71 #define NO_AUTOPROBE
72
73 #define SMC_DEBUG 0
74
75 #if SMC_DEBUG > 1
76 static const char version[] =
77 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
78 #endif
79
80 /* Autonegotiation timeout in seconds */
81 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
82 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
83 #endif
84
85 /*------------------------------------------------------------------------
86 .
87 . Configuration options, for the experienced user to change.
88 .
89 -------------------------------------------------------------------------*/
90
91 /*
92 . Wait time for memory to be free. This probably shouldn't be
93 . tuned that much, as waiting for this means nothing else happens
94 . in the system
95 */
96 #define MEMORY_WAIT_TIME 16
97
98
99 #if (SMC_DEBUG > 2 )
100 #define PRINTK3(args...) printf(args)
101 #else
102 #define PRINTK3(args...)
103 #endif
104
105 #if SMC_DEBUG > 1
106 #define PRINTK2(args...) printf(args)
107 #else
108 #define PRINTK2(args...)
109 #endif
110
111 #ifdef SMC_DEBUG
112 #define PRINTK(args...) printf(args)
113 #else
114 #define PRINTK(args...)
115 #endif
116
117
118 /*------------------------------------------------------------------------
119 .
120 . The internal workings of the driver. If you are changing anything
121 . here with the SMC stuff, you should have the datasheet and know
122 . what you are doing.
123 .
124 -------------------------------------------------------------------------*/
125 #define CARDNAME "LAN91C111"
126
127 /* Memory sizing constant */
128 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
129
130 #ifndef CONFIG_SMC91111_BASE
131 #define CONFIG_SMC91111_BASE 0x20000300
132 #endif
133
134 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
135
136 #define SMC_DEV_NAME "SMC91111"
137 #define SMC_PHY_ADDR 0x0000
138 #define SMC_ALLOC_MAX_TRY 5
139 #define SMC_TX_TIMEOUT 30
140
141 #define SMC_PHY_CLOCK_DELAY 1000
142
143 #define ETH_ZLEN 60
144
145 #ifdef CONFIG_SMC_USE_32_BIT
146 #define USE_32_BIT 1
147 #else
148 #undef USE_32_BIT
149 #endif
150 /*-----------------------------------------------------------------
151 .
152 . The driver can be entered at any of the following entry points.
153 .
154 .------------------------------------------------------------------ */
155
156 extern int eth_init(bd_t *bd);
157 extern void eth_halt(void);
158 extern int eth_rx(void);
159 extern int eth_send(volatile void *packet, int length);
160
161 #ifdef SHARED_RESOURCES
162 extern void swap_to(int device_id);
163 #endif
164
165 /*
166 . This is called by register_netdev(). It is responsible for
167 . checking the portlist for the SMC9000 series chipset. If it finds
168 . one, then it will initialize the device, find the hardware information,
169 . and sets up the appropriate device parameters.
170 . NOTE: Interrupts are *OFF* when this procedure is called.
171 .
172 . NB:This shouldn't be static since it is referred to externally.
173 */
174 int smc_init(void);
175
176 /*
177 . This is called by unregister_netdev(). It is responsible for
178 . cleaning up before the driver is finally unregistered and discarded.
179 */
180 void smc_destructor(void);
181
182 /*
183 . The kernel calls this function when someone wants to use the device,
184 . typically 'ifconfig ethX up'.
185 */
186 static int smc_open(bd_t *bd);
187
188
189 /*
190 . This is called by the kernel in response to 'ifconfig ethX down'. It
191 . is responsible for cleaning up everything that the open routine
192 . does, and maybe putting the card into a powerdown state.
193 */
194 static int smc_close(void);
195
196 /*
197 . Configures the PHY through the MII Management interface
198 */
199 #ifndef CONFIG_SMC91111_EXT_PHY
200 static void smc_phy_configure(void);
201 #endif /* !CONFIG_SMC91111_EXT_PHY */
202
203 /*
204 . This is a separate procedure to handle the receipt of a packet, to
205 . leave the interrupt code looking slightly cleaner
206 */
207 static int smc_rcv(void);
208
209 /* See if a MAC address is defined in the current environment. If so use it. If not
210 . print a warning and set the environment and other globals with the default.
211 . If an EEPROM is present it really should be consulted.
212 */
213 int smc_get_ethaddr(bd_t *bd);
214 int get_rom_mac(uchar *v_rom_mac);
215
216 /*
217 ------------------------------------------------------------
218 .
219 . Internal routines
220 .
221 ------------------------------------------------------------
222 */
223
224 #ifdef CONFIG_SMC_USE_IOFUNCS
225 /*
226 * input and output functions
227 *
228 * Implemented due to inx,outx macros accessing the device improperly
229 * and putting the device into an unkown state.
230 *
231 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
232 * could not be free'd (hence the alloc failures), duplicate packets,
233 * packets being corrupt (shifted) on the wire, etc. Switching to the
234 * inx,outx functions fixed this problem.
235 */
236 static inline word SMC_inw(dword offset);
237 static inline void SMC_outw(word value, dword offset);
238 static inline byte SMC_inb(dword offset);
239 static inline void SMC_outb(byte value, dword offset);
240 static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
241 static inline void SMC_outsw(dword offset, uchar* buf, dword len);
242
243 #define barrier() __asm__ __volatile__("": : :"memory")
244
245 static inline word SMC_inw(dword offset)
246 {
247 word v;
248 v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
249 barrier(); *(volatile u32*)(0xc0000000);
250 return v;
251 }
252
253 static inline void SMC_outw(word value, dword offset)
254 {
255 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
256 barrier(); *(volatile u32*)(0xc0000000);
257 }
258
259 static inline byte SMC_inb(dword offset)
260 {
261 word _w;
262
263 _w = SMC_inw(offset & ~((dword)1));
264 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
265 }
266
267 static inline void SMC_outb(byte value, dword offset)
268 {
269 word _w;
270
271 _w = SMC_inw(offset & ~((dword)1));
272 if (offset & 1)
273 *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
274 else
275 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
276 }
277
278 static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
279 {
280 volatile word *p = (volatile word *)buf;
281
282 while (len-- > 0) {
283 *p++ = SMC_inw(offset);
284 barrier();
285 *((volatile u32*)(0xc0000000));
286 }
287 }
288
289 static inline void SMC_outsw(dword offset, uchar* buf, dword len)
290 {
291 volatile word *p = (volatile word *)buf;
292
293 while (len-- > 0) {
294 SMC_outw(*p++, offset);
295 barrier();
296 *(volatile u32*)(0xc0000000);
297 }
298 }
299 #endif /* CONFIG_SMC_USE_IOFUNCS */
300
301 static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
302
303 /*
304 * This function must be called before smc_open() if you want to override
305 * the default mac address.
306 */
307
308 void smc_set_mac_addr(const unsigned char *addr) {
309 int i;
310
311 for (i=0; i < sizeof(smc_mac_addr); i++){
312 smc_mac_addr[i] = addr[i];
313 }
314 }
315
316 /*
317 * smc_get_macaddr is no longer used. If you want to override the default
318 * mac address, call smc_get_mac_addr as a part of the board initialization.
319 */
320
321 #if 0
322 void smc_get_macaddr( byte *addr ) {
323 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
324 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
325 int i;
326
327
328 for (i=0; i<6; i++) {
329 addr[0] = *(dnp1110_mac+0);
330 addr[1] = *(dnp1110_mac+1);
331 addr[2] = *(dnp1110_mac+2);
332 addr[3] = *(dnp1110_mac+3);
333 addr[4] = *(dnp1110_mac+4);
334 addr[5] = *(dnp1110_mac+5);
335 }
336 }
337 #endif /* 0 */
338
339 /***********************************************
340 * Show available memory *
341 ***********************************************/
342 void dump_memory_info(void)
343 {
344 word mem_info;
345 word old_bank;
346
347 old_bank = SMC_inw(BANK_SELECT)&0xF;
348
349 SMC_SELECT_BANK(0);
350 mem_info = SMC_inw( MIR_REG );
351 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
352
353 SMC_SELECT_BANK(old_bank);
354 }
355 /*
356 . A rather simple routine to print out a packet for debugging purposes.
357 */
358 #if SMC_DEBUG > 2
359 static void print_packet( byte *, int );
360 #endif
361
362 #define tx_done(dev) 1
363
364
365 /* this does a soft reset on the device */
366 static void smc_reset( void );
367
368 /* Enable Interrupts, Receive, and Transmit */
369 static void smc_enable( void );
370
371 /* this puts the device in an inactive state */
372 static void smc_shutdown( void );
373
374 /* Routines to Read and Write the PHY Registers across the
375 MII Management Interface
376 */
377
378 #ifndef CONFIG_SMC91111_EXT_PHY
379 static word smc_read_phy_register(byte phyreg);
380 static void smc_write_phy_register(byte phyreg, word phydata);
381 #endif /* !CONFIG_SMC91111_EXT_PHY */
382
383
384 static int poll4int (byte mask, int timeout)
385 {
386 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
387 int is_timeout = 0;
388 word old_bank = SMC_inw (BSR_REG);
389
390 PRINTK2 ("Polling...\n");
391 SMC_SELECT_BANK (2);
392 while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
393 if (get_timer (0) >= tmo) {
394 is_timeout = 1;
395 break;
396 }
397 }
398
399 /* restore old bank selection */
400 SMC_SELECT_BANK (old_bank);
401
402 if (is_timeout)
403 return 1;
404 else
405 return 0;
406 }
407
408 /* Only one release command at a time, please */
409 static inline void smc_wait_mmu_release_complete (void)
410 {
411 int count = 0;
412
413 /* assume bank 2 selected */
414 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
415 udelay (1); /* Wait until not busy */
416 if (++count > 200)
417 break;
418 }
419 }
420
421 /*
422 . Function: smc_reset( void )
423 . Purpose:
424 . This sets the SMC91111 chip to its normal state, hopefully from whatever
425 . mess that any other DOS driver has put it in.
426 .
427 . Maybe I should reset more registers to defaults in here? SOFTRST should
428 . do that for me.
429 .
430 . Method:
431 . 1. send a SOFT RESET
432 . 2. wait for it to finish
433 . 3. enable autorelease mode
434 . 4. reset the memory management unit
435 . 5. clear all interrupts
436 .
437 */
438 static void smc_reset (void)
439 {
440 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
441
442 /* This resets the registers mostly to defaults, but doesn't
443 affect EEPROM. That seems unnecessary */
444 SMC_SELECT_BANK (0);
445 SMC_outw (RCR_SOFTRST, RCR_REG);
446
447 /* Setup the Configuration Register */
448 /* This is necessary because the CONFIG_REG is not affected */
449 /* by a soft reset */
450
451 SMC_SELECT_BANK (1);
452 #if defined(CONFIG_SMC91111_EXT_PHY)
453 SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
454 #else
455 SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
456 #endif
457
458
459 /* Release from possible power-down state */
460 /* Configuration register is not affected by Soft Reset */
461 SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
462
463 SMC_SELECT_BANK (0);
464
465 /* this should pause enough for the chip to be happy */
466 udelay (10);
467
468 /* Disable transmit and receive functionality */
469 SMC_outw (RCR_CLEAR, RCR_REG);
470 SMC_outw (TCR_CLEAR, TCR_REG);
471
472 /* set the control register */
473 SMC_SELECT_BANK (1);
474 SMC_outw (CTL_DEFAULT, CTL_REG);
475
476 /* Reset the MMU */
477 SMC_SELECT_BANK (2);
478 smc_wait_mmu_release_complete ();
479 SMC_outw (MC_RESET, MMU_CMD_REG);
480 while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
481 udelay (1); /* Wait until not busy */
482
483 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
484 but this is a place where future chipsets _COULD_ break. Be wary
485 of issuing another MMU command right after this */
486
487 /* Disable all interrupts */
488 SMC_outb (0, IM_REG);
489 }
490
491 /*
492 . Function: smc_enable
493 . Purpose: let the chip talk to the outside work
494 . Method:
495 . 1. Enable the transmitter
496 . 2. Enable the receiver
497 . 3. Enable interrupts
498 */
499 static void smc_enable()
500 {
501 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
502 SMC_SELECT_BANK( 0 );
503 /* see the header file for options in TCR/RCR DEFAULT*/
504 SMC_outw( TCR_DEFAULT, TCR_REG );
505 SMC_outw( RCR_DEFAULT, RCR_REG );
506
507 /* clear MII_DIS */
508 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
509 }
510
511 /*
512 . Function: smc_shutdown
513 . Purpose: closes down the SMC91xxx chip.
514 . Method:
515 . 1. zero the interrupt mask
516 . 2. clear the enable receive flag
517 . 3. clear the enable xmit flags
518 .
519 . TODO:
520 . (1) maybe utilize power down mode.
521 . Why not yet? Because while the chip will go into power down mode,
522 . the manual says that it will wake up in response to any I/O requests
523 . in the register space. Empirical results do not show this working.
524 */
525 static void smc_shutdown()
526 {
527 PRINTK2(CARDNAME ": smc_shutdown\n");
528
529 /* no more interrupts for me */
530 SMC_SELECT_BANK( 2 );
531 SMC_outb( 0, IM_REG );
532
533 /* and tell the card to stay away from that nasty outside world */
534 SMC_SELECT_BANK( 0 );
535 SMC_outb( RCR_CLEAR, RCR_REG );
536 SMC_outb( TCR_CLEAR, TCR_REG );
537 #ifdef SHARED_RESOURCES
538 swap_to(FLASH);
539 #endif
540 }
541
542
543 /*
544 . Function: smc_hardware_send_packet(struct net_device * )
545 . Purpose:
546 . This sends the actual packet to the SMC9xxx chip.
547 .
548 . Algorithm:
549 . First, see if a saved_skb is available.
550 . ( this should NOT be called if there is no 'saved_skb'
551 . Now, find the packet number that the chip allocated
552 . Point the data pointers at it in memory
553 . Set the length word in the chip's memory
554 . Dump the packet to chip memory
555 . Check if a last byte is needed ( odd length packet )
556 . if so, set the control flag right
557 . Tell the card to send it
558 . Enable the transmit interrupt, so I know if it failed
559 . Free the kernel data if I actually sent it.
560 */
561 static int smc_send_packet (volatile void *packet, int packet_length)
562 {
563 byte packet_no;
564 unsigned long ioaddr;
565 byte *buf;
566 int length;
567 int numPages;
568 int try = 0;
569 int time_out;
570 byte status;
571 byte saved_pnr;
572 word saved_ptr;
573
574 /* save PTR and PNR registers before manipulation */
575 SMC_SELECT_BANK (2);
576 saved_pnr = SMC_inb( PN_REG );
577 saved_ptr = SMC_inw( PTR_REG );
578
579 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
580
581 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
582
583 /* allocate memory
584 ** The MMU wants the number of pages to be the number of 256 bytes
585 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
586 **
587 ** The 91C111 ignores the size bits, but the code is left intact
588 ** for backwards and future compatibility.
589 **
590 ** Pkt size for allocating is data length +6 (for additional status
591 ** words, length and ctl!)
592 **
593 ** If odd size then last byte is included in this header.
594 */
595 numPages = ((length & 0xfffe) + 6);
596 numPages >>= 8; /* Divide by 256 */
597
598 if (numPages > 7) {
599 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
600 return 0;
601 }
602
603 /* now, try to allocate the memory */
604 SMC_SELECT_BANK (2);
605 SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
606
607 /* FIXME: the ALLOC_INT bit never gets set *
608 * so the following will always give a *
609 * memory allocation error. *
610 * same code works in armboot though *
611 * -ro
612 */
613
614 again:
615 try++;
616 time_out = MEMORY_WAIT_TIME;
617 do {
618 status = SMC_inb (SMC91111_INT_REG);
619 if (status & IM_ALLOC_INT) {
620 /* acknowledge the interrupt */
621 SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
622 break;
623 }
624 } while (--time_out);
625
626 if (!time_out) {
627 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
628 SMC_DEV_NAME, try);
629 if (try < SMC_ALLOC_MAX_TRY)
630 goto again;
631 else
632 return 0;
633 }
634
635 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
636 SMC_DEV_NAME, try);
637
638 /* I can send the packet now.. */
639
640 ioaddr = SMC_BASE_ADDRESS;
641
642 buf = (byte *) packet;
643
644 /* If I get here, I _know_ there is a packet slot waiting for me */
645 packet_no = SMC_inb (AR_REG);
646 if (packet_no & AR_FAILED) {
647 /* or isn't there? BAD CHIP! */
648 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
649 return 0;
650 }
651
652 /* we have a packet address, so tell the card to use it */
653 #ifndef CONFIG_XAENIAX
654 SMC_outb (packet_no, PN_REG);
655 #else
656 /* On Xaeniax board, we can't use SMC_outb here because that way
657 * the Allocate MMU command will end up written to the command register
658 * as well, which will lead to a problem.
659 */
660 SMC_outl (packet_no << 16, 0);
661 #endif
662 /* do not write new ptr value if Write data fifo not empty */
663 while ( saved_ptr & PTR_NOTEMPTY )
664 printf ("Write data fifo not empty!\n");
665
666 /* point to the beginning of the packet */
667 SMC_outw (PTR_AUTOINC, PTR_REG);
668
669 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
670 SMC_DEV_NAME, length);
671
672 #if SMC_DEBUG > 2
673 printf ("Transmitting Packet\n");
674 print_packet (buf, length);
675 #endif
676
677 /* send the packet length ( +6 for status, length and ctl byte )
678 and the status word ( set to zeros ) */
679 #ifdef USE_32_BIT
680 SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
681 #else
682 SMC_outw (0, SMC91111_DATA_REG);
683 /* send the packet length ( +6 for status words, length, and ctl */
684 SMC_outw ((length + 6), SMC91111_DATA_REG);
685 #endif
686
687 /* send the actual data
688 . I _think_ it's faster to send the longs first, and then
689 . mop up by sending the last word. It depends heavily
690 . on alignment, at least on the 486. Maybe it would be
691 . a good idea to check which is optimal? But that could take
692 . almost as much time as is saved?
693 */
694 #ifdef USE_32_BIT
695 SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
696 #ifndef CONFIG_XAENIAX
697 if (length & 0x2)
698 SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
699 SMC91111_DATA_REG);
700 #else
701 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
702 * unaligned tail part specially. The standard code doesn't work.
703 */
704 if ((length & 3) == 3) {
705 u16 * ptr = (u16*) &buf[length-3];
706 SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16),
707 SMC91111_DATA_REG);
708 } else if ((length & 2) == 2) {
709 u16 * ptr = (u16*) &buf[length-2];
710 SMC_outl(*ptr, SMC91111_DATA_REG);
711 } else if (length & 1) {
712 SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG);
713 } else {
714 SMC_outl(0, SMC91111_DATA_REG);
715 }
716 #endif
717 #else
718 SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
719 #endif /* USE_32_BIT */
720
721 #ifndef CONFIG_XAENIAX
722 /* Send the last byte, if there is one. */
723 if ((length & 1) == 0) {
724 SMC_outw (0, SMC91111_DATA_REG);
725 } else {
726 SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
727 }
728 #endif
729
730 /* and let the chipset deal with it */
731 SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
732
733 /* poll for TX INT */
734 /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
735 /* poll for TX_EMPTY INT - autorelease enabled */
736 if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
737 /* sending failed */
738 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
739
740 /* release packet */
741 /* no need to release, MMU does that now */
742 #ifdef CONFIG_XAENIAX
743 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
744 #endif
745
746 /* wait for MMU getting ready (low) */
747 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
748 udelay (10);
749 }
750
751 PRINTK2 ("MMU ready\n");
752
753
754 return 0;
755 } else {
756 /* ack. int */
757 SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
758 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
759 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
760 length);
761
762 /* release packet */
763 /* no need to release, MMU does that now */
764 #ifdef CONFIG_XAENIAX
765 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
766 #endif
767
768 /* wait for MMU getting ready (low) */
769 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
770 udelay (10);
771 }
772
773 PRINTK2 ("MMU ready\n");
774
775
776 }
777
778 /* restore previously saved registers */
779 #ifndef CONFIG_XAENIAX
780 SMC_outb( saved_pnr, PN_REG );
781 #else
782 /* On Xaeniax board, we can't use SMC_outb here because that way
783 * the Allocate MMU command will end up written to the command register
784 * as well, which will lead to a problem.
785 */
786 SMC_outl(saved_pnr << 16, 0);
787 #endif
788 SMC_outw( saved_ptr, PTR_REG );
789
790 return length;
791 }
792
793 /*-------------------------------------------------------------------------
794 |
795 | smc_destructor( struct net_device * dev )
796 | Input parameters:
797 | dev, pointer to the device structure
798 |
799 | Output:
800 | None.
801 |
802 ---------------------------------------------------------------------------
803 */
804 void smc_destructor()
805 {
806 PRINTK2(CARDNAME ": smc_destructor\n");
807 }
808
809
810 /*
811 * Open and Initialize the board
812 *
813 * Set up everything, reset the card, etc ..
814 *
815 */
816 static int smc_open (bd_t * bd)
817 {
818 int i, err;
819
820 PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
821
822 /* reset the hardware */
823 smc_reset ();
824 smc_enable ();
825
826 /* Configure the PHY */
827 #ifndef CONFIG_SMC91111_EXT_PHY
828 smc_phy_configure ();
829 #endif
830
831 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
832 /* SMC_SELECT_BANK(0); */
833 /* SMC_outw(0, RPC_REG); */
834 SMC_SELECT_BANK (1);
835
836 err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
837 if (err < 0)
838 return -1;
839 #ifdef USE_32_BIT
840 for (i = 0; i < 6; i += 2) {
841 word address;
842
843 address = smc_mac_addr[i + 1] << 8;
844 address |= smc_mac_addr[i];
845 SMC_outw (address, (ADDR0_REG + i));
846 }
847 #else
848 for (i = 0; i < 6; i++)
849 SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
850 #endif
851
852 return 0;
853 }
854
855 /*-------------------------------------------------------------
856 .
857 . smc_rcv - receive a packet from the card
858 .
859 . There is ( at least ) a packet waiting to be read from
860 . chip-memory.
861 .
862 . o Read the status
863 . o If an error, record it
864 . o otherwise, read in the packet
865 --------------------------------------------------------------
866 */
867 static int smc_rcv()
868 {
869 int packet_number;
870 word status;
871 word packet_length;
872 int is_error = 0;
873 #ifdef USE_32_BIT
874 dword stat_len;
875 #endif
876 byte saved_pnr;
877 word saved_ptr;
878
879 SMC_SELECT_BANK(2);
880 /* save PTR and PTR registers */
881 saved_pnr = SMC_inb( PN_REG );
882 saved_ptr = SMC_inw( PTR_REG );
883
884 packet_number = SMC_inw( RXFIFO_REG );
885
886 if ( packet_number & RXFIFO_REMPTY ) {
887
888 return 0;
889 }
890
891 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
892 /* start reading from the start of the packet */
893 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
894
895 /* First two words are status and packet_length */
896 #ifdef USE_32_BIT
897 stat_len = SMC_inl(SMC91111_DATA_REG);
898 status = stat_len & 0xffff;
899 packet_length = stat_len >> 16;
900 #else
901 status = SMC_inw( SMC91111_DATA_REG );
902 packet_length = SMC_inw( SMC91111_DATA_REG );
903 #endif
904
905 packet_length &= 0x07ff; /* mask off top bits */
906
907 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
908
909 if ( !(status & RS_ERRORS ) ){
910 /* Adjust for having already read the first two words */
911 packet_length -= 4; /*4; */
912
913
914 /* set odd length for bug in LAN91C111, */
915 /* which never sets RS_ODDFRAME */
916 /* TODO ? */
917
918
919 #ifdef USE_32_BIT
920 PRINTK3(" Reading %d dwords (and %d bytes) \n",
921 packet_length >> 2, packet_length & 3 );
922 /* QUESTION: Like in the TX routine, do I want
923 to send the DWORDs or the bytes first, or some
924 mixture. A mixture might improve already slow PIO
925 performance */
926 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
927 /* read the left over bytes */
928 if (packet_length & 3) {
929 int i;
930
931 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
932 dword leftover = SMC_inl(SMC91111_DATA_REG);
933 for (i=0; i<(packet_length & 3); i++)
934 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
935 }
936 #else
937 PRINTK3(" Reading %d words and %d byte(s) \n",
938 (packet_length >> 1 ), packet_length & 1 );
939 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
940
941 #endif /* USE_32_BIT */
942
943 #if SMC_DEBUG > 2
944 printf("Receiving Packet\n");
945 print_packet( NetRxPackets[0], packet_length );
946 #endif
947 } else {
948 /* error ... */
949 /* TODO ? */
950 is_error = 1;
951 }
952
953 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
954 udelay(1); /* Wait until not busy */
955
956 /* error or good, tell the card to get rid of this packet */
957 SMC_outw( MC_RELEASE, MMU_CMD_REG );
958
959 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
960 udelay(1); /* Wait until not busy */
961
962 /* restore saved registers */
963 #ifndef CONFIG_XAENIAX
964 SMC_outb( saved_pnr, PN_REG );
965 #else
966 /* On Xaeniax board, we can't use SMC_outb here because that way
967 * the Allocate MMU command will end up written to the command register
968 * as well, which will lead to a problem.
969 */
970 SMC_outl( saved_pnr << 16, 0);
971 #endif
972 SMC_outw( saved_ptr, PTR_REG );
973
974 if (!is_error) {
975 /* Pass the packet up to the protocol layers. */
976 NetReceive(NetRxPackets[0], packet_length);
977 return packet_length;
978 } else {
979 return 0;
980 }
981
982 }
983
984
985 /*----------------------------------------------------
986 . smc_close
987 .
988 . this makes the board clean up everything that it can
989 . and not talk to the outside world. Caused by
990 . an 'ifconfig ethX down'
991 .
992 -----------------------------------------------------*/
993 static int smc_close()
994 {
995 PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
996
997 /* clear everything */
998 smc_shutdown();
999
1000 return 0;
1001 }
1002
1003
1004 #if 0
1005 /*------------------------------------------------------------
1006 . Modify a bit in the LAN91C111 register set
1007 .-------------------------------------------------------------*/
1008 static word smc_modify_regbit(int bank, int ioaddr, int reg,
1009 unsigned int bit, int val)
1010 {
1011 word regval;
1012
1013 SMC_SELECT_BANK( bank );
1014
1015 regval = SMC_inw( reg );
1016 if (val)
1017 regval |= bit;
1018 else
1019 regval &= ~bit;
1020
1021 SMC_outw( regval, 0 );
1022 return(regval);
1023 }
1024
1025
1026 /*------------------------------------------------------------
1027 . Retrieve a bit in the LAN91C111 register set
1028 .-------------------------------------------------------------*/
1029 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
1030 {
1031 SMC_SELECT_BANK( bank );
1032 if ( SMC_inw( reg ) & bit)
1033 return(1);
1034 else
1035 return(0);
1036 }
1037
1038
1039 /*------------------------------------------------------------
1040 . Modify a LAN91C111 register (word access only)
1041 .-------------------------------------------------------------*/
1042 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
1043 {
1044 SMC_SELECT_BANK( bank );
1045 SMC_outw( val, reg );
1046 }
1047
1048
1049 /*------------------------------------------------------------
1050 . Retrieve a LAN91C111 register (word access only)
1051 .-------------------------------------------------------------*/
1052 static int smc_get_reg(int bank, int ioaddr, int reg)
1053 {
1054 SMC_SELECT_BANK( bank );
1055 return(SMC_inw( reg ));
1056 }
1057
1058 #endif /* 0 */
1059
1060 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
1061
1062 #if (SMC_DEBUG > 2 )
1063
1064 /*------------------------------------------------------------
1065 . Debugging function for viewing MII Management serial bitstream
1066 .-------------------------------------------------------------*/
1067 static void smc_dump_mii_stream (byte * bits, int size)
1068 {
1069 int i;
1070
1071 printf ("BIT#:");
1072 for (i = 0; i < size; ++i) {
1073 printf ("%d", i % 10);
1074 }
1075
1076 printf ("\nMDOE:");
1077 for (i = 0; i < size; ++i) {
1078 if (bits[i] & MII_MDOE)
1079 printf ("1");
1080 else
1081 printf ("0");
1082 }
1083
1084 printf ("\nMDO :");
1085 for (i = 0; i < size; ++i) {
1086 if (bits[i] & MII_MDO)
1087 printf ("1");
1088 else
1089 printf ("0");
1090 }
1091
1092 printf ("\nMDI :");
1093 for (i = 0; i < size; ++i) {
1094 if (bits[i] & MII_MDI)
1095 printf ("1");
1096 else
1097 printf ("0");
1098 }
1099
1100 printf ("\n");
1101 }
1102 #endif
1103
1104 /*------------------------------------------------------------
1105 . Reads a register from the MII Management serial interface
1106 .-------------------------------------------------------------*/
1107 #ifndef CONFIG_SMC91111_EXT_PHY
1108 static word smc_read_phy_register (byte phyreg)
1109 {
1110 int oldBank;
1111 int i;
1112 byte mask;
1113 word mii_reg;
1114 byte bits[64];
1115 int clk_idx = 0;
1116 int input_idx;
1117 word phydata;
1118 byte phyaddr = SMC_PHY_ADDR;
1119
1120 /* 32 consecutive ones on MDO to establish sync */
1121 for (i = 0; i < 32; ++i)
1122 bits[clk_idx++] = MII_MDOE | MII_MDO;
1123
1124 /* Start code <01> */
1125 bits[clk_idx++] = MII_MDOE;
1126 bits[clk_idx++] = MII_MDOE | MII_MDO;
1127
1128 /* Read command <10> */
1129 bits[clk_idx++] = MII_MDOE | MII_MDO;
1130 bits[clk_idx++] = MII_MDOE;
1131
1132 /* Output the PHY address, msb first */
1133 mask = (byte) 0x10;
1134 for (i = 0; i < 5; ++i) {
1135 if (phyaddr & mask)
1136 bits[clk_idx++] = MII_MDOE | MII_MDO;
1137 else
1138 bits[clk_idx++] = MII_MDOE;
1139
1140 /* Shift to next lowest bit */
1141 mask >>= 1;
1142 }
1143
1144 /* Output the phy register number, msb first */
1145 mask = (byte) 0x10;
1146 for (i = 0; i < 5; ++i) {
1147 if (phyreg & mask)
1148 bits[clk_idx++] = MII_MDOE | MII_MDO;
1149 else
1150 bits[clk_idx++] = MII_MDOE;
1151
1152 /* Shift to next lowest bit */
1153 mask >>= 1;
1154 }
1155
1156 /* Tristate and turnaround (2 bit times) */
1157 bits[clk_idx++] = 0;
1158 /*bits[clk_idx++] = 0; */
1159
1160 /* Input starts at this bit time */
1161 input_idx = clk_idx;
1162
1163 /* Will input 16 bits */
1164 for (i = 0; i < 16; ++i)
1165 bits[clk_idx++] = 0;
1166
1167 /* Final clock bit */
1168 bits[clk_idx++] = 0;
1169
1170 /* Save the current bank */
1171 oldBank = SMC_inw (BANK_SELECT);
1172
1173 /* Select bank 3 */
1174 SMC_SELECT_BANK (3);
1175
1176 /* Get the current MII register value */
1177 mii_reg = SMC_inw (MII_REG);
1178
1179 /* Turn off all MII Interface bits */
1180 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1181
1182 /* Clock all 64 cycles */
1183 for (i = 0; i < sizeof bits; ++i) {
1184 /* Clock Low - output data */
1185 SMC_outw (mii_reg | bits[i], MII_REG);
1186 udelay (SMC_PHY_CLOCK_DELAY);
1187
1188
1189 /* Clock Hi - input data */
1190 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1191 udelay (SMC_PHY_CLOCK_DELAY);
1192 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1193 }
1194
1195 /* Return to idle state */
1196 /* Set clock to low, data to low, and output tristated */
1197 SMC_outw (mii_reg, MII_REG);
1198 udelay (SMC_PHY_CLOCK_DELAY);
1199
1200 /* Restore original bank select */
1201 SMC_SELECT_BANK (oldBank);
1202
1203 /* Recover input data */
1204 phydata = 0;
1205 for (i = 0; i < 16; ++i) {
1206 phydata <<= 1;
1207
1208 if (bits[input_idx++] & MII_MDI)
1209 phydata |= 0x0001;
1210 }
1211
1212 #if (SMC_DEBUG > 2 )
1213 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1214 phyaddr, phyreg, phydata);
1215 smc_dump_mii_stream (bits, sizeof bits);
1216 #endif
1217
1218 return (phydata);
1219 }
1220
1221
1222 /*------------------------------------------------------------
1223 . Writes a register to the MII Management serial interface
1224 .-------------------------------------------------------------*/
1225 static void smc_write_phy_register (byte phyreg, word phydata)
1226 {
1227 int oldBank;
1228 int i;
1229 word mask;
1230 word mii_reg;
1231 byte bits[65];
1232 int clk_idx = 0;
1233 byte phyaddr = SMC_PHY_ADDR;
1234
1235 /* 32 consecutive ones on MDO to establish sync */
1236 for (i = 0; i < 32; ++i)
1237 bits[clk_idx++] = MII_MDOE | MII_MDO;
1238
1239 /* Start code <01> */
1240 bits[clk_idx++] = MII_MDOE;
1241 bits[clk_idx++] = MII_MDOE | MII_MDO;
1242
1243 /* Write command <01> */
1244 bits[clk_idx++] = MII_MDOE;
1245 bits[clk_idx++] = MII_MDOE | MII_MDO;
1246
1247 /* Output the PHY address, msb first */
1248 mask = (byte) 0x10;
1249 for (i = 0; i < 5; ++i) {
1250 if (phyaddr & mask)
1251 bits[clk_idx++] = MII_MDOE | MII_MDO;
1252 else
1253 bits[clk_idx++] = MII_MDOE;
1254
1255 /* Shift to next lowest bit */
1256 mask >>= 1;
1257 }
1258
1259 /* Output the phy register number, msb first */
1260 mask = (byte) 0x10;
1261 for (i = 0; i < 5; ++i) {
1262 if (phyreg & mask)
1263 bits[clk_idx++] = MII_MDOE | MII_MDO;
1264 else
1265 bits[clk_idx++] = MII_MDOE;
1266
1267 /* Shift to next lowest bit */
1268 mask >>= 1;
1269 }
1270
1271 /* Tristate and turnaround (2 bit times) */
1272 bits[clk_idx++] = 0;
1273 bits[clk_idx++] = 0;
1274
1275 /* Write out 16 bits of data, msb first */
1276 mask = 0x8000;
1277 for (i = 0; i < 16; ++i) {
1278 if (phydata & mask)
1279 bits[clk_idx++] = MII_MDOE | MII_MDO;
1280 else
1281 bits[clk_idx++] = MII_MDOE;
1282
1283 /* Shift to next lowest bit */
1284 mask >>= 1;
1285 }
1286
1287 /* Final clock bit (tristate) */
1288 bits[clk_idx++] = 0;
1289
1290 /* Save the current bank */
1291 oldBank = SMC_inw (BANK_SELECT);
1292
1293 /* Select bank 3 */
1294 SMC_SELECT_BANK (3);
1295
1296 /* Get the current MII register value */
1297 mii_reg = SMC_inw (MII_REG);
1298
1299 /* Turn off all MII Interface bits */
1300 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1301
1302 /* Clock all cycles */
1303 for (i = 0; i < sizeof bits; ++i) {
1304 /* Clock Low - output data */
1305 SMC_outw (mii_reg | bits[i], MII_REG);
1306 udelay (SMC_PHY_CLOCK_DELAY);
1307
1308
1309 /* Clock Hi - input data */
1310 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1311 udelay (SMC_PHY_CLOCK_DELAY);
1312 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1313 }
1314
1315 /* Return to idle state */
1316 /* Set clock to low, data to low, and output tristated */
1317 SMC_outw (mii_reg, MII_REG);
1318 udelay (SMC_PHY_CLOCK_DELAY);
1319
1320 /* Restore original bank select */
1321 SMC_SELECT_BANK (oldBank);
1322
1323 #if (SMC_DEBUG > 2 )
1324 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1325 phyaddr, phyreg, phydata);
1326 smc_dump_mii_stream (bits, sizeof bits);
1327 #endif
1328 }
1329 #endif /* !CONFIG_SMC91111_EXT_PHY */
1330
1331
1332 /*------------------------------------------------------------
1333 . Waits the specified number of milliseconds - kernel friendly
1334 .-------------------------------------------------------------*/
1335 #ifndef CONFIG_SMC91111_EXT_PHY
1336 static void smc_wait_ms(unsigned int ms)
1337 {
1338 udelay(ms*1000);
1339 }
1340 #endif /* !CONFIG_SMC91111_EXT_PHY */
1341
1342
1343 /*------------------------------------------------------------
1344 . Configures the specified PHY using Autonegotiation. Calls
1345 . smc_phy_fixed() if the user has requested a certain config.
1346 .-------------------------------------------------------------*/
1347 #ifndef CONFIG_SMC91111_EXT_PHY
1348 static void smc_phy_configure ()
1349 {
1350 int timeout;
1351 byte phyaddr;
1352 word my_phy_caps; /* My PHY capabilities */
1353 word my_ad_caps; /* My Advertised capabilities */
1354 word status = 0; /*;my status = 0 */
1355 int failed = 0;
1356
1357 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1358
1359
1360 /* Get the detected phy address */
1361 phyaddr = SMC_PHY_ADDR;
1362
1363 /* Reset the PHY, setting all other bits to zero */
1364 smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
1365
1366 /* Wait for the reset to complete, or time out */
1367 timeout = 6; /* Wait up to 3 seconds */
1368 while (timeout--) {
1369 if (!(smc_read_phy_register (PHY_CNTL_REG)
1370 & PHY_CNTL_RST)) {
1371 /* reset complete */
1372 break;
1373 }
1374
1375 smc_wait_ms (500); /* wait 500 millisecs */
1376 }
1377
1378 if (timeout < 1) {
1379 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1380 goto smc_phy_configure_exit;
1381 }
1382
1383 /* Read PHY Register 18, Status Output */
1384 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1385
1386 /* Enable PHY Interrupts (for register 18) */
1387 /* Interrupts listed here are disabled */
1388 smc_write_phy_register (PHY_MASK_REG, 0xffff);
1389
1390 /* Configure the Receive/Phy Control register */
1391 SMC_SELECT_BANK (0);
1392 SMC_outw (RPC_DEFAULT, RPC_REG);
1393
1394 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1395 my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
1396 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1397
1398 if (my_phy_caps & PHY_STAT_CAP_T4)
1399 my_ad_caps |= PHY_AD_T4;
1400
1401 if (my_phy_caps & PHY_STAT_CAP_TXF)
1402 my_ad_caps |= PHY_AD_TX_FDX;
1403
1404 if (my_phy_caps & PHY_STAT_CAP_TXH)
1405 my_ad_caps |= PHY_AD_TX_HDX;
1406
1407 if (my_phy_caps & PHY_STAT_CAP_TF)
1408 my_ad_caps |= PHY_AD_10_FDX;
1409
1410 if (my_phy_caps & PHY_STAT_CAP_TH)
1411 my_ad_caps |= PHY_AD_10_HDX;
1412
1413 /* Update our Auto-Neg Advertisement Register */
1414 smc_write_phy_register (PHY_AD_REG, my_ad_caps);
1415
1416 /* Read the register back. Without this, it appears that when */
1417 /* auto-negotiation is restarted, sometimes it isn't ready and */
1418 /* the link does not come up. */
1419 smc_read_phy_register(PHY_AD_REG);
1420
1421 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1422 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1423
1424 /* Restart auto-negotiation process in order to advertise my caps */
1425 smc_write_phy_register (PHY_CNTL_REG,
1426 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1427
1428 /* Wait for the auto-negotiation to complete. This may take from */
1429 /* 2 to 3 seconds. */
1430 /* Wait for the reset to complete, or time out */
1431 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1432 while (timeout--) {
1433
1434 status = smc_read_phy_register (PHY_STAT_REG);
1435 if (status & PHY_STAT_ANEG_ACK) {
1436 /* auto-negotiate complete */
1437 break;
1438 }
1439
1440 smc_wait_ms (500); /* wait 500 millisecs */
1441
1442 /* Restart auto-negotiation if remote fault */
1443 if (status & PHY_STAT_REM_FLT) {
1444 printf ("%s: PHY remote fault detected\n",
1445 SMC_DEV_NAME);
1446
1447 /* Restart auto-negotiation */
1448 printf ("%s: PHY restarting auto-negotiation\n",
1449 SMC_DEV_NAME);
1450 smc_write_phy_register (PHY_CNTL_REG,
1451 PHY_CNTL_ANEG_EN |
1452 PHY_CNTL_ANEG_RST |
1453 PHY_CNTL_SPEED |
1454 PHY_CNTL_DPLX);
1455 }
1456 }
1457
1458 if (timeout < 1) {
1459 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1460 failed = 1;
1461 }
1462
1463 /* Fail if we detected an auto-negotiate remote fault */
1464 if (status & PHY_STAT_REM_FLT) {
1465 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1466 failed = 1;
1467 }
1468
1469 /* Re-Configure the Receive/Phy Control register */
1470 SMC_outw (RPC_DEFAULT, RPC_REG);
1471
1472 smc_phy_configure_exit: ;
1473
1474 }
1475 #endif /* !CONFIG_SMC91111_EXT_PHY */
1476
1477
1478 #if SMC_DEBUG > 2
1479 static void print_packet( byte * buf, int length )
1480 {
1481 int i;
1482 int remainder;
1483 int lines;
1484
1485 printf("Packet of length %d \n", length );
1486
1487 #if SMC_DEBUG > 3
1488 lines = length / 16;
1489 remainder = length % 16;
1490
1491 for ( i = 0; i < lines ; i ++ ) {
1492 int cur;
1493
1494 for ( cur = 0; cur < 8; cur ++ ) {
1495 byte a, b;
1496
1497 a = *(buf ++ );
1498 b = *(buf ++ );
1499 printf("%02x%02x ", a, b );
1500 }
1501 printf("\n");
1502 }
1503 for ( i = 0; i < remainder/2 ; i++ ) {
1504 byte a, b;
1505
1506 a = *(buf ++ );
1507 b = *(buf ++ );
1508 printf("%02x%02x ", a, b );
1509 }
1510 printf("\n");
1511 #endif
1512 }
1513 #endif
1514
1515 int eth_init(bd_t *bd) {
1516 #ifdef SHARED_RESOURCES
1517 swap_to(ETHERNET);
1518 #endif
1519 return (smc_open(bd));
1520 }
1521
1522 void eth_halt() {
1523 smc_close();
1524 }
1525
1526 int eth_rx() {
1527 return smc_rcv();
1528 }
1529
1530 int eth_send(volatile void *packet, int length) {
1531 return smc_send_packet(packet, length);
1532 }
1533
1534 int smc_get_ethaddr (bd_t * bd)
1535 {
1536 uchar v_mac[6];
1537
1538 if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
1539 /* get ROM mac value if any */
1540 if (!get_rom_mac(v_mac)) {
1541 printf("\n*** ERROR: ethaddr is NOT set !!\n");
1542 return -1;
1543 }
1544 eth_setenv_enetaddr("ethaddr", v_mac);
1545 }
1546
1547 smc_set_mac_addr(v_mac); /* use old function to update smc default */
1548 PRINTK("Using MAC Address %pM\n", v_mac);
1549 return 0;
1550 }
1551
1552 int get_rom_mac (uchar *v_rom_mac)
1553 {
1554 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1555 char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1556
1557 memcpy (v_rom_mac, hw_mac_addr, 6);
1558 return (1);
1559 #else
1560 int i;
1561 int valid_mac = 0;
1562
1563 SMC_SELECT_BANK (1);
1564 for (i=0; i<6; i++)
1565 {
1566 v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
1567 valid_mac |= v_rom_mac[i];
1568 }
1569
1570 return (valid_mac ? 1 : 0);
1571 #endif
1572 }
"Das U-Boot" Source Tree