drivers/net/sun8i_emac.c

   1 /*
   2  * (C) Copyright 2016
   3  * Author: Amit Singh Tomar, amittomer25@gmail.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Ethernet driver for H3/A64/A83T based SoC's
   8  *
   9  * It is derived from the work done by
  10  * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  11  *
  12 */
  13
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/gpio.h>
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <fdt_support.h>
  20 #include <linux/err.h>
  21 #include <malloc.h>
  22 #include <miiphy.h>
  23 #include <net.h>
  24
  25 #define SCTL_EMAC_TX_CLK_SRC_MII        BIT(0)
  26 #define SCTL_EMAC_EPIT_MII              BIT(2)
  27 #define SCTL_EMAC_CLK_SEL               BIT(18) /* 25 Mhz */
  28
  29 #define MDIO_CMD_MII_BUSY               BIT(0)
  30 #define MDIO_CMD_MII_WRITE              BIT(1)
  31
  32 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK  0x000001f0
  33 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  34 #define MDIO_CMD_MII_PHY_ADDR_MASK      0x0001f000
  35 #define MDIO_CMD_MII_PHY_ADDR_SHIFT     12
  36
  37 #define CONFIG_TX_DESCR_NUM     32
  38 #define CONFIG_RX_DESCR_NUM     32
  39 #define CONFIG_ETH_BUFSIZE      2024
  40
  41 #define TX_TOTAL_BUFSIZE        (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  42 #define RX_TOTAL_BUFSIZE        (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  43
  44 #define H3_EPHY_DEFAULT_VALUE   0x58000
  45 #define H3_EPHY_DEFAULT_MASK    GENMASK(31, 15)
  46 #define H3_EPHY_ADDR_SHIFT      20
  47 #define REG_PHY_ADDR_MASK       GENMASK(4, 0)
  48 #define H3_EPHY_LED_POL         BIT(17) /* 1: active low, 0: active high */
  49 #define H3_EPHY_SHUTDOWN        BIT(16) /* 1: shutdown, 0: power up */
  50 #define H3_EPHY_SELECT          BIT(15) /* 1: internal PHY, 0: external PHY */
  51
  52 #define SC_RMII_EN              BIT(13)
  53 #define SC_EPIT                 BIT(2) /* 1: RGMII, 0: MII */
  54 #define SC_ETCS_MASK            GENMASK(1, 0)
  55 #define SC_ETCS_EXT_GMII        0x1
  56 #define SC_ETCS_INT_GMII        0x2
  57
  58 #define CONFIG_MDIO_TIMEOUT     (3 * CONFIG_SYS_HZ)
  59
  60 #define AHB_GATE_OFFSET_EPHY    0
  61
  62 #if defined(CONFIG_MACH_SUN8I_H3)
  63 #define SUN8I_GPD8_GMAC         2
  64 #else
  65 #define SUN8I_GPD8_GMAC         4
  66 #endif
  67
  68 /* H3/A64 EMAC Register's offset */
  69 #define EMAC_CTL0               0x00
  70 #define EMAC_CTL1               0x04
  71 #define EMAC_INT_STA            0x08
  72 #define EMAC_INT_EN             0x0c
  73 #define EMAC_TX_CTL0            0x10
  74 #define EMAC_TX_CTL1            0x14
  75 #define EMAC_TX_FLOW_CTL        0x1c
  76 #define EMAC_TX_DMA_DESC        0x20
  77 #define EMAC_RX_CTL0            0x24
  78 #define EMAC_RX_CTL1            0x28
  79 #define EMAC_RX_DMA_DESC        0x34
  80 #define EMAC_MII_CMD            0x48
  81 #define EMAC_MII_DATA           0x4c
  82 #define EMAC_ADDR0_HIGH         0x50
  83 #define EMAC_ADDR0_LOW          0x54
  84 #define EMAC_TX_DMA_STA         0xb0
  85 #define EMAC_TX_CUR_DESC        0xb4
  86 #define EMAC_TX_CUR_BUF         0xb8
  87 #define EMAC_RX_DMA_STA         0xc0
  88 #define EMAC_RX_CUR_DESC        0xc4
  89
  90 DECLARE_GLOBAL_DATA_PTR;
  91
  92 enum emac_variant {
  93         A83T_EMAC = 1,
  94         H3_EMAC,
  95         A64_EMAC,
  96 };
  97
  98 struct emac_dma_desc {
  99         u32 status;
 100         u32 st;
 101         u32 buf_addr;
 102         u32 next;
 103 } __aligned(ARCH_DMA_MINALIGN);
 104
 105 struct emac_eth_dev {
 106         struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
 107         struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
 108         char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 109         char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 110
 111         u32 interface;
 112         u32 phyaddr;
 113         u32 link;
 114         u32 speed;
 115         u32 duplex;
 116         u32 phy_configured;
 117         u32 tx_currdescnum;
 118         u32 rx_currdescnum;
 119         u32 addr;
 120         u32 tx_slot;
 121         bool use_internal_phy;
 122
 123         enum emac_variant variant;
 124         void *mac_reg;
 125         phys_addr_t sysctl_reg;
 126         struct phy_device *phydev;
 127         struct mii_dev *bus;
 128 };
 129
 130 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 131 {
 132         struct emac_eth_dev *priv = bus->priv;
 133         ulong start;
 134         u32 miiaddr = 0;
 135         int timeout = CONFIG_MDIO_TIMEOUT;
 136
 137         miiaddr &= ~MDIO_CMD_MII_WRITE;
 138         miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 139         miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
 140                 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 141
 142         miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
 143
 144         miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
 145                 MDIO_CMD_MII_PHY_ADDR_MASK;
 146
 147         miiaddr |= MDIO_CMD_MII_BUSY;
 148
 149         writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
 150
 151         start = get_timer(0);
 152         while (get_timer(start) < timeout) {
 153                 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
 154                         return readl(priv->mac_reg + EMAC_MII_DATA);
 155                 udelay(10);
 156         };
 157
 158         return -1;
 159 }
 160
 161 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 162                             u16 val)
 163 {
 164         struct emac_eth_dev *priv = bus->priv;
 165         ulong start;
 166         u32 miiaddr = 0;
 167         int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
 168
 169         miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 170         miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
 171                 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 172
 173         miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
 174         miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
 175                 MDIO_CMD_MII_PHY_ADDR_MASK;
 176
 177         miiaddr |= MDIO_CMD_MII_WRITE;
 178         miiaddr |= MDIO_CMD_MII_BUSY;
 179
 180         writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
 181         writel(val, priv->mac_reg + EMAC_MII_DATA);
 182
 183         start = get_timer(0);
 184         while (get_timer(start) < timeout) {
 185                 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
 186                                         MDIO_CMD_MII_BUSY)) {
 187                         ret = 0;
 188                         break;
 189                 }
 190                 udelay(10);
 191         };
 192
 193         return ret;
 194 }
 195
 196 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
 197 {
 198         u32 macid_lo, macid_hi;
 199
 200         macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
 201                 (mac_id[3] << 24);
 202         macid_hi = mac_id[4] + (mac_id[5] << 8);
 203
 204         writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
 205         writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
 206
 207         return 0;
 208 }
 209
 210 static void sun8i_adjust_link(struct emac_eth_dev *priv,
 211                               struct phy_device *phydev)
 212 {
 213         u32 v;
 214
 215         v = readl(priv->mac_reg + EMAC_CTL0);
 216
 217         if (phydev->duplex)
 218                 v |= BIT(0);
 219         else
 220                 v &= ~BIT(0);
 221
 222         v &= ~0x0C;
 223
 224         switch (phydev->speed) {
 225         case 1000:
 226                 break;
 227         case 100:
 228                 v |= BIT(2);
 229                 v |= BIT(3);
 230                 break;
 231         case 10:
 232                 v |= BIT(3);
 233                 break;
 234         }
 235         writel(v, priv->mac_reg + EMAC_CTL0);
 236 }
 237
 238 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
 239 {
 240         if (priv->use_internal_phy) {
 241                 /* H3 based SoC's that has an Internal 100MBit PHY
 242                  * needs to be configured and powered up before use
 243                 */
 244                 *reg &= ~H3_EPHY_DEFAULT_MASK;
 245                 *reg |=  H3_EPHY_DEFAULT_VALUE;
 246                 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
 247                 *reg &= ~H3_EPHY_SHUTDOWN;
 248                 *reg |= H3_EPHY_SELECT;
 249         } else
 250                 /* This is to select External Gigabit PHY on
 251                  * the boards with H3 SoC.
 252                 */
 253                 *reg &= ~H3_EPHY_SELECT;
 254
 255         return 0;
 256 }
 257
 258 static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
 259 {
 260         int ret;
 261         u32 reg;
 262
 263         reg = readl(priv->sysctl_reg);
 264
 265         if (priv->variant == H3_EMAC) {
 266                 ret = sun8i_emac_set_syscon_ephy(priv, &reg);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         reg &= ~(SC_ETCS_MASK | SC_EPIT);
 272         if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
 273                 reg &= ~SC_RMII_EN;
 274
 275         switch (priv->interface) {
 276         case PHY_INTERFACE_MODE_MII:
 277                 /* default */
 278                 break;
 279         case PHY_INTERFACE_MODE_RGMII:
 280                 reg |= SC_EPIT | SC_ETCS_INT_GMII;
 281                 break;
 282         case PHY_INTERFACE_MODE_RMII:
 283                 if (priv->variant == H3_EMAC ||
 284                     priv->variant == A64_EMAC) {
 285                         reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
 286                 break;
 287                 }
 288                 /* RMII not supported on A83T */
 289         default:
 290                 debug("%s: Invalid PHY interface\n", __func__);
 291                 return -EINVAL;
 292         }
 293
 294         writel(reg, priv->sysctl_reg);
 295
 296         return 0;
 297 }
 298
 299 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
 300 {
 301         struct phy_device *phydev;
 302
 303         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 304         if (!phydev)
 305                 return -ENODEV;
 306
 307         phy_connect_dev(phydev, dev);
 308
 309         priv->phydev = phydev;
 310         phy_config(priv->phydev);
 311
 312         return 0;
 313 }
 314
 315 static void rx_descs_init(struct emac_eth_dev *priv)
 316 {
 317         struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
 318         char *rxbuffs = &priv->rxbuffer[0];
 319         struct emac_dma_desc *desc_p;
 320         u32 idx;
 321
 322         /* flush Rx buffers */
 323         flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
 324                         RX_TOTAL_BUFSIZE);
 325
 326         for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
 327                 desc_p = &desc_table_p[idx];
 328                 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
 329                         ;
 330                 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
 331                 desc_p->st |= CONFIG_ETH_BUFSIZE;
 332                 desc_p->status = BIT(31);
 333         }
 334
 335         /* Correcting the last pointer of the chain */
 336         desc_p->next = (uintptr_t)&desc_table_p[0];
 337
 338         flush_dcache_range((uintptr_t)priv->rx_chain,
 339                            (uintptr_t)priv->rx_chain +
 340                         sizeof(priv->rx_chain));
 341
 342         writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
 343         priv->rx_currdescnum = 0;
 344 }
 345
 346 static void tx_descs_init(struct emac_eth_dev *priv)
 347 {
 348         struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
 349         char *txbuffs = &priv->txbuffer[0];
 350         struct emac_dma_desc *desc_p;
 351         u32 idx;
 352
 353         for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
 354                 desc_p = &desc_table_p[idx];
 355                 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
 356                         ;
 357                 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
 358                 desc_p->status = (1 << 31);
 359                 desc_p->st = 0;
 360         }
 361
 362         /* Correcting the last pointer of the chain */
 363         desc_p->next =  (uintptr_t)&desc_table_p[0];
 364
 365         /* Flush all Tx buffer descriptors */
 366         flush_dcache_range((uintptr_t)priv->tx_chain,
 367                            (uintptr_t)priv->tx_chain +
 368                         sizeof(priv->tx_chain));
 369
 370         writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
 371         priv->tx_currdescnum = 0;
 372 }
 373
 374 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 375 {
 376         u32 reg, v;
 377         int timeout = 100;
 378
 379         reg = readl((priv->mac_reg + EMAC_CTL1));
 380
 381         if (!(reg & 0x1)) {
 382                 /* Soft reset MAC */
 383                 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
 384                 do {
 385                         reg = readl(priv->mac_reg + EMAC_CTL1);
 386                 } while ((reg & 0x01) != 0 &&  (--timeout));
 387                 if (!timeout) {
 388                         printf("%s: Timeout\n", __func__);
 389                         return -1;
 390                 }
 391         }
 392
 393         /* Rewrite mac address after reset */
 394         _sun8i_write_hwaddr(priv, enetaddr);
 395
 396         v = readl(priv->mac_reg + EMAC_TX_CTL1);
 397         /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
 398         v |= BIT(1);
 399         writel(v, priv->mac_reg + EMAC_TX_CTL1);
 400
 401         v = readl(priv->mac_reg + EMAC_RX_CTL1);
 402         /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
 403          * complete frame has been written to RX DMA FIFO
 404          */
 405         v |= BIT(1);
 406         writel(v, priv->mac_reg + EMAC_RX_CTL1);
 407
 408         /* DMA */
 409         writel(8 << 24, priv->mac_reg + EMAC_CTL1);
 410
 411         /* Initialize rx/tx descriptors */
 412         rx_descs_init(priv);
 413         tx_descs_init(priv);
 414
 415         /* PHY Start Up */
 416         genphy_parse_link(priv->phydev);
 417
 418         sun8i_adjust_link(priv, priv->phydev);
 419
 420         /* Start RX DMA */
 421         v = readl(priv->mac_reg + EMAC_RX_CTL1);
 422         v |= BIT(30);
 423         writel(v, priv->mac_reg + EMAC_RX_CTL1);
 424         /* Start TX DMA */
 425         v = readl(priv->mac_reg + EMAC_TX_CTL1);
 426         v |= BIT(30);
 427         writel(v, priv->mac_reg + EMAC_TX_CTL1);
 428
 429         /* Enable RX/TX */
 430         setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
 431         setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
 432
 433         return 0;
 434 }
 435
 436 static int parse_phy_pins(struct udevice *dev)
 437 {
 438         int offset;
 439         const char *pin_name;
 440         int drive, pull, i;
 441
 442         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 443                                        "pinctrl-0");
 444         if (offset < 0) {
 445                 printf("WARNING: emac: cannot find pinctrl-0 node\n");
 446                 return offset;
 447         }
 448
 449         drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
 450                                              "allwinner,drive", 4);
 451         pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
 452                                             "allwinner,pull", 0);
 453         for (i = 0; ; i++) {
 454                 int pin;
 455
 456                 if (fdt_get_string_index(gd->fdt_blob, offset,
 457                                          "allwinner,pins", i, &pin_name))
 458                         break;
 459                 if (pin_name[0] != 'P')
 460                         continue;
 461                 pin = (pin_name[1] - 'A') << 5;
 462                 if (pin >= 26 << 5)
 463                         continue;
 464                 pin += simple_strtol(&pin_name[2], NULL, 10);
 465
 466                 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
 467                 sunxi_gpio_set_drv(pin, drive);
 468                 sunxi_gpio_set_pull(pin, pull);
 469         }
 470
 471         if (!i) {
 472                 printf("WARNING: emac: cannot find allwinner,pins property\n");
 473                 return -2;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
 480 {
 481         u32 status, desc_num = priv->rx_currdescnum;
 482         struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
 483         int length = -EAGAIN;
 484         int good_packet = 1;
 485         uintptr_t desc_start = (uintptr_t)desc_p;
 486         uintptr_t desc_end = desc_start +
 487                 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
 488
 489         ulong data_start = (uintptr_t)desc_p->buf_addr;
 490         ulong data_end;
 491
 492         /* Invalidate entire buffer descriptor */
 493         invalidate_dcache_range(desc_start, desc_end);
 494
 495         status = desc_p->status;
 496
 497         /* Check for DMA own bit */
 498         if (!(status & BIT(31))) {
 499                 length = (desc_p->status >> 16) & 0x3FFF;
 500
 501                 if (length < 0x40) {
 502                         good_packet = 0;
 503                         debug("RX: Bad Packet (runt)\n");
 504                 }
 505
 506                 data_end = data_start + length;
 507                 /* Invalidate received data */
 508                 invalidate_dcache_range(rounddown(data_start,
 509                                                   ARCH_DMA_MINALIGN),
 510                                         roundup(data_end,
 511                                                 ARCH_DMA_MINALIGN));
 512                 if (good_packet) {
 513                         if (length > CONFIG_ETH_BUFSIZE) {
 514                                 printf("Received packet is too big (len=%d)\n",
 515                                        length);
 516                                 return -EMSGSIZE;
 517                         }
 518                         *packetp = (uchar *)(ulong)desc_p->buf_addr;
 519                         return length;
 520                 }
 521         }
 522
 523         return length;
 524 }
 525
 526 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
 527                                 int len)
 528 {
 529         u32 v, desc_num = priv->tx_currdescnum;
 530         struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
 531         uintptr_t desc_start = (uintptr_t)desc_p;
 532         uintptr_t desc_end = desc_start +
 533                 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
 534
 535         uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
 536         uintptr_t data_end = data_start +
 537                 roundup(len, ARCH_DMA_MINALIGN);
 538
 539         /* Invalidate entire buffer descriptor */
 540         invalidate_dcache_range(desc_start, desc_end);
 541
 542         desc_p->st = len;
 543         /* Mandatory undocumented bit */
 544         desc_p->st |= BIT(24);
 545
 546         memcpy((void *)data_start, packet, len);
 547
 548         /* Flush data to be sent */
 549         flush_dcache_range(data_start, data_end);
 550
 551         /* frame end */
 552         desc_p->st |= BIT(30);
 553         desc_p->st |= BIT(31);
 554
 555         /*frame begin */
 556         desc_p->st |= BIT(29);
 557         desc_p->status = BIT(31);
 558
 559         /*Descriptors st and status field has changed, so FLUSH it */
 560         flush_dcache_range(desc_start, desc_end);
 561
 562         /* Move to next Descriptor and wrap around */
 563         if (++desc_num >= CONFIG_TX_DESCR_NUM)
 564                 desc_num = 0;
 565         priv->tx_currdescnum = desc_num;
 566
 567         /* Start the DMA */
 568         v = readl(priv->mac_reg + EMAC_TX_CTL1);
 569         v |= BIT(31);/* mandatory */
 570         v |= BIT(30);/* mandatory */
 571         writel(v, priv->mac_reg + EMAC_TX_CTL1);
 572
 573         return 0;
 574 }
 575
 576 static int sun8i_eth_write_hwaddr(struct udevice *dev)
 577 {
 578         struct eth_pdata *pdata = dev_get_platdata(dev);
 579         struct emac_eth_dev *priv = dev_get_priv(dev);
 580
 581         return _sun8i_write_hwaddr(priv, pdata->enetaddr);
 582 }
 583
 584 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 585 {
 586         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 587
 588         if (priv->use_internal_phy) {
 589                 /* Set clock gating for ephy */
 590                 setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
 591
 592                 /* Set Tx clock source as MII with rate 25 MZ */
 593                 setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
 594                                 SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
 595                 /* Deassert EPHY */
 596                 setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
 597         }
 598
 599         /* Set clock gating for emac */
 600         setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
 601
 602         /* Set EMAC clock */
 603         setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
 604
 605         /* De-assert EMAC */
 606         setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
 607 }
 608
 609 static int sun8i_mdio_init(const char *name, struct  emac_eth_dev *priv)
 610 {
 611         struct mii_dev *bus = mdio_alloc();
 612
 613         if (!bus) {
 614                 debug("Failed to allocate MDIO bus\n");
 615                 return -ENOMEM;
 616         }
 617
 618         bus->read = sun8i_mdio_read;
 619         bus->write = sun8i_mdio_write;
 620         snprintf(bus->name, sizeof(bus->name), name);
 621         bus->priv = (void *)priv;
 622
 623         return  mdio_register(bus);
 624 }
 625
 626 static int sun8i_emac_eth_start(struct udevice *dev)
 627 {
 628         struct eth_pdata *pdata = dev_get_platdata(dev);
 629
 630         return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
 631 }
 632
 633 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
 634 {
 635         struct emac_eth_dev *priv = dev_get_priv(dev);
 636
 637         return _sun8i_emac_eth_send(priv, packet, length);
 638 }
 639
 640 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 641 {
 642         struct emac_eth_dev *priv = dev_get_priv(dev);
 643
 644         return _sun8i_eth_recv(priv, packetp);
 645 }
 646
 647 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
 648 {
 649         u32 desc_num = priv->rx_currdescnum;
 650         struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
 651         uintptr_t desc_start = (uintptr_t)desc_p;
 652         uintptr_t desc_end = desc_start +
 653                 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
 654
 655         /* Make the current descriptor valid again */
 656         desc_p->status |= BIT(31);
 657
 658         /* Flush Status field of descriptor */
 659         flush_dcache_range(desc_start, desc_end);
 660
 661         /* Move to next desc and wrap-around condition. */
 662         if (++desc_num >= CONFIG_RX_DESCR_NUM)
 663                 desc_num = 0;
 664         priv->rx_currdescnum = desc_num;
 665
 666         return 0;
 667 }
 668
 669 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
 670                               int length)
 671 {
 672         struct emac_eth_dev *priv = dev_get_priv(dev);
 673
 674         return _sun8i_free_pkt(priv);
 675 }
 676
 677 static void sun8i_emac_eth_stop(struct udevice *dev)
 678 {
 679         struct emac_eth_dev *priv = dev_get_priv(dev);
 680
 681         /* Stop Rx/Tx transmitter */
 682         clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
 683         clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
 684
 685         /* Stop TX DMA */
 686         clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
 687
 688         phy_shutdown(priv->phydev);
 689 }
 690
 691 static int sun8i_emac_eth_probe(struct udevice *dev)
 692 {
 693         struct eth_pdata *pdata = dev_get_platdata(dev);
 694         struct emac_eth_dev *priv = dev_get_priv(dev);
 695
 696         priv->mac_reg = (void *)pdata->iobase;
 697
 698         sun8i_emac_board_setup(priv);
 699
 700         sun8i_mdio_init(dev->name, priv);
 701         priv->bus = miiphy_get_dev_by_name(dev->name);
 702
 703         sun8i_emac_set_syscon(priv);
 704
 705         return sun8i_phy_init(priv, dev);
 706 }
 707
 708 static const struct eth_ops sun8i_emac_eth_ops = {
 709         .start                  = sun8i_emac_eth_start,
 710         .write_hwaddr           = sun8i_eth_write_hwaddr,
 711         .send                   = sun8i_emac_eth_send,
 712         .recv                   = sun8i_emac_eth_recv,
 713         .free_pkt               = sun8i_eth_free_pkt,
 714         .stop                   = sun8i_emac_eth_stop,
 715 };
 716
 717 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 718 {
 719         struct eth_pdata *pdata = dev_get_platdata(dev);
 720         struct emac_eth_dev *priv = dev_get_priv(dev);
 721         const char *phy_mode;
 722         int offset = 0;
 723
 724         pdata->iobase = dev_get_addr_name(dev, "emac");
 725         priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
 726
 727         pdata->phy_interface = -1;
 728         priv->phyaddr = -1;
 729         priv->use_internal_phy = false;
 730
 731         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 732                                        "phy");
 733         if (offset > 0)
 734                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
 735                                                -1);
 736
 737         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 738
 739         if (phy_mode)
 740                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 741         printf("phy interface%d\n", pdata->phy_interface);
 742
 743         if (pdata->phy_interface == -1) {
 744                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 745                 return -EINVAL;
 746         }
 747
 748         priv->variant = dev_get_driver_data(dev);
 749
 750         if (!priv->variant) {
 751                 printf("%s: Missing variant '%s'\n", __func__,
 752                        (char *)priv->variant);
 753                 return -EINVAL;
 754         }
 755
 756         if (priv->variant == H3_EMAC) {
 757                 if (fdt_getprop(gd->fdt_blob, dev->of_offset,
 758                                 "allwinner,use-internal-phy", NULL))
 759                         priv->use_internal_phy = true;
 760         }
 761
 762         priv->interface = pdata->phy_interface;
 763
 764         if (!priv->use_internal_phy)
 765                 parse_phy_pins(dev);
 766
 767         return 0;
 768 }
 769
 770 static const struct udevice_id sun8i_emac_eth_ids[] = {
 771         {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
 772         {.compatible = "allwinner,sun50i-a64-emac",
 773                 .data = (uintptr_t)A64_EMAC },
 774         {.compatible = "allwinner,sun8i-a83t-emac",
 775                 .data = (uintptr_t)A83T_EMAC },
 776         { }
 777 };
 778
 779 U_BOOT_DRIVER(eth_sun8i_emac) = {
 780         .name   = "eth_sun8i_emac",
 781         .id     = UCLASS_ETH,
 782         .of_match = sun8i_emac_eth_ids,
 783         .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
 784         .probe  = sun8i_emac_eth_probe,
 785         .ops    = &sun8i_emac_eth_ops,
 786         .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
 787         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 788         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 789 };