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[people/ms/u-boot.git] / drivers / net / uli526x.c
1 /*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
5 *
6 * Description:
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
9 *
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 #include <common.h>
17 #include <malloc.h>
18 #include <net.h>
19 #include <netdev.h>
20 #include <asm/io.h>
21 #include <pci.h>
22 #include <miiphy.h>
23
24 /* some kernel function compatible define */
25
26 #undef DEBUG
27
28 /* Board/System/Debug information/definition */
29 #define ULI_VENDOR_ID 0x10B9
30 #define ULI5261_DEVICE_ID 0x5261
31 #define ULI5263_DEVICE_ID 0x5263
32 /* ULi M5261 ID*/
33 #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
34 /* ULi M5263 ID*/
35 #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
36
37 #define ULI526X_IO_SIZE 0x100
38 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
39 #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
40 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
41 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
42 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
43 #define TX_BUF_ALLOC 0x300
44 #define RX_ALLOC_SIZE PKTSIZE
45 #define ULI526X_RESET 1
46 #define CR0_DEFAULT 0
47 #define CR6_DEFAULT 0x22200000
48 #define CR7_DEFAULT 0x180c1
49 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
50 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
51 #define MAX_PACKET_SIZE 1514
52 #define ULI5261_MAX_MULTICAST 14
53 #define RX_COPY_SIZE 100
54 #define MAX_CHECK_PACKET 0x8000
55
56 #define ULI526X_10MHF 0
57 #define ULI526X_100MHF 1
58 #define ULI526X_10MFD 4
59 #define ULI526X_100MFD 5
60 #define ULI526X_AUTO 8
61
62 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
63 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
64 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
65 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
66 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
67 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
68
69 /* CR9 definition: SROM/MII */
70 #define CR9_SROM_READ 0x4800
71 #define CR9_SRCS 0x1
72 #define CR9_SRCLK 0x2
73 #define CR9_CRDOUT 0x8
74 #define SROM_DATA_0 0x0
75 #define SROM_DATA_1 0x4
76 #define PHY_DATA_1 0x20000
77 #define PHY_DATA_0 0x00000
78 #define MDCLKH 0x10000
79
80 #define PHY_POWER_DOWN 0x800
81
82 #define SROM_V41_CODE 0x14
83
84 #define SROM_CLK_WRITE(data, ioaddr) do { \
85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
86 udelay(5); \
87 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
88 udelay(5); \
89 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
90 udelay(5); \
91 } while (0)
92
93 /* Structure/enum declaration */
94
95 struct tx_desc {
96 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
97 char *tx_buf_ptr; /* Data for us */
98 struct tx_desc *next_tx_desc;
99 };
100
101 struct rx_desc {
102 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
103 char *rx_buf_ptr; /* Data for us */
104 struct rx_desc *next_rx_desc;
105 };
106
107 struct uli526x_board_info {
108 u32 chip_id; /* Chip vendor/Device ID */
109 pci_dev_t pdev;
110
111 long ioaddr; /* I/O base address */
112 u32 cr0_data;
113 u32 cr5_data;
114 u32 cr6_data;
115 u32 cr7_data;
116 u32 cr15_data;
117
118 /* pointer for memory physical address */
119 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
120 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
121 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
122 dma_addr_t first_tx_desc_dma;
123 dma_addr_t first_rx_desc_dma;
124
125 /* descriptor pointer */
126 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
127 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
128 unsigned char *desc_pool_ptr; /* descriptor pool memory */
129 struct tx_desc *first_tx_desc;
130 struct tx_desc *tx_insert_ptr;
131 struct tx_desc *tx_remove_ptr;
132 struct rx_desc *first_rx_desc;
133 struct rx_desc *rx_ready_ptr; /* packet come pointer */
134 unsigned long tx_packet_cnt; /* transmitted packet count */
135
136 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
137
138 u8 media_mode; /* user specify media mode */
139 u8 op_mode; /* real work dedia mode */
140 u8 phy_addr;
141
142 /* NIC SROM data */
143 unsigned char srom[128];
144 };
145
146 enum uli526x_offsets {
147 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
148 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
149 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
150 DCR15 = 0x78
151 };
152
153 enum uli526x_CR6_bits {
154 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
155 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
156 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
157 };
158
159 /* Global variable declaration -- */
160
161 static unsigned char uli526x_media_mode = ULI526X_AUTO;
162
163 static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
164 __attribute__ ((aligned(32)));
165 static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
166
167 /* For module input parameter */
168 static int mode = 8;
169
170 /* function declaration -- */
171 static int uli526x_start_xmit(struct eth_device *dev,
172 volatile void *packet, int length);
173 static const struct ethtool_ops netdev_ethtool_ops;
174 static u16 read_srom_word(long, int);
175 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
176 static void allocate_rx_buffer(struct uli526x_board_info *);
177 static void update_cr6(u32, unsigned long);
178 static u16 phy_read(unsigned long, u8, u8, u32);
179 static u16 phy_readby_cr10(unsigned long, u8, u8);
180 static void phy_write(unsigned long, u8, u8, u16, u32);
181 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
182 static void phy_write_1bit(unsigned long, u32, u32);
183 static u16 phy_read_1bit(unsigned long, u32);
184 static int uli526x_rx_packet(struct eth_device *);
185 static void uli526x_free_tx_pkt(struct eth_device *,
186 struct uli526x_board_info *);
187 static void uli526x_reuse_buf(struct rx_desc *);
188 static void uli526x_init(struct eth_device *);
189 static void uli526x_set_phyxcer(struct uli526x_board_info *);
190
191
192 static int uli526x_init_one(struct eth_device *, bd_t *);
193 static void uli526x_disable(struct eth_device *);
194 static void set_mac_addr(struct eth_device *);
195
196 static struct pci_device_id uli526x_pci_tbl[] = {
197 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
198 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
199 {}
200 };
201
202 /* ULI526X network board routine */
203
204 /*
205 * Search ULI526X board, register it
206 */
207
208 int uli526x_initialize(bd_t *bis)
209 {
210 pci_dev_t devno;
211 int card_number = 0;
212 struct eth_device *dev;
213 struct uli526x_board_info *db; /* board information structure */
214
215 u32 iobase;
216 int idx = 0;
217
218 while (1) {
219 /* Find PCI device */
220 devno = pci_find_devices(uli526x_pci_tbl, idx++);
221 if (devno < 0)
222 break;
223
224 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
225 iobase &= ~0xf;
226
227 dev = (struct eth_device *)malloc(sizeof *dev);
228 sprintf(dev->name, "uli526x#%d", card_number);
229 db = (struct uli526x_board_info *)
230 malloc(sizeof(struct uli526x_board_info));
231
232 dev->priv = db;
233 db->pdev = devno;
234 dev->iobase = iobase;
235
236 dev->init = uli526x_init_one;
237 dev->halt = uli526x_disable;
238 dev->send = uli526x_start_xmit;
239 dev->recv = uli526x_rx_packet;
240
241 /* init db */
242 db->ioaddr = dev->iobase;
243 /* get chip id */
244
245 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
246 #ifdef DEBUG
247 printf("uli526x: uli526x @0x%x\n", iobase);
248 printf("uli526x: chip_id%x\n", db->chip_id);
249 #endif
250 eth_register(dev);
251 card_number++;
252 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
253 udelay(10 * 1000);
254 }
255 return card_number;
256 }
257
258 static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
259 {
260
261 struct uli526x_board_info *db = dev->priv;
262 int i;
263
264 switch (mode) {
265 case ULI526X_10MHF:
266 case ULI526X_100MHF:
267 case ULI526X_10MFD:
268 case ULI526X_100MFD:
269 uli526x_media_mode = mode;
270 break;
271 default:
272 uli526x_media_mode = ULI526X_AUTO;
273 break;
274 }
275
276 /* Allocate Tx/Rx descriptor memory */
277 db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
278 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
279 if (db->desc_pool_ptr == NULL)
280 return -1;
281
282 db->buf_pool_ptr = (uchar *)&buf_pool[0];
283 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
284 if (db->buf_pool_ptr == NULL)
285 return -1;
286
287 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
288 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
289
290 db->buf_pool_start = db->buf_pool_ptr;
291 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
292
293 #ifdef DEBUG
294 printf("%s(): db->ioaddr= 0x%x\n",
295 __FUNCTION__, db->ioaddr);
296 printf("%s(): media_mode= 0x%x\n",
297 __FUNCTION__, uli526x_media_mode);
298 printf("%s(): db->desc_pool_ptr= 0x%x\n",
299 __FUNCTION__, db->desc_pool_ptr);
300 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
301 __FUNCTION__, db->desc_pool_dma_ptr);
302 printf("%s(): db->buf_pool_ptr= 0x%x\n",
303 __FUNCTION__, db->buf_pool_ptr);
304 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
305 __FUNCTION__, db->buf_pool_dma_ptr);
306 #endif
307
308 /* read 64 word srom data */
309 for (i = 0; i < 64; i++)
310 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
311 i));
312
313 /* Set Node address */
314 if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
315 /* SROM absent, so write MAC address to ID Table */
316 set_mac_addr(dev);
317 else { /*Exist SROM*/
318 for (i = 0; i < 6; i++)
319 dev->enetaddr[i] = db->srom[20 + i];
320 }
321 #ifdef DEBUG
322 for (i = 0; i < 6; i++)
323 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
324 #endif
325 db->PHY_reg4 = 0x1e0;
326
327 /* system variable init */
328 db->cr6_data = CR6_DEFAULT ;
329 db->cr6_data |= ULI526X_TXTH_256;
330 db->cr0_data = CR0_DEFAULT;
331 uli526x_init(dev);
332 return 0;
333 }
334
335 static void uli526x_disable(struct eth_device *dev)
336 {
337 #ifdef DEBUG
338 printf("uli526x_disable\n");
339 #endif
340 struct uli526x_board_info *db = dev->priv;
341
342 if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
343 /* Reset & stop ULI526X board */
344 outl(ULI526X_RESET, db->ioaddr + DCR0);
345 udelay(5);
346 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
347
348 /* reset the board */
349 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
350 update_cr6(db->cr6_data, dev->iobase);
351 outl(0, dev->iobase + DCR7); /* Disable Interrupt */
352 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
353 }
354 }
355
356 /* Initialize ULI526X board
357 * Reset ULI526X board
358 * Initialize TX/Rx descriptor chain structure
359 * Send the set-up frame
360 * Enable Tx/Rx machine
361 */
362
363 static void uli526x_init(struct eth_device *dev)
364 {
365
366 struct uli526x_board_info *db = dev->priv;
367 u8 phy_tmp;
368 u16 phy_value;
369 u16 phy_reg_reset;
370
371 /* Reset M526x MAC controller */
372 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
373 udelay(100);
374 outl(db->cr0_data, db->ioaddr + DCR0);
375 udelay(5);
376
377 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
378 db->phy_addr = 1;
379 db->tx_packet_cnt = 0;
380 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
381 /* peer add */
382 phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
383 if (phy_value != 0xffff && phy_value != 0) {
384 db->phy_addr = phy_tmp;
385 break;
386 }
387 }
388
389 #ifdef DEBUG
390 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
391 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
392 #endif
393 if (phy_tmp == 32)
394 printf("Can not find the phy address!!!");
395
396 /* Parser SROM and media mode */
397 db->media_mode = uli526x_media_mode;
398
399 if (!(inl(db->ioaddr + DCR12) & 0x8)) {
400 /* Phyxcer capability setting */
401 phy_reg_reset = phy_read(db->ioaddr,
402 db->phy_addr, 0, db->chip_id);
403 phy_reg_reset = (phy_reg_reset | 0x8000);
404 phy_write(db->ioaddr, db->phy_addr, 0,
405 phy_reg_reset, db->chip_id);
406 udelay(500);
407
408 /* Process Phyxcer Media Mode */
409 uli526x_set_phyxcer(db);
410 }
411 /* Media Mode Process */
412 if (!(db->media_mode & ULI526X_AUTO))
413 db->op_mode = db->media_mode; /* Force Mode */
414
415 /* Initialize Transmit/Receive decriptor and CR3/4 */
416 uli526x_descriptor_init(db, db->ioaddr);
417
418 /* Init CR6 to program M526X operation */
419 update_cr6(db->cr6_data, db->ioaddr);
420
421 /* Init CR7, interrupt active bit */
422 db->cr7_data = CR7_DEFAULT;
423 outl(db->cr7_data, db->ioaddr + DCR7);
424
425 /* Init CR15, Tx jabber and Rx watchdog timer */
426 outl(db->cr15_data, db->ioaddr + DCR15);
427
428 /* Enable ULI526X Tx/Rx function */
429 db->cr6_data |= CR6_RXSC | CR6_TXSC;
430 update_cr6(db->cr6_data, db->ioaddr);
431 while (!(inl(db->ioaddr + DCR12) & 0x8))
432 udelay(10);
433 }
434
435 /*
436 * Hardware start transmission.
437 * Send a packet to media from the upper layer.
438 */
439
440 static int uli526x_start_xmit(struct eth_device *dev,
441 volatile void *packet, int length)
442 {
443 struct uli526x_board_info *db = dev->priv;
444 struct tx_desc *txptr;
445 unsigned int len = length;
446 /* Too large packet check */
447 if (len > MAX_PACKET_SIZE) {
448 printf(": big packet = %d\n", len);
449 return 0;
450 }
451
452 /* No Tx resource check, it never happen nromally */
453 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
454 printf("No Tx resource %ld\n", db->tx_packet_cnt);
455 return 0;
456 }
457
458 /* Disable NIC interrupt */
459 outl(0, dev->iobase + DCR7);
460
461 /* transmit this packet */
462 txptr = db->tx_insert_ptr;
463 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
464 txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
465
466 /* Point to next transmit free descriptor */
467 db->tx_insert_ptr = txptr->next_tx_desc;
468
469 /* Transmit Packet Process */
470 if ((db->tx_packet_cnt < TX_DESC_CNT)) {
471 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
472 db->tx_packet_cnt++; /* Ready to send */
473 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
474 }
475
476 /* Got ULI526X status */
477 db->cr5_data = inl(db->ioaddr + DCR5);
478 outl(db->cr5_data, db->ioaddr + DCR5);
479
480 #ifdef TX_DEBUG
481 printf("%s(): length = 0x%x\n", __FUNCTION__, length);
482 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
483 #endif
484
485 outl(db->cr7_data, dev->iobase + DCR7);
486 uli526x_free_tx_pkt(dev, db);
487
488 return length;
489 }
490
491 /*
492 * Free TX resource after TX complete
493 */
494
495 static void uli526x_free_tx_pkt(struct eth_device *dev,
496 struct uli526x_board_info *db)
497 {
498 struct tx_desc *txptr;
499 u32 tdes0;
500
501 txptr = db->tx_remove_ptr;
502 while (db->tx_packet_cnt) {
503 tdes0 = le32_to_cpu(txptr->tdes0);
504 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
505 if (tdes0 & 0x80000000)
506 break;
507
508 /* A packet sent completed */
509 db->tx_packet_cnt--;
510
511 if (tdes0 != 0x7fffffff) {
512 #ifdef TX_DEBUG
513 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
514 #endif
515 if (tdes0 & TDES0_ERR_MASK) {
516 if (tdes0 & 0x0002) { /* UnderRun */
517 if (!(db->cr6_data & CR6_SFT)) {
518 db->cr6_data = db->cr6_data |
519 CR6_SFT;
520 update_cr6(db->cr6_data,
521 db->ioaddr);
522 }
523 }
524 }
525 }
526
527 txptr = txptr->next_tx_desc;
528 }/* End of while */
529
530 /* Update TX remove pointer to next */
531 db->tx_remove_ptr = txptr;
532 }
533
534
535 /*
536 * Receive the come packet and pass to upper layer
537 */
538
539 static int uli526x_rx_packet(struct eth_device *dev)
540 {
541 struct uli526x_board_info *db = dev->priv;
542 struct rx_desc *rxptr;
543 int rxlen = 0;
544 u32 rdes0;
545
546 rxptr = db->rx_ready_ptr;
547
548 rdes0 = le32_to_cpu(rxptr->rdes0);
549 #ifdef RX_DEBUG
550 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
551 #endif
552 if (!(rdes0 & 0x80000000)) { /* packet owner check */
553 if ((rdes0 & 0x300) != 0x300) {
554 /* A packet without First/Last flag */
555 /* reuse this buf */
556 printf("A packet without First/Last flag");
557 uli526x_reuse_buf(rxptr);
558 } else {
559 /* A packet with First/Last flag */
560 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
561 #ifdef RX_DEBUG
562 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
563 #endif
564 /* error summary bit check */
565 if (rdes0 & 0x8000) {
566 /* This is a error packet */
567 printf("Error: rdes0: %x\n", rdes0);
568 }
569
570 if (!(rdes0 & 0x8000) ||
571 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
572
573 #ifdef RX_DEBUG
574 printf("%s(): rx_skb_ptr =%x\n",
575 __FUNCTION__, rxptr->rx_buf_ptr);
576 printf("%s(): rxlen =%x\n",
577 __FUNCTION__, rxlen);
578
579 printf("%s(): buf addr =%x\n",
580 __FUNCTION__, rxptr->rx_buf_ptr);
581 printf("%s(): rxlen =%x\n",
582 __FUNCTION__, rxlen);
583 int i;
584 for (i = 0; i < 0x20; i++)
585 printf("%s(): data[%x] =%x\n",
586 __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
587 #endif
588
589 NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
590 uli526x_reuse_buf(rxptr);
591
592 } else {
593 /* Reuse SKB buffer when the packet is error */
594 printf("Reuse buffer, rdes0");
595 uli526x_reuse_buf(rxptr);
596 }
597 }
598
599 rxptr = rxptr->next_rx_desc;
600 }
601
602 db->rx_ready_ptr = rxptr;
603 return rxlen;
604 }
605
606 /*
607 * Reuse the RX buffer
608 */
609
610 static void uli526x_reuse_buf(struct rx_desc *rxptr)
611 {
612
613 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
614 rxptr->rdes0 = cpu_to_le32(0x80000000);
615 else
616 printf("Buffer reuse method error");
617 }
618 /*
619 * Initialize transmit/Receive descriptor
620 * Using Chain structure, and allocate Tx/Rx buffer
621 */
622
623 static void uli526x_descriptor_init(struct uli526x_board_info *db,
624 unsigned long ioaddr)
625 {
626 struct tx_desc *tmp_tx;
627 struct rx_desc *tmp_rx;
628 unsigned char *tmp_buf;
629 dma_addr_t tmp_tx_dma, tmp_rx_dma;
630 dma_addr_t tmp_buf_dma;
631 int i;
632 /* tx descriptor start pointer */
633 db->tx_insert_ptr = db->first_tx_desc;
634 db->tx_remove_ptr = db->first_tx_desc;
635
636 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
637
638 /* rx descriptor start pointer */
639 db->first_rx_desc = (void *)db->first_tx_desc +
640 sizeof(struct tx_desc) * TX_DESC_CNT;
641 db->first_rx_desc_dma = db->first_tx_desc_dma +
642 sizeof(struct tx_desc) * TX_DESC_CNT;
643 db->rx_ready_ptr = db->first_rx_desc;
644 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
645 #ifdef DEBUG
646 printf("%s(): db->first_tx_desc= 0x%x\n",
647 __FUNCTION__, db->first_tx_desc);
648 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
649 __FUNCTION__, db->first_rx_desc_dma);
650 #endif
651 /* Init Transmit chain */
652 tmp_buf = db->buf_pool_start;
653 tmp_buf_dma = db->buf_pool_dma_start;
654 tmp_tx_dma = db->first_tx_desc_dma;
655 for (tmp_tx = db->first_tx_desc, i = 0;
656 i < TX_DESC_CNT; i++, tmp_tx++) {
657 tmp_tx->tx_buf_ptr = (char *)tmp_buf;
658 tmp_tx->tdes0 = cpu_to_le32(0);
659 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
660 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
661 tmp_tx_dma += sizeof(struct tx_desc);
662 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
663 tmp_tx->next_tx_desc = tmp_tx + 1;
664 tmp_buf = tmp_buf + TX_BUF_ALLOC;
665 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
666 }
667 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
668 tmp_tx->next_tx_desc = db->first_tx_desc;
669
670 /* Init Receive descriptor chain */
671 tmp_rx_dma = db->first_rx_desc_dma;
672 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
673 i++, tmp_rx++) {
674 tmp_rx->rdes0 = cpu_to_le32(0);
675 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
676 tmp_rx_dma += sizeof(struct rx_desc);
677 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
678 tmp_rx->next_rx_desc = tmp_rx + 1;
679 }
680 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
681 tmp_rx->next_rx_desc = db->first_rx_desc;
682
683 /* pre-allocate Rx buffer */
684 allocate_rx_buffer(db);
685 }
686
687 /*
688 * Update CR6 value
689 * Firstly stop ULI526X, then written value and start
690 */
691
692 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
693 {
694
695 outl(cr6_data, ioaddr + DCR6);
696 udelay(5);
697 }
698
699 /*
700 * Allocate rx buffer,
701 */
702
703 static void allocate_rx_buffer(struct uli526x_board_info *db)
704 {
705 int index;
706 struct rx_desc *rxptr;
707 rxptr = db->first_rx_desc;
708 u32 addr;
709
710 for (index = 0; index < RX_DESC_CNT; index++) {
711 addr = (u32)NetRxPackets[index];
712 addr += (16 - (addr & 15));
713 rxptr->rx_buf_ptr = (char *) addr;
714 rxptr->rdes2 = cpu_to_le32(addr);
715 rxptr->rdes0 = cpu_to_le32(0x80000000);
716 #ifdef DEBUG
717 printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
718 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
719 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
720 printf("%s(): rxptr buf address = 0x%x\n", \
721 __FUNCTION__, rxptr->rx_buf_ptr);
722 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
723 #endif
724 rxptr = rxptr->next_rx_desc;
725 }
726 }
727
728 /*
729 * Read one word data from the serial ROM
730 */
731
732 static u16 read_srom_word(long ioaddr, int offset)
733 {
734 int i;
735 u16 srom_data = 0;
736 long cr9_ioaddr = ioaddr + DCR9;
737
738 outl(CR9_SROM_READ, cr9_ioaddr);
739 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
740
741 /* Send the Read Command 110b */
742 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
743 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
744 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
745
746 /* Send the offset */
747 for (i = 5; i >= 0; i--) {
748 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
749 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
750 }
751
752 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
753
754 for (i = 16; i > 0; i--) {
755 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
756 udelay(5);
757 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
758 ? 1 : 0);
759 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
760 udelay(5);
761 }
762
763 outl(CR9_SROM_READ, cr9_ioaddr);
764 return srom_data;
765 }
766
767 /*
768 * Set 10/100 phyxcer capability
769 * AUTO mode : phyxcer register4 is NIC capability
770 * Force mode: phyxcer register4 is the force media
771 */
772
773 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
774 {
775 u16 phy_reg;
776
777 /* Phyxcer capability setting */
778 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
779
780 if (db->media_mode & ULI526X_AUTO) {
781 /* AUTO Mode */
782 phy_reg |= db->PHY_reg4;
783 } else {
784 /* Force Mode */
785 switch (db->media_mode) {
786 case ULI526X_10MHF: phy_reg |= 0x20; break;
787 case ULI526X_10MFD: phy_reg |= 0x40; break;
788 case ULI526X_100MHF: phy_reg |= 0x80; break;
789 case ULI526X_100MFD: phy_reg |= 0x100; break;
790 }
791
792 }
793
794 /* Write new capability to Phyxcer Reg4 */
795 if (!(phy_reg & 0x01e0)) {
796 phy_reg |= db->PHY_reg4;
797 db->media_mode |= ULI526X_AUTO;
798 }
799 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
800
801 /* Restart Auto-Negotiation */
802 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
803 udelay(50);
804 }
805
806 /*
807 * Write a word to Phy register
808 */
809
810 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
811 u16 phy_data, u32 chip_id)
812 {
813 u16 i;
814 unsigned long ioaddr;
815
816 if (chip_id == PCI_ULI5263_ID) {
817 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
818 return;
819 }
820 /* M5261/M5263 Chip */
821 ioaddr = iobase + DCR9;
822
823 /* Send 33 synchronization clock to Phy controller */
824 for (i = 0; i < 35; i++)
825 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
826
827 /* Send start command(01) to Phy */
828 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
829 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
830
831 /* Send write command(01) to Phy */
832 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
833 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
834
835 /* Send Phy address */
836 for (i = 0x10; i > 0; i = i >> 1)
837 phy_write_1bit(ioaddr, phy_addr & i ?
838 PHY_DATA_1 : PHY_DATA_0, chip_id);
839
840 /* Send register address */
841 for (i = 0x10; i > 0; i = i >> 1)
842 phy_write_1bit(ioaddr, offset & i ?
843 PHY_DATA_1 : PHY_DATA_0, chip_id);
844
845 /* written trasnition */
846 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
847 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
848
849 /* Write a word data to PHY controller */
850 for (i = 0x8000; i > 0; i >>= 1)
851 phy_write_1bit(ioaddr, phy_data & i ?
852 PHY_DATA_1 : PHY_DATA_0, chip_id);
853 }
854
855 /*
856 * Read a word data from phy register
857 */
858
859 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
860 {
861 int i;
862 u16 phy_data;
863 unsigned long ioaddr;
864
865 if (chip_id == PCI_ULI5263_ID)
866 return phy_readby_cr10(iobase, phy_addr, offset);
867 /* M5261/M5263 Chip */
868 ioaddr = iobase + DCR9;
869
870 /* Send 33 synchronization clock to Phy controller */
871 for (i = 0; i < 35; i++)
872 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
873
874 /* Send start command(01) to Phy */
875 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
876 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
877
878 /* Send read command(10) to Phy */
879 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
880 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
881
882 /* Send Phy address */
883 for (i = 0x10; i > 0; i = i >> 1)
884 phy_write_1bit(ioaddr, phy_addr & i ?
885 PHY_DATA_1 : PHY_DATA_0, chip_id);
886
887 /* Send register address */
888 for (i = 0x10; i > 0; i = i >> 1)
889 phy_write_1bit(ioaddr, offset & i ?
890 PHY_DATA_1 : PHY_DATA_0, chip_id);
891
892 /* Skip transition state */
893 phy_read_1bit(ioaddr, chip_id);
894
895 /* read 16bit data */
896 for (phy_data = 0, i = 0; i < 16; i++) {
897 phy_data <<= 1;
898 phy_data |= phy_read_1bit(ioaddr, chip_id);
899 }
900
901 return phy_data;
902 }
903
904 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
905 {
906 unsigned long ioaddr, cr10_value;
907
908 ioaddr = iobase + DCR10;
909 cr10_value = phy_addr;
910 cr10_value = (cr10_value<<5) + offset;
911 cr10_value = (cr10_value<<16) + 0x08000000;
912 outl(cr10_value, ioaddr);
913 udelay(1);
914 while (1) {
915 cr10_value = inl(ioaddr);
916 if (cr10_value & 0x10000000)
917 break;
918 }
919 return (cr10_value&0x0ffff);
920 }
921
922 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
923 u8 offset, u16 phy_data)
924 {
925 unsigned long ioaddr, cr10_value;
926
927 ioaddr = iobase + DCR10;
928 cr10_value = phy_addr;
929 cr10_value = (cr10_value<<5) + offset;
930 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
931 outl(cr10_value, ioaddr);
932 udelay(1);
933 }
934 /*
935 * Write one bit data to Phy Controller
936 */
937
938 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
939 {
940 outl(phy_data , ioaddr); /* MII Clock Low */
941 udelay(1);
942 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
943 udelay(1);
944 outl(phy_data , ioaddr); /* MII Clock Low */
945 udelay(1);
946 }
947
948 /*
949 * Read one bit phy data from PHY controller
950 */
951
952 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
953 {
954 u16 phy_data;
955
956 outl(0x50000 , ioaddr);
957 udelay(1);
958 phy_data = (inl(ioaddr) >> 19) & 0x1;
959 outl(0x40000 , ioaddr);
960 udelay(1);
961
962 return phy_data;
963 }
964
965 /*
966 * Set MAC address to ID Table
967 */
968
969 static void set_mac_addr(struct eth_device *dev)
970 {
971 int i;
972 u16 addr;
973 struct uli526x_board_info *db = dev->priv;
974 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
975 /* Reset dianostic pointer port */
976 outl(0x1c0, db->ioaddr + DCR13);
977 outl(0, db->ioaddr + DCR14); /* Clear reset port */
978 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
979 outl(0, db->ioaddr + DCR14); /* Clear reset port */
980 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
981 /* Select ID Table access port */
982 outl(0x1b0, db->ioaddr + DCR13);
983 /* Read MAC address from CR14 */
984 for (i = 0; i < 3; i++) {
985 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
986 outl(addr, db->ioaddr + DCR14);
987 }
988 /* write end */
989 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
990 outl(0, db->ioaddr + DCR0); /* Clear CR0 */
991 udelay(10);
992 return;
993 }
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