drivers/net/xilinx_ll_temac_mdio.c

   1 /*
   2  * Xilinx xps_ll_temac ethernet driver for u-boot
   3  *
   4  * MDIO bus access
   5  *
   6  * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
   7  * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
   8  * Copyright (C) 2008 - 2011 PetaLogix
   9  *
  10  * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
  11  * Copyright (C) 2008 Nissin Systems Co.,Ltd.
  12  * March 2008 created
  13  *
  14  * CREDITS: tsec driver
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * [0]: http://www.xilinx.com/support/documentation
  22  *
  23  * [S]: [0]/ip_documentation/xps_ll_temac.pdf
  24  * [A]: [0]/application_notes/xapp1041.pdf
  25  */
  26
  27 #include <config.h>
  28 #include <common.h>
  29 #include <miiphy.h>
  30 #include <phy.h>
  31 #include <malloc.h>
  32 #include <asm/io.h>
  33
  34 #include "xilinx_ll_temac.h"
  35 #include "xilinx_ll_temac_mdio.h"
  36
  37 #if !defined(CONFIG_MII)
  38 # error "LL_TEMAC requires MII -- missing CONFIG_MII"
  39 #endif
  40
  41 #if !defined(CONFIG_PHYLIB)
  42 # error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB"
  43 #endif
  44
  45 /*
  46  * Prior to PHY access, the MDIO clock must be setup. This driver will set a
  47  * safe default that should work with PLB bus speeds of up to 150 MHz and keep
  48  * the MDIO clock below 2.5 MHz. If the user wishes faster access to the PHY
  49  * then the clock divisor can be set to a different value by setting the
  50  * correct bus speed value with CONFIG_XILINX_LL_TEMAC_CLK.
  51  */
  52 #if !defined(CONFIG_XILINX_LL_TEMAC_CLK)
  53 #define MDIO_CLOCK_DIV          MC_CLKDIV_10(150000000)
  54 #else
  55 #define MDIO_CLOCK_DIV          MC_CLKDIV_25(CONFIG_XILINX_LL_TEMAC_CLK)
  56 #endif
  57
  58 static int ll_temac_mdio_setup(struct mii_dev *bus)
  59 {
  60         struct temac_reg *regs = (struct temac_reg *)bus->priv;
  61
  62         /* setup MDIO clock */
  63         ll_temac_indirect_set(regs, TEMAC_MC,
  64                         MC_MDIOEN | (MDIO_CLOCK_DIV & MC_CLKDIV_MASK));
  65
  66         return 0;
  67 }
  68
  69 /*
  70  * Indirect MII PHY read via ll_temac.
  71  *
  72  * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
  73  * page 67, Using the MII Management to Access PHY Registers
  74  */
  75 int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad,
  76                                 int regnum)
  77 {
  78         out_be32(&regs->lsw,
  79                 ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) |
  80                 (regnum & LSW_REGAD_MASK));
  81         out_be32(&regs->ctl, TEMAC_MIIMAI);
  82
  83         ll_temac_check_status(regs, RSE_MIIM_RR);
  84
  85         return in_be32(&regs->lsw) & LSW_REGDAT_MASK;
  86 }
  87
  88 /*
  89  * Indirect MII PHY write via ll_temac.
  90  *
  91  * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
  92  * page 67, Using the MII Management to Access PHY Registers
  93  */
  94 void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad,
  95                                 int regnum, u16 value)
  96 {
  97         out_be32(&regs->lsw, (value & LSW_REGDAT_MASK));
  98         out_be32(&regs->ctl, CTL_WEN | TEMAC_MIIMWD);
  99
 100         out_be32(&regs->lsw,
 101                 ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) |
 102                 (regnum & LSW_REGAD_MASK));
 103         out_be32(&regs->ctl, CTL_WEN | TEMAC_MIIMAI);
 104
 105         ll_temac_check_status(regs, RSE_MIIM_WR);
 106 }
 107
 108 int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum)
 109 {
 110         struct temac_reg *regs = (struct temac_reg *)bus->priv;
 111
 112         return ll_temac_local_mdio_read(regs, addr, devad, regnum);
 113 }
 114
 115 int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum,
 116                         u16 value)
 117 {
 118         struct temac_reg *regs = (struct temac_reg *)bus->priv;
 119
 120         ll_temac_local_mdio_write(regs, addr, devad, regnum, value);
 121
 122         return 0;
 123 }
 124
 125 /*
 126  * Use MII register 1 (MII status register) to detect PHY
 127  *
 128  * A Mask used to verify certain PHY features (register content)
 129  * in the PHY detection register:
 130  *  Auto-negotiation support, 10Mbps half/full duplex support
 131  */
 132 #define PHY_DETECT_REG          MII_BMSR
 133 #define PHY_DETECT_MASK         (BMSR_10FULL | BMSR_10HALF | BMSR_ANEGCAPABLE)
 134
 135 /* Looking for a valid PHY address */
 136 int ll_temac_phy_addr(struct mii_dev *bus)
 137 {
 138         struct temac_reg *regs = (struct temac_reg *)bus->priv;
 139         unsigned short val;
 140         unsigned int phy;
 141
 142         for (phy = PHY_MAX_ADDR; phy >= 0; phy--) {
 143                 val = ll_temac_local_mdio_read(regs, phy, 0, PHY_DETECT_REG);
 144                 if ((val != 0xFFFF) &&
 145                 ((val & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 146                         /* Found a valid PHY address */
 147                         return phy;
 148                 }
 149         }
 150
 151         return -1;
 152 }
 153
 154 int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info)
 155 {
 156         struct mii_dev *bus = mdio_alloc();
 157
 158         if (!bus) {
 159                 printf("Failed to allocate LL_TEMAC MDIO bus: %s\n",
 160                                 info->name);
 161                 return -1;
 162         }
 163
 164         bus->read = ll_temac_phy_read;
 165         bus->write = ll_temac_phy_write;
 166         bus->reset = NULL;
 167
 168         /* use given name or generate its own unique name */
 169         if (info->name) {
 170                 strncpy(bus->name, info->name, MDIO_NAME_LEN);
 171         } else {
 172                 snprintf(bus->name, MDIO_NAME_LEN, "lltemii.%p", info->regs);
 173                 info->name = bus->name;
 174         }
 175
 176         bus->priv = info->regs;
 177
 178         ll_temac_mdio_setup(bus);
 179         return mdio_register(bus);
 180 }