drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <config.h>
  16 #include <fdtdec.h>
  17 #include <libfdt.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <watchdog.h>
  23 #include <asm/system.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm-generic/errno.h>
  27
  28 #if !defined(CONFIG_PHYLIB)
  29 # error XILINX_GEM_ETHERNET requires PHYLIB
  30 #endif
  31
  32 /* Bit/mask specification */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  38
  39 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  40 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  41 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  42
  43 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  44 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  45 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  46
  47 /* Wrap bit, last descriptor */
  48 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  49 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  50 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  51
  52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  56
  57 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  58 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  59 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  60 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x0000c0000 /* Div pclk by 48, max 120MHz */
  62
  63 #ifdef CONFIG_ARM64
  64 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  65 #else
  66 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  67 #endif
  68
  69 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  70                                         ZYNQ_GEM_NWCFG_FDEN | \
  71                                         ZYNQ_GEM_NWCFG_FSREM | \
  72                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  73
  74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  75
  76 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  77 /* Use full configured addressable space (8 Kb) */
  78 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  79 /* Use full configured addressable space (4 Kb) */
  80 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  82 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  83
  84 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  85                                         ZYNQ_GEM_DMACR_RXSIZE | \
  86                                         ZYNQ_GEM_DMACR_TXSIZE | \
  87                                         ZYNQ_GEM_DMACR_RXBUF)
  88
  89 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  90
  91 /* Use MII register 1 (MII status register) to detect PHY */
  92 #define PHY_DETECT_REG  1
  93
  94 /* Mask used to verify certain PHY features (or register contents)
  95  * in the register above:
  96  *  0x1000: 10Mbps full duplex support
  97  *  0x0800: 10Mbps half duplex support
  98  *  0x0008: Auto-negotiation support
  99  */
 100 #define PHY_DETECT_MASK 0x1808
 101
 102 /* TX BD status masks */
 103 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 104 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 105 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 106
 107 /* Clock frequencies for different speeds */
 108 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 109 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 110 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 111
 112 /* Device registers */
 113 struct zynq_gem_regs {
 114         u32 nwctrl; /* 0x0 - Network Control reg */
 115         u32 nwcfg; /* 0x4 - Network Config reg */
 116         u32 nwsr; /* 0x8 - Network Status reg */
 117         u32 reserved1;
 118         u32 dmacr; /* 0x10 - DMA Control reg */
 119         u32 txsr; /* 0x14 - TX Status reg */
 120         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 121         u32 txqbase; /* 0x1c - TX Q Base address reg */
 122         u32 rxsr; /* 0x20 - RX Status reg */
 123         u32 reserved2[2];
 124         u32 idr; /* 0x2c - Interrupt Disable reg */
 125         u32 reserved3;
 126         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 127         u32 reserved4[18];
 128         u32 hashl; /* 0x80 - Hash Low address reg */
 129         u32 hashh; /* 0x84 - Hash High address reg */
 130 #define LADDR_LOW       0
 131 #define LADDR_HIGH      1
 132         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 133         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 134         u32 reserved6[18];
 135 #define STAT_SIZE       44
 136         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 137         u32 reserved7[164];
 138         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 139         u32 reserved8[15];
 140         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 141 };
 142
 143 /* BD descriptors */
 144 struct emac_bd {
 145         u32 addr; /* Next descriptor pointer */
 146         u32 status;
 147 };
 148
 149 #define RX_BUF 32
 150 /* Page table entries are set to 1MB, or multiples of 1MB
 151  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 152  */
 153 #define BD_SPACE        0x100000
 154 /* BD separation space */
 155 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 156
 157 /* Setup the first free TX descriptor */
 158 #define TX_FREE_DESC    2
 159
 160 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 161 struct zynq_gem_priv {
 162         struct emac_bd *tx_bd;
 163         struct emac_bd *rx_bd;
 164         char *rxbuffers;
 165         u32 rxbd_current;
 166         u32 rx_first_buf;
 167         int phyaddr;
 168         u32 emio;
 169         int init;
 170         phy_interface_t interface;
 171         struct phy_device *phydev;
 172         struct mii_dev *bus;
 173 };
 174
 175 static inline int mdio_wait(struct eth_device *dev)
 176 {
 177         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 178         u32 timeout = 20000;
 179
 180         /* Wait till MDIO interface is ready to accept a new transaction. */
 181         while (--timeout) {
 182                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 183                         break;
 184                 WATCHDOG_RESET();
 185         }
 186
 187         if (!timeout) {
 188                 printf("%s: Timeout\n", __func__);
 189                 return 1;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
 196                                                         u32 op, u16 *data)
 197 {
 198         u32 mgtcr;
 199         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 200
 201         if (mdio_wait(dev))
 202                 return 1;
 203
 204         /* Construct mgtcr mask for the operation */
 205         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 206                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 207                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 208
 209         /* Write mgtcr and wait for completion */
 210         writel(mgtcr, &regs->phymntnc);
 211
 212         if (mdio_wait(dev))
 213                 return 1;
 214
 215         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 216                 *data = readl(&regs->phymntnc);
 217
 218         return 0;
 219 }
 220
 221 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
 222 {
 223         u32 ret;
 224
 225         ret = phy_setup_op(dev, phy_addr, regnum,
 226                                 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 227
 228         if (!ret)
 229                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 230                       phy_addr, regnum, *val);
 231
 232         return ret;
 233 }
 234
 235 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
 236 {
 237         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 238               regnum, data);
 239
 240         return phy_setup_op(dev, phy_addr, regnum,
 241                                 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 242 }
 243
 244 static int phy_detection(struct eth_device *dev)
 245 {
 246         int i;
 247         u16 phyreg;
 248         struct zynq_gem_priv *priv = dev->priv;
 249
 250         if (priv->phyaddr != -1) {
 251                 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 252                 if ((phyreg != 0xFFFF) &&
 253                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 254                         /* Found a valid PHY address */
 255                         debug("Default phy address %d is valid\n",
 256                               priv->phyaddr);
 257                         return 0;
 258                 } else {
 259                         debug("PHY address is not setup correctly %d\n",
 260                               priv->phyaddr);
 261                         priv->phyaddr = -1;
 262                 }
 263         }
 264
 265         debug("detecting phy address\n");
 266         if (priv->phyaddr == -1) {
 267                 /* detect the PHY address */
 268                 for (i = 31; i >= 0; i--) {
 269                         phyread(dev, i, PHY_DETECT_REG, &phyreg);
 270                         if ((phyreg != 0xFFFF) &&
 271                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 272                                 /* Found a valid PHY address */
 273                                 priv->phyaddr = i;
 274                                 debug("Found valid phy address, %d\n", i);
 275                                 return 0;
 276                         }
 277                 }
 278         }
 279         printf("PHY is not detected\n");
 280         return -1;
 281 }
 282
 283 static int zynq_gem_setup_mac(struct eth_device *dev)
 284 {
 285         u32 i, macaddrlow, macaddrhigh;
 286         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 287
 288         /* Set the MAC bits [31:0] in BOT */
 289         macaddrlow = dev->enetaddr[0];
 290         macaddrlow |= dev->enetaddr[1] << 8;
 291         macaddrlow |= dev->enetaddr[2] << 16;
 292         macaddrlow |= dev->enetaddr[3] << 24;
 293
 294         /* Set MAC bits [47:32] in TOP */
 295         macaddrhigh = dev->enetaddr[4];
 296         macaddrhigh |= dev->enetaddr[5] << 8;
 297
 298         for (i = 0; i < 4; i++) {
 299                 writel(0, &regs->laddr[i][LADDR_LOW]);
 300                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 301                 /* Do not use MATCHx register */
 302                 writel(0, &regs->match[i]);
 303         }
 304
 305         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 306         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 307
 308         return 0;
 309 }
 310
 311 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 312 {
 313         u32 i;
 314         int ret;
 315         unsigned long clk_rate = 0;
 316         struct phy_device *phydev;
 317         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 318         struct zynq_gem_priv *priv = dev->priv;
 319         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 320         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 321         const u32 supported = SUPPORTED_10baseT_Half |
 322                         SUPPORTED_10baseT_Full |
 323                         SUPPORTED_100baseT_Half |
 324                         SUPPORTED_100baseT_Full |
 325                         SUPPORTED_1000baseT_Half |
 326                         SUPPORTED_1000baseT_Full;
 327
 328         if (!priv->init) {
 329                 /* Disable all interrupts */
 330                 writel(0xFFFFFFFF, &regs->idr);
 331
 332                 /* Disable the receiver & transmitter */
 333                 writel(0, &regs->nwctrl);
 334                 writel(0, &regs->txsr);
 335                 writel(0, &regs->rxsr);
 336                 writel(0, &regs->phymntnc);
 337
 338                 /* Clear the Hash registers for the mac address
 339                  * pointed by AddressPtr
 340                  */
 341                 writel(0x0, &regs->hashl);
 342                 /* Write bits [63:32] in TOP */
 343                 writel(0x0, &regs->hashh);
 344
 345                 /* Clear all counters */
 346                 for (i = 0; i < STAT_SIZE; i++)
 347                         readl(&regs->stat[i]);
 348
 349                 /* Setup RxBD space */
 350                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 351
 352                 for (i = 0; i < RX_BUF; i++) {
 353                         priv->rx_bd[i].status = 0xF0000000;
 354                         priv->rx_bd[i].addr =
 355                                         ((ulong)(priv->rxbuffers) +
 356                                                         (i * PKTSIZE_ALIGN));
 357                 }
 358                 /* WRAP bit to last BD */
 359                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 360                 /* Write RxBDs to IP */
 361                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 362
 363                 /* Setup for DMA Configuration register */
 364                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 365
 366                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 367                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 368
 369                 /* Disable the second priority queue */
 370                 dummy_tx_bd->addr = 0;
 371                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 372                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 373                                 ZYNQ_GEM_TXBUF_USED_MASK;
 374
 375                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 376                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 377                 dummy_rx_bd->status = 0;
 378                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 379                                    sizeof(dummy_tx_bd));
 380                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 381                                    sizeof(dummy_rx_bd));
 382
 383                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 384                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 385
 386                 priv->init++;
 387         }
 388
 389         ret = phy_detection(dev);
 390         if (ret) {
 391                 printf("GEM PHY init failed\n");
 392                 return ret;
 393         }
 394
 395         /* interface - look at tsec */
 396         phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 397                              priv->interface);
 398
 399         phydev->supported = supported | ADVERTISED_Pause |
 400                             ADVERTISED_Asym_Pause;
 401         phydev->advertising = phydev->supported;
 402         priv->phydev = phydev;
 403         phy_config(phydev);
 404         phy_startup(phydev);
 405
 406         if (!phydev->link) {
 407                 printf("%s: No link.\n", phydev->dev->name);
 408                 return -1;
 409         }
 410
 411         switch (phydev->speed) {
 412         case SPEED_1000:
 413                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 414                        &regs->nwcfg);
 415                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 416                 break;
 417         case SPEED_100:
 418                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
 419                        &regs->nwcfg);
 420                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 421                 break;
 422         case SPEED_10:
 423                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 424                 break;
 425         }
 426
 427         /* Change the rclk and clk only not using EMIO interface */
 428         if (!priv->emio)
 429                 zynq_slcr_gem_clk_setup(dev->iobase !=
 430                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 431
 432         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 433                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 434
 435         return 0;
 436 }
 437
 438 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 439                         bool set, unsigned int timeout)
 440 {
 441         u32 val;
 442         unsigned long start = get_timer(0);
 443
 444         while (1) {
 445                 val = readl(reg);
 446
 447                 if (!set)
 448                         val = ~val;
 449
 450                 if ((val & mask) == mask)
 451                         return 0;
 452
 453                 if (get_timer(start) > timeout)
 454                         break;
 455
 456                 udelay(1);
 457         }
 458
 459         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
 460               func, reg, mask, set);
 461
 462         return -ETIMEDOUT;
 463 }
 464
 465 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
 466 {
 467         u32 addr, size;
 468         struct zynq_gem_priv *priv = dev->priv;
 469         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 470         struct emac_bd *current_bd = &priv->tx_bd[1];
 471
 472         /* Setup Tx BD */
 473         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 474
 475         priv->tx_bd->addr = (ulong)ptr;
 476         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 477                                ZYNQ_GEM_TXBUF_LAST_MASK;
 478         /* Dummy descriptor to mark it as the last in descriptor chain */
 479         current_bd->addr = 0x0;
 480         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 481                              ZYNQ_GEM_TXBUF_LAST_MASK|
 482                              ZYNQ_GEM_TXBUF_USED_MASK;
 483
 484         /* setup BD */
 485         writel((ulong)priv->tx_bd, &regs->txqbase);
 486
 487         addr = (ulong) ptr;
 488         addr &= ~(ARCH_DMA_MINALIGN - 1);
 489         size = roundup(len, ARCH_DMA_MINALIGN);
 490         flush_dcache_range(addr, addr + size);
 491
 492         addr = (ulong)priv->rxbuffers;
 493         addr &= ~(ARCH_DMA_MINALIGN - 1);
 494         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 495         flush_dcache_range(addr, addr + size);
 496         barrier();
 497
 498         /* Start transmit */
 499         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 500
 501         /* Read TX BD status */
 502         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 503                 printf("TX buffers exhausted in mid frame\n");
 504
 505         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 506                             true, 20000);
 507 }
 508
 509 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 510 static int zynq_gem_recv(struct eth_device *dev)
 511 {
 512         int frame_len;
 513         struct zynq_gem_priv *priv = dev->priv;
 514         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 515         struct emac_bd *first_bd;
 516
 517         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 518                 return 0;
 519
 520         if (!(current_bd->status &
 521                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 522                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 523                 return 0;
 524         }
 525
 526         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 527         if (frame_len) {
 528                 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 529                 addr &= ~(ARCH_DMA_MINALIGN - 1);
 530
 531                 net_process_received_packet((u8 *)(ulong)addr, frame_len);
 532
 533                 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
 534                         priv->rx_first_buf = priv->rxbd_current;
 535                 else {
 536                         current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 537                         current_bd->status = 0xF0000000; /* FIXME */
 538                 }
 539
 540                 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 541                         first_bd = &priv->rx_bd[priv->rx_first_buf];
 542                         first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 543                         first_bd->status = 0xF0000000;
 544                 }
 545
 546                 if ((++priv->rxbd_current) >= RX_BUF)
 547                         priv->rxbd_current = 0;
 548         }
 549
 550         return frame_len;
 551 }
 552
 553 static void zynq_gem_halt(struct eth_device *dev)
 554 {
 555         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 556
 557         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 558                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 559 }
 560
 561 static int zynq_gem_miiphyread(const char *devname, uchar addr,
 562                                                         uchar reg, ushort *val)
 563 {
 564         struct eth_device *dev = eth_get_dev();
 565         int ret;
 566
 567         ret = phyread(dev, addr, reg, val);
 568         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
 569         return ret;
 570 }
 571
 572 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
 573                                                         uchar reg, ushort val)
 574 {
 575         struct eth_device *dev = eth_get_dev();
 576
 577         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
 578         return phywrite(dev, addr, reg, val);
 579 }
 580
 581 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
 582                         int phy_addr, u32 emio)
 583 {
 584         struct eth_device *dev;
 585         struct zynq_gem_priv *priv;
 586         void *bd_space;
 587
 588         dev = calloc(1, sizeof(*dev));
 589         if (dev == NULL)
 590                 return -1;
 591
 592         dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
 593         if (dev->priv == NULL) {
 594                 free(dev);
 595                 return -1;
 596         }
 597         priv = dev->priv;
 598
 599         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 600         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 601         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 602
 603         /* Align bd_space to MMU_SECTION_SHIFT */
 604         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 605         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 606                                         BD_SPACE, DCACHE_OFF);
 607
 608         /* Initialize the bd spaces for tx and rx bd's */
 609         priv->tx_bd = (struct emac_bd *)bd_space;
 610         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 611
 612         priv->phyaddr = phy_addr;
 613         priv->emio = emio;
 614
 615 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
 616         priv->interface = PHY_INTERFACE_MODE_MII;
 617 #else
 618         priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
 619 #endif
 620
 621         sprintf(dev->name, "Gem.%lx", base_addr);
 622
 623         dev->iobase = base_addr;
 624
 625         dev->init = zynq_gem_init;
 626         dev->halt = zynq_gem_halt;
 627         dev->send = zynq_gem_send;
 628         dev->recv = zynq_gem_recv;
 629         dev->write_hwaddr = zynq_gem_setup_mac;
 630
 631         eth_register(dev);
 632
 633         miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
 634         priv->bus = miiphy_get_dev_by_name(dev->name);
 635
 636         return 1;
 637 }
 638
 639 #if CONFIG_IS_ENABLED(OF_CONTROL)
 640 int zynq_gem_of_init(const void *blob)
 641 {
 642         int offset = 0;
 643         u32 ret = 0;
 644         u32 reg, phy_reg;
 645
 646         debug("ZYNQ GEM: Initialization\n");
 647
 648         do {
 649                 offset = fdt_node_offset_by_compatible(blob, offset,
 650                                         "xlnx,ps7-ethernet-1.00.a");
 651                 if (offset != -1) {
 652                         reg = fdtdec_get_addr(blob, offset, "reg");
 653                         if (reg != FDT_ADDR_T_NONE) {
 654                                 offset = fdtdec_lookup_phandle(blob, offset,
 655                                                                "phy-handle");
 656                                 if (offset != -1)
 657                                         phy_reg = fdtdec_get_addr(blob, offset,
 658                                                                   "reg");
 659                                 else
 660                                         phy_reg = 0;
 661
 662                                 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
 663                                       reg, phy_reg);
 664
 665                                 ret |= zynq_gem_initialize(NULL, reg,
 666                                                            phy_reg, 0);
 667
 668                         } else {
 669                                 debug("ZYNQ GEM: Can't get base address\n");
 670                                 return -1;
 671                         }
 672                 }
 673         } while (offset != -1);
 674
 675         return ret;
 676 }
 677 #endif