drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <config.h>
  16 #include <fdtdec.h>
  17 #include <libfdt.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <miiphy.h>
  22 #include <watchdog.h>
  23 #include <asm/system.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm-generic/errno.h>
  27
  28 #if !defined(CONFIG_PHYLIB)
  29 # error XILINX_GEM_ETHERNET requires PHYLIB
  30 #endif
  31
  32 /* Bit/mask specification */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  38
  39 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  40 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  41 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  42
  43 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  44 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  45 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  46
  47 /* Wrap bit, last descriptor */
  48 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  49 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  50 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  51
  52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  56
  57 #define ZYNQ_GEM_NWCFG_SPEED100         0x000000001 /* 100 Mbps operation */
  58 #define ZYNQ_GEM_NWCFG_SPEED1000        0x000000400 /* 1Gbps operation */
  59 #define ZYNQ_GEM_NWCFG_FDEN             0x000000002 /* Full Duplex mode */
  60 #define ZYNQ_GEM_NWCFG_FSREM            0x000020000 /* FCS removal */
  61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x0000c0000 /* Div pclk by 48, max 120MHz */
  62
  63 #ifdef CONFIG_ARM64
  64 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  65 #else
  66 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  67 #endif
  68
  69 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  70                                         ZYNQ_GEM_NWCFG_FDEN | \
  71                                         ZYNQ_GEM_NWCFG_FSREM | \
  72                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  73
  74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  75
  76 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  77 /* Use full configured addressable space (8 Kb) */
  78 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  79 /* Use full configured addressable space (4 Kb) */
  80 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  82 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  83
  84 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  85                                         ZYNQ_GEM_DMACR_RXSIZE | \
  86                                         ZYNQ_GEM_DMACR_TXSIZE | \
  87                                         ZYNQ_GEM_DMACR_RXBUF)
  88
  89 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  90
  91 /* Use MII register 1 (MII status register) to detect PHY */
  92 #define PHY_DETECT_REG  1
  93
  94 /* Mask used to verify certain PHY features (or register contents)
  95  * in the register above:
  96  *  0x1000: 10Mbps full duplex support
  97  *  0x0800: 10Mbps half duplex support
  98  *  0x0008: Auto-negotiation support
  99  */
 100 #define PHY_DETECT_MASK 0x1808
 101
 102 /* TX BD status masks */
 103 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 104 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 105 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 106
 107 /* Clock frequencies for different speeds */
 108 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 109 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 110 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 111
 112 /* Device registers */
 113 struct zynq_gem_regs {
 114         u32 nwctrl; /* 0x0 - Network Control reg */
 115         u32 nwcfg; /* 0x4 - Network Config reg */
 116         u32 nwsr; /* 0x8 - Network Status reg */
 117         u32 reserved1;
 118         u32 dmacr; /* 0x10 - DMA Control reg */
 119         u32 txsr; /* 0x14 - TX Status reg */
 120         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 121         u32 txqbase; /* 0x1c - TX Q Base address reg */
 122         u32 rxsr; /* 0x20 - RX Status reg */
 123         u32 reserved2[2];
 124         u32 idr; /* 0x2c - Interrupt Disable reg */
 125         u32 reserved3;
 126         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 127         u32 reserved4[18];
 128         u32 hashl; /* 0x80 - Hash Low address reg */
 129         u32 hashh; /* 0x84 - Hash High address reg */
 130 #define LADDR_LOW       0
 131 #define LADDR_HIGH      1
 132         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 133         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 134         u32 reserved6[18];
 135 #define STAT_SIZE       44
 136         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 137         u32 reserved7[164];
 138         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 139         u32 reserved8[15];
 140         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 141 };
 142
 143 /* BD descriptors */
 144 struct emac_bd {
 145         u32 addr; /* Next descriptor pointer */
 146         u32 status;
 147 };
 148
 149 #define RX_BUF 32
 150 /* Page table entries are set to 1MB, or multiples of 1MB
 151  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 152  */
 153 #define BD_SPACE        0x100000
 154 /* BD separation space */
 155 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 156
 157 /* Setup the first free TX descriptor */
 158 #define TX_FREE_DESC    2
 159
 160 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 161 struct zynq_gem_priv {
 162         struct emac_bd *tx_bd;
 163         struct emac_bd *rx_bd;
 164         char *rxbuffers;
 165         u32 rxbd_current;
 166         u32 rx_first_buf;
 167         int phyaddr;
 168         u32 emio;
 169         int init;
 170         struct zynq_gem_regs *iobase;
 171         phy_interface_t interface;
 172         struct phy_device *phydev;
 173         struct mii_dev *bus;
 174 };
 175
 176 static inline int mdio_wait(struct zynq_gem_regs *regs)
 177 {
 178         u32 timeout = 20000;
 179
 180         /* Wait till MDIO interface is ready to accept a new transaction. */
 181         while (--timeout) {
 182                 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
 183                         break;
 184                 WATCHDOG_RESET();
 185         }
 186
 187         if (!timeout) {
 188                 printf("%s: Timeout\n", __func__);
 189                 return 1;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 196                         u32 op, u16 *data)
 197 {
 198         u32 mgtcr;
 199         struct zynq_gem_regs *regs = priv->iobase;
 200
 201         if (mdio_wait(regs))
 202                 return 1;
 203
 204         /* Construct mgtcr mask for the operation */
 205         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 206                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 207                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 208
 209         /* Write mgtcr and wait for completion */
 210         writel(mgtcr, &regs->phymntnc);
 211
 212         if (mdio_wait(regs))
 213                 return 1;
 214
 215         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 216                 *data = readl(&regs->phymntnc);
 217
 218         return 0;
 219 }
 220
 221 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 222                    u32 regnum, u16 *val)
 223 {
 224         u32 ret;
 225
 226         ret = phy_setup_op(priv, phy_addr, regnum,
 227                            ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 228
 229         if (!ret)
 230                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 231                       phy_addr, regnum, *val);
 232
 233         return ret;
 234 }
 235
 236 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 237                     u32 regnum, u16 data)
 238 {
 239         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 240               regnum, data);
 241
 242         return phy_setup_op(priv, phy_addr, regnum,
 243                             ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 244 }
 245
 246 static int phy_detection(struct eth_device *dev)
 247 {
 248         int i;
 249         u16 phyreg;
 250         struct zynq_gem_priv *priv = dev->priv;
 251
 252         if (priv->phyaddr != -1) {
 253                 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 254                 if ((phyreg != 0xFFFF) &&
 255                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 256                         /* Found a valid PHY address */
 257                         debug("Default phy address %d is valid\n",
 258                               priv->phyaddr);
 259                         return 0;
 260                 } else {
 261                         debug("PHY address is not setup correctly %d\n",
 262                               priv->phyaddr);
 263                         priv->phyaddr = -1;
 264                 }
 265         }
 266
 267         debug("detecting phy address\n");
 268         if (priv->phyaddr == -1) {
 269                 /* detect the PHY address */
 270                 for (i = 31; i >= 0; i--) {
 271                         phyread(priv, i, PHY_DETECT_REG, &phyreg);
 272                         if ((phyreg != 0xFFFF) &&
 273                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 274                                 /* Found a valid PHY address */
 275                                 priv->phyaddr = i;
 276                                 debug("Found valid phy address, %d\n", i);
 277                                 return 0;
 278                         }
 279                 }
 280         }
 281         printf("PHY is not detected\n");
 282         return -1;
 283 }
 284
 285 static int zynq_gem_setup_mac(struct eth_device *dev)
 286 {
 287         u32 i, macaddrlow, macaddrhigh;
 288         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 289
 290         /* Set the MAC bits [31:0] in BOT */
 291         macaddrlow = dev->enetaddr[0];
 292         macaddrlow |= dev->enetaddr[1] << 8;
 293         macaddrlow |= dev->enetaddr[2] << 16;
 294         macaddrlow |= dev->enetaddr[3] << 24;
 295
 296         /* Set MAC bits [47:32] in TOP */
 297         macaddrhigh = dev->enetaddr[4];
 298         macaddrhigh |= dev->enetaddr[5] << 8;
 299
 300         for (i = 0; i < 4; i++) {
 301                 writel(0, &regs->laddr[i][LADDR_LOW]);
 302                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 303                 /* Do not use MATCHx register */
 304                 writel(0, &regs->match[i]);
 305         }
 306
 307         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 308         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 309
 310         return 0;
 311 }
 312
 313 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 314 {
 315         u32 i;
 316         int ret;
 317         unsigned long clk_rate = 0;
 318         struct phy_device *phydev;
 319         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 320         struct zynq_gem_priv *priv = dev->priv;
 321         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 322         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 323         const u32 supported = SUPPORTED_10baseT_Half |
 324                         SUPPORTED_10baseT_Full |
 325                         SUPPORTED_100baseT_Half |
 326                         SUPPORTED_100baseT_Full |
 327                         SUPPORTED_1000baseT_Half |
 328                         SUPPORTED_1000baseT_Full;
 329
 330         if (!priv->init) {
 331                 /* Disable all interrupts */
 332                 writel(0xFFFFFFFF, &regs->idr);
 333
 334                 /* Disable the receiver & transmitter */
 335                 writel(0, &regs->nwctrl);
 336                 writel(0, &regs->txsr);
 337                 writel(0, &regs->rxsr);
 338                 writel(0, &regs->phymntnc);
 339
 340                 /* Clear the Hash registers for the mac address
 341                  * pointed by AddressPtr
 342                  */
 343                 writel(0x0, &regs->hashl);
 344                 /* Write bits [63:32] in TOP */
 345                 writel(0x0, &regs->hashh);
 346
 347                 /* Clear all counters */
 348                 for (i = 0; i < STAT_SIZE; i++)
 349                         readl(&regs->stat[i]);
 350
 351                 /* Setup RxBD space */
 352                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 353
 354                 for (i = 0; i < RX_BUF; i++) {
 355                         priv->rx_bd[i].status = 0xF0000000;
 356                         priv->rx_bd[i].addr =
 357                                         ((ulong)(priv->rxbuffers) +
 358                                                         (i * PKTSIZE_ALIGN));
 359                 }
 360                 /* WRAP bit to last BD */
 361                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 362                 /* Write RxBDs to IP */
 363                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 364
 365                 /* Setup for DMA Configuration register */
 366                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 367
 368                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 369                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 370
 371                 /* Disable the second priority queue */
 372                 dummy_tx_bd->addr = 0;
 373                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 374                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 375                                 ZYNQ_GEM_TXBUF_USED_MASK;
 376
 377                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 378                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 379                 dummy_rx_bd->status = 0;
 380                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 381                                    sizeof(dummy_tx_bd));
 382                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 383                                    sizeof(dummy_rx_bd));
 384
 385                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 386                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 387
 388                 priv->init++;
 389         }
 390
 391         ret = phy_detection(dev);
 392         if (ret) {
 393                 printf("GEM PHY init failed\n");
 394                 return ret;
 395         }
 396
 397         /* interface - look at tsec */
 398         phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 399                              priv->interface);
 400
 401         phydev->supported = supported | ADVERTISED_Pause |
 402                             ADVERTISED_Asym_Pause;
 403         phydev->advertising = phydev->supported;
 404         priv->phydev = phydev;
 405         phy_config(phydev);
 406         phy_startup(phydev);
 407
 408         if (!phydev->link) {
 409                 printf("%s: No link.\n", phydev->dev->name);
 410                 return -1;
 411         }
 412
 413         switch (phydev->speed) {
 414         case SPEED_1000:
 415                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 416                        &regs->nwcfg);
 417                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 418                 break;
 419         case SPEED_100:
 420                 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
 421                        &regs->nwcfg);
 422                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 423                 break;
 424         case SPEED_10:
 425                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 426                 break;
 427         }
 428
 429         /* Change the rclk and clk only not using EMIO interface */
 430         if (!priv->emio)
 431                 zynq_slcr_gem_clk_setup(dev->iobase !=
 432                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 433
 434         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 435                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 436
 437         return 0;
 438 }
 439
 440 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 441                         bool set, unsigned int timeout)
 442 {
 443         u32 val;
 444         unsigned long start = get_timer(0);
 445
 446         while (1) {
 447                 val = readl(reg);
 448
 449                 if (!set)
 450                         val = ~val;
 451
 452                 if ((val & mask) == mask)
 453                         return 0;
 454
 455                 if (get_timer(start) > timeout)
 456                         break;
 457
 458                 udelay(1);
 459         }
 460
 461         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
 462               func, reg, mask, set);
 463
 464         return -ETIMEDOUT;
 465 }
 466
 467 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
 468 {
 469         u32 addr, size;
 470         struct zynq_gem_priv *priv = dev->priv;
 471         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 472         struct emac_bd *current_bd = &priv->tx_bd[1];
 473
 474         /* Setup Tx BD */
 475         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 476
 477         priv->tx_bd->addr = (ulong)ptr;
 478         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 479                                ZYNQ_GEM_TXBUF_LAST_MASK;
 480         /* Dummy descriptor to mark it as the last in descriptor chain */
 481         current_bd->addr = 0x0;
 482         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 483                              ZYNQ_GEM_TXBUF_LAST_MASK|
 484                              ZYNQ_GEM_TXBUF_USED_MASK;
 485
 486         /* setup BD */
 487         writel((ulong)priv->tx_bd, &regs->txqbase);
 488
 489         addr = (ulong) ptr;
 490         addr &= ~(ARCH_DMA_MINALIGN - 1);
 491         size = roundup(len, ARCH_DMA_MINALIGN);
 492         flush_dcache_range(addr, addr + size);
 493
 494         addr = (ulong)priv->rxbuffers;
 495         addr &= ~(ARCH_DMA_MINALIGN - 1);
 496         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 497         flush_dcache_range(addr, addr + size);
 498         barrier();
 499
 500         /* Start transmit */
 501         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 502
 503         /* Read TX BD status */
 504         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 505                 printf("TX buffers exhausted in mid frame\n");
 506
 507         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 508                             true, 20000);
 509 }
 510
 511 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 512 static int zynq_gem_recv(struct eth_device *dev)
 513 {
 514         int frame_len;
 515         struct zynq_gem_priv *priv = dev->priv;
 516         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 517         struct emac_bd *first_bd;
 518
 519         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 520                 return 0;
 521
 522         if (!(current_bd->status &
 523                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 524                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 525                 return 0;
 526         }
 527
 528         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 529         if (frame_len) {
 530                 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 531                 addr &= ~(ARCH_DMA_MINALIGN - 1);
 532
 533                 net_process_received_packet((u8 *)(ulong)addr, frame_len);
 534
 535                 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
 536                         priv->rx_first_buf = priv->rxbd_current;
 537                 else {
 538                         current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 539                         current_bd->status = 0xF0000000; /* FIXME */
 540                 }
 541
 542                 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 543                         first_bd = &priv->rx_bd[priv->rx_first_buf];
 544                         first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 545                         first_bd->status = 0xF0000000;
 546                 }
 547
 548                 if ((++priv->rxbd_current) >= RX_BUF)
 549                         priv->rxbd_current = 0;
 550         }
 551
 552         return frame_len;
 553 }
 554
 555 static void zynq_gem_halt(struct eth_device *dev)
 556 {
 557         struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 558
 559         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 560                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 561 }
 562
 563 static int zynq_gem_miiphyread(const char *devname, uchar addr,
 564                                                         uchar reg, ushort *val)
 565 {
 566         struct eth_device *dev = eth_get_dev();
 567         struct zynq_gem_priv *priv = dev->priv;
 568         int ret;
 569
 570         ret = phyread(priv, addr, reg, val);
 571         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
 572         return ret;
 573 }
 574
 575 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
 576                                                         uchar reg, ushort val)
 577 {
 578         struct eth_device *dev = eth_get_dev();
 579         struct zynq_gem_priv *priv = dev->priv;
 580
 581         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
 582         return phywrite(priv, addr, reg, val);
 583 }
 584
 585 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
 586                         int phy_addr, u32 emio)
 587 {
 588         struct eth_device *dev;
 589         struct zynq_gem_priv *priv;
 590         void *bd_space;
 591
 592         dev = calloc(1, sizeof(*dev));
 593         if (dev == NULL)
 594                 return -1;
 595
 596         dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
 597         if (dev->priv == NULL) {
 598                 free(dev);
 599                 return -1;
 600         }
 601         priv = dev->priv;
 602
 603         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 604         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 605         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 606
 607         /* Align bd_space to MMU_SECTION_SHIFT */
 608         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 609         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 610                                         BD_SPACE, DCACHE_OFF);
 611
 612         /* Initialize the bd spaces for tx and rx bd's */
 613         priv->tx_bd = (struct emac_bd *)bd_space;
 614         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 615
 616         priv->phyaddr = phy_addr;
 617         priv->emio = emio;
 618
 619 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
 620         priv->interface = PHY_INTERFACE_MODE_MII;
 621 #else
 622         priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
 623 #endif
 624
 625         sprintf(dev->name, "Gem.%lx", base_addr);
 626
 627         dev->iobase = base_addr;
 628         priv->iobase = (struct zynq_gem_regs *)base_addr;
 629
 630         dev->init = zynq_gem_init;
 631         dev->halt = zynq_gem_halt;
 632         dev->send = zynq_gem_send;
 633         dev->recv = zynq_gem_recv;
 634         dev->write_hwaddr = zynq_gem_setup_mac;
 635
 636         eth_register(dev);
 637
 638         miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
 639         priv->bus = miiphy_get_dev_by_name(dev->name);
 640
 641         return 1;
 642 }
 643
 644 #if CONFIG_IS_ENABLED(OF_CONTROL)
 645 int zynq_gem_of_init(const void *blob)
 646 {
 647         int offset = 0;
 648         u32 ret = 0;
 649         u32 reg, phy_reg;
 650
 651         debug("ZYNQ GEM: Initialization\n");
 652
 653         do {
 654                 offset = fdt_node_offset_by_compatible(blob, offset,
 655                                         "xlnx,ps7-ethernet-1.00.a");
 656                 if (offset != -1) {
 657                         reg = fdtdec_get_addr(blob, offset, "reg");
 658                         if (reg != FDT_ADDR_T_NONE) {
 659                                 offset = fdtdec_lookup_phandle(blob, offset,
 660                                                                "phy-handle");
 661                                 if (offset != -1)
 662                                         phy_reg = fdtdec_get_addr(blob, offset,
 663                                                                   "reg");
 664                                 else
 665                                         phy_reg = 0;
 666
 667                                 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
 668                                       reg, phy_reg);
 669
 670                                 ret |= zynq_gem_initialize(NULL, reg,
 671                                                            phy_reg, 0);
 672
 673                         } else {
 674                                 debug("ZYNQ GEM: Can't get base address\n");
 675                                 return -1;
 676                         }
 677                 }
 678         } while (offset != -1);
 679
 680         return ret;
 681 }
 682 #endif