drivers/net/zynq_gem.c

   1 /*
   2  * (C) Copyright 2011 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * Based on Xilinx gmac driver:
   7  * (C) Copyright 2011 Xilinx
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <clk.h>
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <config.h>
  18 #include <console.h>
  19 #include <malloc.h>
  20 #include <asm/io.h>
  21 #include <phy.h>
  22 #include <miiphy.h>
  23 #include <wait_bit.h>
  24 #include <watchdog.h>
  25 #include <asm/system.h>
  26 #include <asm/arch/hardware.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <linux/errno.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 /* Bit/mask specification */
  33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK       0x40020000 /* operation mask bits */
  34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK     0x20000000 /* read operation */
  35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK     0x10000000 /* write operation */
  36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK      23 /* Shift bits for PHYAD */
  37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK      18 /* Shift bits for PHREG */
  38
  39 #define ZYNQ_GEM_RXBUF_EOF_MASK         0x00008000 /* End of frame. */
  40 #define ZYNQ_GEM_RXBUF_SOF_MASK         0x00004000 /* Start of frame. */
  41 #define ZYNQ_GEM_RXBUF_LEN_MASK         0x00003FFF /* Mask for length field */
  42
  43 #define ZYNQ_GEM_RXBUF_WRAP_MASK        0x00000002 /* Wrap bit, last BD */
  44 #define ZYNQ_GEM_RXBUF_NEW_MASK         0x00000001 /* Used bit.. */
  45 #define ZYNQ_GEM_RXBUF_ADD_MASK         0xFFFFFFFC /* Mask for address */
  46
  47 /* Wrap bit, last descriptor */
  48 #define ZYNQ_GEM_TXBUF_WRAP_MASK        0x40000000
  49 #define ZYNQ_GEM_TXBUF_LAST_MASK        0x00008000 /* Last buffer */
  50 #define ZYNQ_GEM_TXBUF_USED_MASK        0x80000000 /* Used by Hw */
  51
  52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK       0x00000008 /* Enable transmit */
  53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK       0x00000004 /* Enable receive */
  54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK       0x00000010 /* Enable MDIO port */
  55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK    0x00000200 /* Start tx (tx_go) */
  56
  57 #define ZYNQ_GEM_NWCFG_SPEED100         0x00000001 /* 100 Mbps operation */
  58 #define ZYNQ_GEM_NWCFG_SPEED1000        0x00000400 /* 1Gbps operation */
  59 #define ZYNQ_GEM_NWCFG_FDEN             0x00000002 /* Full Duplex mode */
  60 #define ZYNQ_GEM_NWCFG_FSREM            0x00020000 /* FCS removal */
  61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL       0x08000000 /* SGMII Enable */
  62 #define ZYNQ_GEM_NWCFG_PCS_SEL          0x00000800 /* PCS select */
  63 #ifdef CONFIG_ARM64
  64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x00100000 /* Div pclk by 64, max 160MHz */
  65 #else
  66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV        0x000c0000 /* Div pclk by 48, max 120MHz */
  67 #endif
  68
  69 #ifdef CONFIG_ARM64
  70 # define ZYNQ_GEM_DBUS_WIDTH    (1 << 21) /* 64 bit bus */
  71 #else
  72 # define ZYNQ_GEM_DBUS_WIDTH    (0 << 21) /* 32 bit bus */
  73 #endif
  74
  75 #define ZYNQ_GEM_NWCFG_INIT             (ZYNQ_GEM_DBUS_WIDTH | \
  76                                         ZYNQ_GEM_NWCFG_FDEN | \
  77                                         ZYNQ_GEM_NWCFG_FSREM | \
  78                                         ZYNQ_GEM_NWCFG_MDCCLKDIV)
  79
  80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK     0x00000004 /* PHY management idle */
  81
  82 #define ZYNQ_GEM_DMACR_BLENGTH          0x00000004 /* INCR4 AHB bursts */
  83 /* Use full configured addressable space (8 Kb) */
  84 #define ZYNQ_GEM_DMACR_RXSIZE           0x00000300
  85 /* Use full configured addressable space (4 Kb) */
  86 #define ZYNQ_GEM_DMACR_TXSIZE           0x00000400
  87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  88 #define ZYNQ_GEM_DMACR_RXBUF            0x00180000
  89
  90 #define ZYNQ_GEM_DMACR_INIT             (ZYNQ_GEM_DMACR_BLENGTH | \
  91                                         ZYNQ_GEM_DMACR_RXSIZE | \
  92                                         ZYNQ_GEM_DMACR_TXSIZE | \
  93                                         ZYNQ_GEM_DMACR_RXBUF)
  94
  95 #define ZYNQ_GEM_TSR_DONE               0x00000020 /* Tx done mask */
  96
  97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL      0x1000
  98
  99 /* Use MII register 1 (MII status register) to detect PHY */
 100 #define PHY_DETECT_REG  1
 101
 102 /* Mask used to verify certain PHY features (or register contents)
 103  * in the register above:
 104  *  0x1000: 10Mbps full duplex support
 105  *  0x0800: 10Mbps half duplex support
 106  *  0x0008: Auto-negotiation support
 107  */
 108 #define PHY_DETECT_MASK 0x1808
 109
 110 /* TX BD status masks */
 111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK      0x000007ff
 112 #define ZYNQ_GEM_TXBUF_EXHAUSTED        0x08000000
 113 #define ZYNQ_GEM_TXBUF_UNDERRUN         0x10000000
 114
 115 /* Clock frequencies for different speeds */
 116 #define ZYNQ_GEM_FREQUENCY_10   2500000UL
 117 #define ZYNQ_GEM_FREQUENCY_100  25000000UL
 118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
 119
 120 /* Device registers */
 121 struct zynq_gem_regs {
 122         u32 nwctrl; /* 0x0 - Network Control reg */
 123         u32 nwcfg; /* 0x4 - Network Config reg */
 124         u32 nwsr; /* 0x8 - Network Status reg */
 125         u32 reserved1;
 126         u32 dmacr; /* 0x10 - DMA Control reg */
 127         u32 txsr; /* 0x14 - TX Status reg */
 128         u32 rxqbase; /* 0x18 - RX Q Base address reg */
 129         u32 txqbase; /* 0x1c - TX Q Base address reg */
 130         u32 rxsr; /* 0x20 - RX Status reg */
 131         u32 reserved2[2];
 132         u32 idr; /* 0x2c - Interrupt Disable reg */
 133         u32 reserved3;
 134         u32 phymntnc; /* 0x34 - Phy Maintaince reg */
 135         u32 reserved4[18];
 136         u32 hashl; /* 0x80 - Hash Low address reg */
 137         u32 hashh; /* 0x84 - Hash High address reg */
 138 #define LADDR_LOW       0
 139 #define LADDR_HIGH      1
 140         u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 141         u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 142         u32 reserved6[18];
 143 #define STAT_SIZE       44
 144         u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 145         u32 reserved9[20];
 146         u32 pcscntrl;
 147         u32 reserved7[143];
 148         u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 149         u32 reserved8[15];
 150         u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 151 };
 152
 153 /* BD descriptors */
 154 struct emac_bd {
 155         u32 addr; /* Next descriptor pointer */
 156         u32 status;
 157 };
 158
 159 #define RX_BUF 32
 160 /* Page table entries are set to 1MB, or multiples of 1MB
 161  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 162  */
 163 #define BD_SPACE        0x100000
 164 /* BD separation space */
 165 #define BD_SEPRN_SPACE  (RX_BUF * sizeof(struct emac_bd))
 166
 167 /* Setup the first free TX descriptor */
 168 #define TX_FREE_DESC    2
 169
 170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 171 struct zynq_gem_priv {
 172         struct emac_bd *tx_bd;
 173         struct emac_bd *rx_bd;
 174         char *rxbuffers;
 175         u32 rxbd_current;
 176         u32 rx_first_buf;
 177         int phyaddr;
 178         u32 emio;
 179         int init;
 180         struct zynq_gem_regs *iobase;
 181         phy_interface_t interface;
 182         struct phy_device *phydev;
 183         int phy_of_handle;
 184         struct mii_dev *bus;
 185 #ifdef CONFIG_CLK_ZYNQMP
 186         struct clk clk;
 187 #endif
 188 };
 189
 190 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 191                         u32 op, u16 *data)
 192 {
 193         u32 mgtcr;
 194         struct zynq_gem_regs *regs = priv->iobase;
 195         int err;
 196
 197         err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
 198                             true, 20000, true);
 199         if (err)
 200                 return err;
 201
 202         /* Construct mgtcr mask for the operation */
 203         mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
 204                 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
 205                 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
 206
 207         /* Write mgtcr and wait for completion */
 208         writel(mgtcr, &regs->phymntnc);
 209
 210         err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
 211                             true, 20000, true);
 212         if (err)
 213                 return err;
 214
 215         if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 216                 *data = readl(&regs->phymntnc);
 217
 218         return 0;
 219 }
 220
 221 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 222                    u32 regnum, u16 *val)
 223 {
 224         u32 ret;
 225
 226         ret = phy_setup_op(priv, phy_addr, regnum,
 227                            ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
 228
 229         if (!ret)
 230                 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
 231                       phy_addr, regnum, *val);
 232
 233         return ret;
 234 }
 235
 236 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 237                     u32 regnum, u16 data)
 238 {
 239         debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
 240               regnum, data);
 241
 242         return phy_setup_op(priv, phy_addr, regnum,
 243                             ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 244 }
 245
 246 static int phy_detection(struct udevice *dev)
 247 {
 248         int i;
 249         u16 phyreg;
 250         struct zynq_gem_priv *priv = dev->priv;
 251
 252         if (priv->phyaddr != -1) {
 253                 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
 254                 if ((phyreg != 0xFFFF) &&
 255                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 256                         /* Found a valid PHY address */
 257                         debug("Default phy address %d is valid\n",
 258                               priv->phyaddr);
 259                         return 0;
 260                 } else {
 261                         debug("PHY address is not setup correctly %d\n",
 262                               priv->phyaddr);
 263                         priv->phyaddr = -1;
 264                 }
 265         }
 266
 267         debug("detecting phy address\n");
 268         if (priv->phyaddr == -1) {
 269                 /* detect the PHY address */
 270                 for (i = 31; i >= 0; i--) {
 271                         phyread(priv, i, PHY_DETECT_REG, &phyreg);
 272                         if ((phyreg != 0xFFFF) &&
 273                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 274                                 /* Found a valid PHY address */
 275                                 priv->phyaddr = i;
 276                                 debug("Found valid phy address, %d\n", i);
 277                                 return 0;
 278                         }
 279                 }
 280         }
 281         printf("PHY is not detected\n");
 282         return -1;
 283 }
 284
 285 static int zynq_gem_setup_mac(struct udevice *dev)
 286 {
 287         u32 i, macaddrlow, macaddrhigh;
 288         struct eth_pdata *pdata = dev_get_platdata(dev);
 289         struct zynq_gem_priv *priv = dev_get_priv(dev);
 290         struct zynq_gem_regs *regs = priv->iobase;
 291
 292         /* Set the MAC bits [31:0] in BOT */
 293         macaddrlow = pdata->enetaddr[0];
 294         macaddrlow |= pdata->enetaddr[1] << 8;
 295         macaddrlow |= pdata->enetaddr[2] << 16;
 296         macaddrlow |= pdata->enetaddr[3] << 24;
 297
 298         /* Set MAC bits [47:32] in TOP */
 299         macaddrhigh = pdata->enetaddr[4];
 300         macaddrhigh |= pdata->enetaddr[5] << 8;
 301
 302         for (i = 0; i < 4; i++) {
 303                 writel(0, &regs->laddr[i][LADDR_LOW]);
 304                 writel(0, &regs->laddr[i][LADDR_HIGH]);
 305                 /* Do not use MATCHx register */
 306                 writel(0, &regs->match[i]);
 307         }
 308
 309         writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
 310         writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
 311
 312         return 0;
 313 }
 314
 315 static int zynq_phy_init(struct udevice *dev)
 316 {
 317         int ret;
 318         struct zynq_gem_priv *priv = dev_get_priv(dev);
 319         struct zynq_gem_regs *regs = priv->iobase;
 320         const u32 supported = SUPPORTED_10baseT_Half |
 321                         SUPPORTED_10baseT_Full |
 322                         SUPPORTED_100baseT_Half |
 323                         SUPPORTED_100baseT_Full |
 324                         SUPPORTED_1000baseT_Half |
 325                         SUPPORTED_1000baseT_Full;
 326
 327         /* Enable only MDIO bus */
 328         writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 329
 330         if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
 331                 ret = phy_detection(dev);
 332                 if (ret) {
 333                         printf("GEM PHY init failed\n");
 334                         return ret;
 335                 }
 336         }
 337
 338         priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 339                                    priv->interface);
 340         if (!priv->phydev)
 341                 return -ENODEV;
 342
 343         priv->phydev->supported = supported | ADVERTISED_Pause |
 344                                   ADVERTISED_Asym_Pause;
 345         priv->phydev->advertising = priv->phydev->supported;
 346
 347         if (priv->phy_of_handle > 0)
 348                 priv->phydev->dev->of_offset = priv->phy_of_handle;
 349
 350         return phy_config(priv->phydev);
 351 }
 352
 353 static int zynq_gem_init(struct udevice *dev)
 354 {
 355         u32 i, nwconfig;
 356         int ret;
 357         unsigned long clk_rate = 0;
 358         struct zynq_gem_priv *priv = dev_get_priv(dev);
 359         struct zynq_gem_regs *regs = priv->iobase;
 360         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
 361         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 362
 363         if (!priv->init) {
 364                 /* Disable all interrupts */
 365                 writel(0xFFFFFFFF, &regs->idr);
 366
 367                 /* Disable the receiver & transmitter */
 368                 writel(0, &regs->nwctrl);
 369                 writel(0, &regs->txsr);
 370                 writel(0, &regs->rxsr);
 371                 writel(0, &regs->phymntnc);
 372
 373                 /* Clear the Hash registers for the mac address
 374                  * pointed by AddressPtr
 375                  */
 376                 writel(0x0, &regs->hashl);
 377                 /* Write bits [63:32] in TOP */
 378                 writel(0x0, &regs->hashh);
 379
 380                 /* Clear all counters */
 381                 for (i = 0; i < STAT_SIZE; i++)
 382                         readl(&regs->stat[i]);
 383
 384                 /* Setup RxBD space */
 385                 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 386
 387                 for (i = 0; i < RX_BUF; i++) {
 388                         priv->rx_bd[i].status = 0xF0000000;
 389                         priv->rx_bd[i].addr =
 390                                         ((ulong)(priv->rxbuffers) +
 391                                                         (i * PKTSIZE_ALIGN));
 392                 }
 393                 /* WRAP bit to last BD */
 394                 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 395                 /* Write RxBDs to IP */
 396                 writel((ulong)priv->rx_bd, &regs->rxqbase);
 397
 398                 /* Setup for DMA Configuration register */
 399                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 400
 401                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
 402                 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 403
 404                 /* Disable the second priority queue */
 405                 dummy_tx_bd->addr = 0;
 406                 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 407                                 ZYNQ_GEM_TXBUF_LAST_MASK|
 408                                 ZYNQ_GEM_TXBUF_USED_MASK;
 409
 410                 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
 411                                 ZYNQ_GEM_RXBUF_NEW_MASK;
 412                 dummy_rx_bd->status = 0;
 413                 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
 414                                    sizeof(dummy_tx_bd));
 415                 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
 416                                    sizeof(dummy_rx_bd));
 417
 418                 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
 419                 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
 420
 421                 priv->init++;
 422         }
 423
 424         ret = phy_startup(priv->phydev);
 425         if (ret)
 426                 return ret;
 427
 428         if (!priv->phydev->link) {
 429                 printf("%s: No link.\n", priv->phydev->dev->name);
 430                 return -1;
 431         }
 432
 433         nwconfig = ZYNQ_GEM_NWCFG_INIT;
 434
 435         if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
 436                 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 437                             ZYNQ_GEM_NWCFG_PCS_SEL;
 438 #ifdef CONFIG_ARM64
 439                 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
 440                        &regs->pcscntrl);
 441 #endif
 442         }
 443
 444         switch (priv->phydev->speed) {
 445         case SPEED_1000:
 446                 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
 447                        &regs->nwcfg);
 448                 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 449                 break;
 450         case SPEED_100:
 451                 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
 452                        &regs->nwcfg);
 453                 clk_rate = ZYNQ_GEM_FREQUENCY_100;
 454                 break;
 455         case SPEED_10:
 456                 clk_rate = ZYNQ_GEM_FREQUENCY_10;
 457                 break;
 458         }
 459
 460         /* Change the rclk and clk only not using EMIO interface */
 461         if (!priv->emio)
 462 #ifndef CONFIG_CLK_ZYNQMP
 463                 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 464                                         ZYNQ_GEM_BASEADDR0, clk_rate);
 465 #else
 466                 ret = clk_set_rate(&priv->clk, clk_rate);
 467                 if (IS_ERR_VALUE(ret))
 468                         return -1;
 469 #endif
 470
 471         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 472                                         ZYNQ_GEM_NWCTRL_TXEN_MASK);
 473
 474         return 0;
 475 }
 476
 477 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 478 {
 479         u32 addr, size;
 480         struct zynq_gem_priv *priv = dev_get_priv(dev);
 481         struct zynq_gem_regs *regs = priv->iobase;
 482         struct emac_bd *current_bd = &priv->tx_bd[1];
 483
 484         /* Setup Tx BD */
 485         memset(priv->tx_bd, 0, sizeof(struct emac_bd));
 486
 487         priv->tx_bd->addr = (ulong)ptr;
 488         priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
 489                                ZYNQ_GEM_TXBUF_LAST_MASK;
 490         /* Dummy descriptor to mark it as the last in descriptor chain */
 491         current_bd->addr = 0x0;
 492         current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
 493                              ZYNQ_GEM_TXBUF_LAST_MASK|
 494                              ZYNQ_GEM_TXBUF_USED_MASK;
 495
 496         /* setup BD */
 497         writel((ulong)priv->tx_bd, &regs->txqbase);
 498
 499         addr = (ulong) ptr;
 500         addr &= ~(ARCH_DMA_MINALIGN - 1);
 501         size = roundup(len, ARCH_DMA_MINALIGN);
 502         flush_dcache_range(addr, addr + size);
 503
 504         addr = (ulong)priv->rxbuffers;
 505         addr &= ~(ARCH_DMA_MINALIGN - 1);
 506         size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
 507         flush_dcache_range(addr, addr + size);
 508         barrier();
 509
 510         /* Start transmit */
 511         setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 512
 513         /* Read TX BD status */
 514         if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 515                 printf("TX buffers exhausted in mid frame\n");
 516
 517         return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
 518                             true, 20000, true);
 519 }
 520
 521 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 522 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 523 {
 524         int frame_len;
 525         u32 addr;
 526         struct zynq_gem_priv *priv = dev_get_priv(dev);
 527         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 528
 529         if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
 530                 return -1;
 531
 532         if (!(current_bd->status &
 533                         (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 534                 printf("GEM: SOF or EOF not set for last buffer received!\n");
 535                 return -1;
 536         }
 537
 538         frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 539         if (!frame_len) {
 540                 printf("%s: Zero size packet?\n", __func__);
 541                 return -1;
 542         }
 543
 544         addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 545         addr &= ~(ARCH_DMA_MINALIGN - 1);
 546         *packetp = (uchar *)(uintptr_t)addr;
 547
 548         return frame_len;
 549 }
 550
 551 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
 552 {
 553         struct zynq_gem_priv *priv = dev_get_priv(dev);
 554         struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
 555         struct emac_bd *first_bd;
 556
 557         if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
 558                 priv->rx_first_buf = priv->rxbd_current;
 559         } else {
 560                 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 561                 current_bd->status = 0xF0000000; /* FIXME */
 562         }
 563
 564         if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
 565                 first_bd = &priv->rx_bd[priv->rx_first_buf];
 566                 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
 567                 first_bd->status = 0xF0000000;
 568         }
 569
 570         if ((++priv->rxbd_current) >= RX_BUF)
 571                 priv->rxbd_current = 0;
 572
 573         return 0;
 574 }
 575
 576 static void zynq_gem_halt(struct udevice *dev)
 577 {
 578         struct zynq_gem_priv *priv = dev_get_priv(dev);
 579         struct zynq_gem_regs *regs = priv->iobase;
 580
 581         clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 582                                                 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 583 }
 584
 585 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 586 {
 587         return -ENOSYS;
 588 }
 589
 590 static int zynq_gem_read_rom_mac(struct udevice *dev)
 591 {
 592         int retval;
 593         struct eth_pdata *pdata = dev_get_platdata(dev);
 594
 595         retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
 596         if (retval == -ENOSYS)
 597                 retval = 0;
 598
 599         return retval;
 600 }
 601
 602 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
 603                                 int devad, int reg)
 604 {
 605         struct zynq_gem_priv *priv = bus->priv;
 606         int ret;
 607         u16 val;
 608
 609         ret = phyread(priv, addr, reg, &val);
 610         debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
 611         return val;
 612 }
 613
 614 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
 615                                  int reg, u16 value)
 616 {
 617         struct zynq_gem_priv *priv = bus->priv;
 618
 619         debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
 620         return phywrite(priv, addr, reg, value);
 621 }
 622
 623 static int zynq_gem_probe(struct udevice *dev)
 624 {
 625         void *bd_space;
 626         struct zynq_gem_priv *priv = dev_get_priv(dev);
 627         int ret;
 628
 629         /* Align rxbuffers to ARCH_DMA_MINALIGN */
 630         priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
 631         memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 632
 633         /* Align bd_space to MMU_SECTION_SHIFT */
 634         bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 635         mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 636                                         BD_SPACE, DCACHE_OFF);
 637
 638         /* Initialize the bd spaces for tx and rx bd's */
 639         priv->tx_bd = (struct emac_bd *)bd_space;
 640         priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 641
 642 #ifdef CONFIG_CLK_ZYNQMP
 643         ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
 644         if (ret < 0) {
 645                 dev_err(dev, "failed to get clock\n");
 646                 return -EINVAL;
 647         }
 648 #endif
 649
 650         priv->bus = mdio_alloc();
 651         priv->bus->read = zynq_gem_miiphy_read;
 652         priv->bus->write = zynq_gem_miiphy_write;
 653         priv->bus->priv = priv;
 654
 655         ret = mdio_register_seq(priv->bus, dev->seq);
 656         if (ret)
 657                 return ret;
 658
 659         return zynq_phy_init(dev);
 660 }
 661
 662 static int zynq_gem_remove(struct udevice *dev)
 663 {
 664         struct zynq_gem_priv *priv = dev_get_priv(dev);
 665
 666         free(priv->phydev);
 667         mdio_unregister(priv->bus);
 668         mdio_free(priv->bus);
 669
 670         return 0;
 671 }
 672
 673 static const struct eth_ops zynq_gem_ops = {
 674         .start                  = zynq_gem_init,
 675         .send                   = zynq_gem_send,
 676         .recv                   = zynq_gem_recv,
 677         .free_pkt               = zynq_gem_free_pkt,
 678         .stop                   = zynq_gem_halt,
 679         .write_hwaddr           = zynq_gem_setup_mac,
 680         .read_rom_hwaddr        = zynq_gem_read_rom_mac,
 681 };
 682
 683 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 684 {
 685         struct eth_pdata *pdata = dev_get_platdata(dev);
 686         struct zynq_gem_priv *priv = dev_get_priv(dev);
 687         const char *phy_mode;
 688
 689         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 690         priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
 691         /* Hardcode for now */
 692         priv->emio = 0;
 693         priv->phyaddr = -1;
 694
 695         priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
 696                                         dev->of_offset, "phy-handle");
 697         if (priv->phy_of_handle > 0)
 698                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
 699                                         priv->phy_of_handle, "reg", -1);
 700
 701         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 702         if (phy_mode)
 703                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 704         if (pdata->phy_interface == -1) {
 705                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 706                 return -EINVAL;
 707         }
 708         priv->interface = pdata->phy_interface;
 709
 710         priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
 711
 712         printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
 713                priv->phyaddr, phy_string_for_interface(priv->interface));
 714
 715         return 0;
 716 }
 717
 718 static const struct udevice_id zynq_gem_ids[] = {
 719         { .compatible = "cdns,zynqmp-gem" },
 720         { .compatible = "cdns,zynq-gem" },
 721         { .compatible = "cdns,gem" },
 722         { }
 723 };
 724
 725 U_BOOT_DRIVER(zynq_gem) = {
 726         .name   = "zynq_gem",
 727         .id     = UCLASS_ETH,
 728         .of_match = zynq_gem_ids,
 729         .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
 730         .probe  = zynq_gem_probe,
 731         .remove = zynq_gem_remove,
 732         .ops    = &zynq_gem_ops,
 733         .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
 734         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 735 };