drivers/pci/fsl_pci_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /*
  24  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  25  *
  26  * Initialize controller and call the common driver/pci pci_hose_scan to
  27  * scan for bridges and devices.
  28  *
  29  * Hose fields which need to be pre-initialized by board specific code:
  30  *   regions[]
  31  *   first_busno
  32  *
  33  * Fields updated:
  34  *   last_busno
  35  */
  36
  37 #include <pci.h>
  38 #include <asm/fsl_pci.h>
  39
  40 /* Freescale-specific PCI config registers */
  41 #define FSL_PCI_PBFR            0x44
  42 #define FSL_PCIE_CAP_ID         0x4c
  43 #define FSL_PCIE_CFG_RDY        0x4b0
  44
  45 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  46                                 pci_dev_t dev, int sub_bus);
  47 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  48                                 pci_dev_t dev, int sub_bus);
  49 void pciauto_config_init(struct pci_controller *hose);
  50
  51 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  52 #define CONFIG_SYS_PCI_MEMORY_BUS 0
  53 #endif
  54
  55 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  56 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  57 #endif
  58
  59 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  60 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  61 #endif
  62
  63 static int fsl_pci_setup_inbound_windows(struct pci_region *r)
  64 {
  65         struct pci_region *rgn_base = r;
  66         u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
  67
  68         phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  69         pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  70         pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
  71
  72         debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  73                 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  74         pci_set_region(r++, bus_start, phys_start, pci_sz,
  75                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  76                         PCI_REGION_PREFETCH);
  77
  78         sz -= pci_sz;
  79         bus_start += pci_sz;
  80         phys_start += pci_sz;
  81
  82         pci_sz = 1ull << __ilog2_u64(sz);
  83         if (sz) {
  84                 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  85                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  86                 pci_set_region(r++, bus_start, phys_start, pci_sz,
  87                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  88                                 PCI_REGION_PREFETCH);
  89                 sz -= pci_sz;
  90                 bus_start += pci_sz;
  91                 phys_start += pci_sz;
  92         }
  93
  94 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  95         /*
  96          * On 64-bit capable systems, set up a mapping for all of DRAM
  97          * in high pci address space.
  98          */
  99         pci_sz = 1ull << __ilog2_u64(gd->ram_size);
 100         /* round up to the next largest power of two */
 101         if (gd->ram_size > pci_sz)
 102                 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
 103         debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
 104                 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
 105                 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
 106                 (u64)pci_sz);
 107         pci_set_region(r++,
 108                         CONFIG_SYS_PCI64_MEMORY_BUS,
 109                         CONFIG_SYS_PCI_MEMORY_PHYS,
 110                         pci_sz,
 111                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 112                         PCI_REGION_PREFETCH);
 113 #else
 114         pci_sz = 1ull << __ilog2_u64(sz);
 115         if (sz) {
 116                 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
 117                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 118                 pci_set_region(r++, bus_start, phys_start, pci_sz,
 119                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 120                                 PCI_REGION_PREFETCH);
 121                 sz -= pci_sz;
 122                 bus_start += pci_sz;
 123                 phys_start += pci_sz;
 124         }
 125 #endif
 126
 127 #ifdef CONFIG_PHYS_64BIT
 128         if (sz && (((u64)gd->ram_size) < (1ull << 32)))
 129                 printf("Was not able to map all of memory via "
 130                         "inbound windows -- %lld remaining\n", sz);
 131 #endif
 132
 133         return r - rgn_base;
 134 }
 135
 136 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 137 {
 138         u16 temp16;
 139         u32 temp32;
 140         int enabled, r, inbound = 0;
 141         u16 ltssm;
 142         u8 temp8, pcie_cap;
 143         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
 144         struct pci_region *reg = hose->regions + hose->region_count;
 145         pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 146
 147         /* Initialize ATMU registers based on hose regions and flags */
 148         volatile pot_t *po = &pci->pot[1];      /* skip 0 */
 149         volatile pit_t *pi = &pci->pit[0];      /* ranges from: 3 to 1 */
 150
 151 #ifdef DEBUG
 152         int neg_link_w;
 153 #endif
 154
 155         pci_setup_indirect(hose, cfg_addr, cfg_data);
 156
 157         /* inbound */
 158         reg += fsl_pci_setup_inbound_windows(reg);
 159
 160         hose->region_count = reg - hose->regions;
 161
 162         for (r=0; r<hose->region_count; r++) {
 163                 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
 164                 if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
 165                         u32 flag = PIWAR_EN | PIWAR_LOCAL |
 166                                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 167                         pi->pitar = (hose->regions[r].phys_start >> 12);
 168                         pi->piwbar = (hose->regions[r].bus_start >> 12);
 169 #ifdef CONFIG_SYS_PCI_64BIT
 170                         pi->piwbear = (hose->regions[r].bus_start >> 44);
 171 #else
 172                         pi->piwbear = 0;
 173 #endif
 174                         if (hose->regions[r].flags & PCI_REGION_PREFETCH)
 175                                 flag |= PIWAR_PF;
 176                         pi->piwar = flag | sz;
 177                         pi++;
 178                         inbound = hose->regions[r].size > 0;
 179                 } else { /* Outbound */
 180                         po->powbar = (hose->regions[r].phys_start >> 12);
 181                         po->potar = (hose->regions[r].bus_start >> 12);
 182 #ifdef CONFIG_SYS_PCI_64BIT
 183                         po->potear = (hose->regions[r].bus_start >> 44);
 184 #else
 185                         po->potear = 0;
 186 #endif
 187                         if (hose->regions[r].flags & PCI_REGION_IO)
 188                                 po->powar = POWAR_EN | sz |
 189                                         POWAR_IO_READ | POWAR_IO_WRITE;
 190                         else
 191                                 po->powar = POWAR_EN | sz |
 192                                         POWAR_MEM_READ | POWAR_MEM_WRITE;
 193                         po++;
 194                 }
 195         }
 196
 197         /* see if we are a PCIe or PCI controller */
 198         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 199
 200         pci_register_hose(hose);
 201         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
 202         hose->current_busno = hose->first_busno;
 203
 204         pci->pedr = 0xffffffff;         /* Clear any errors */
 205         pci->peer = ~0x20140;           /* Enable All Error Interupts except
 206                                          * - Master abort (pci)
 207                                          * - Master PERR (pci)
 208                                          * - ICCA (PCIe)
 209                                          */
 210         pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
 211         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
 212         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 213
 214         if (pcie_cap == PCI_CAP_ID_EXP) {
 215                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 216                 enabled = ltssm >= PCI_LTSSM_L0;
 217
 218 #ifdef CONFIG_FSL_PCIE_RESET
 219                 if (ltssm == 1) {
 220                         int i;
 221                         debug("....PCIe link error. "
 222                               "LTSSM=0x%02x.", ltssm);
 223                         pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
 224                         temp32 = pci->pdb_stat;
 225                         udelay(100);
 226                         debug("  Asserting PCIe reset @%x = %x\n",
 227                               &pci->pdb_stat, pci->pdb_stat);
 228                         pci->pdb_stat &= ~0x08000000; /* clear reset */
 229                         asm("sync;isync");
 230                         for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
 231                                 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
 232                                                         &ltssm);
 233                                 udelay(1000);
 234                                 debug("....PCIe link error. "
 235                                       "LTSSM=0x%02x.\n", ltssm);
 236                         }
 237                         enabled = ltssm >= PCI_LTSSM_L0;
 238                 }
 239 #endif
 240
 241                 if (!enabled) {
 242                         debug("....PCIE link error.  Skipping scan."
 243                               "LTSSM=0x%02x\n", ltssm);
 244                         hose->last_busno = hose->first_busno;
 245                         return;
 246                 }
 247
 248                 pci->pme_msg_det = 0xffffffff;
 249                 pci->pme_msg_int_en = 0xffffffff;
 250 #ifdef DEBUG
 251                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 252                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 253                 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 254                       ltssm, neg_link_w);
 255 #endif
 256                 hose->current_busno++; /* Start scan with secondary */
 257                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 258         }
 259
 260         /* Use generic setup_device to initialize standard pci regs,
 261          * but do not allocate any windows since any BAR found (such
 262          * as PCSRBAR) is not in this cpu's memory space.
 263          */
 264         pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 265                              hose->pci_prefetch, hose->pci_io);
 266
 267         if (inbound) {
 268                 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
 269                 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 270                                            temp16 | PCI_COMMAND_MEMORY);
 271         }
 272
 273 #ifndef CONFIG_PCI_NOSCAN
 274         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
 275
 276         /* Programming Interface (PCI_CLASS_PROG)
 277          * 0 == pci host or pcie root-complex,
 278          * 1 == pci agent or pcie end-point
 279          */
 280         if (!temp8) {
 281                 printf("               Scanning PCI bus %02x\n",
 282                         hose->current_busno);
 283                 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
 284         } else {
 285                 debug("               Not scanning PCI bus %02x. PI=%x\n",
 286                         hose->current_busno, temp8);
 287                 hose->last_busno = hose->current_busno;
 288         }
 289
 290         /* if we are PCIe - update limit regs and subordinate busno
 291          * for the virtual P2P bridge
 292          */
 293         if (pcie_cap == PCI_CAP_ID_EXP) {
 294                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 295         }
 296 #else
 297         hose->last_busno = hose->current_busno;
 298 #endif
 299
 300         /* Clear all error indications */
 301         if (pcie_cap == PCI_CAP_ID_EXP)
 302                 pci->pme_msg_det = 0xffffffff;
 303         pci->pedr = 0xffffffff;
 304
 305         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 306         if (temp16) {
 307                 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
 308         }
 309
 310         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 311         if (temp16) {
 312                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 313         }
 314 }
 315
 316 /* Enable inbound PCI config cycles for agent/endpoint interface */
 317 void fsl_pci_config_unlock(struct pci_controller *hose)
 318 {
 319         pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
 320         u8 agent;
 321         u8 pcie_cap;
 322         u16 pbfr;
 323
 324         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
 325         if (!agent)
 326                 return;
 327
 328         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 329         if (pcie_cap != 0x0) {
 330                 /* PCIe - set CFG_READY bit of Configuration Ready Register */
 331                 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
 332         } else {
 333                 /* PCI - clear ACL bit of PBFR */
 334                 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
 335                 pbfr &= ~0x20;
 336                 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
 337         }
 338 }
 339
 340 #ifdef CONFIG_OF_BOARD_SETUP
 341 #include <libfdt.h>
 342 #include <fdt_support.h>
 343
 344 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 345                         struct pci_controller *hose)
 346 {
 347         int off = fdt_path_offset(blob, pci_alias);
 348
 349         if (off >= 0) {
 350                 u32 bus_range[2];
 351
 352                 bus_range[0] = 0;
 353                 bus_range[1] = hose->last_busno - hose->first_busno;
 354                 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
 355                 fdt_pci_dma_ranges(blob, off, hose);
 356         }
 357 }
 358 #endif